JPS58214924A - Integrated circuit element - Google Patents

Abstract

PURPOSE:To eliminate a terminal exclusively used for initialization and to decrease the number of terminals of an IC, by providing a delay circuit containing plural non-reverse buffers, etc. and a power-on reset pulse generating circuit to the power supply terminal, etc. of an IC element. CONSTITUTION:A delay circuit containing plural non-reverse buffers, etc. connected with input terminals, power supply terminals, etc. is provided to the power supply terminal, etc. of an IC element together with a power-on reset pulse generating circuit which generates an output during the rise of the power supply voltage and then stops the output with the output of the non-reverse buffer on the final stage of the delay circuit. For instance, when an IC power supply is supplied, the output of a non-reverse buffer 32a is set at ''1'' when the IC power supply voltage VCC exceeds the minimum working voltage level of the IC element. At the same time, a reset preference type flip-flop 33 of the power-on reset generating circuit is set. Then the outputs of non-inverse buffers 32b-32n are set at ''1'' when the delay time due to an input capacity Cin, output capacity Cout, etc. elapses. This output of ''1'' resets the flip-flop 33.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device in which initial settings of the integrated circuit device at power-on are realized without using a dedicated reset terminal.

Generally integrated circuits (hereinafter referred to as ICs), especially digital I
In C, it is necessary to initialize the inside of the IC (power-on reset) when the power is turned on. Conventionally, this initial setting is performed by providing a power-on reset exclusive terminal RIThSPl:T in the IC 10 as shown in FIG. For example, as shown in FIG. 2, a voltage with a gradual rising waveform is applied to the power-on reset dedicated terminal 1sET, and a reset pulse as shown in FIG. 2 is generated via an inverting buffer having a threshold value Sl. This is achieved by supplying the ICC internally. Here, the power-on reset dedicated terminal RESHT
It was literally a terminal only for initial settings and could not be used for any other purpose.

An object of the present invention is to eliminate such a power-on reset exclusive terminal and reduce the number of IC terminals. Examples will be described in detail below.

FIG. 3 is a block diagram of main parts of an embodiment of the present invention, in which 30 is an IC, 31 is a power supply terminal, 32a to 32n are non-inverting wires, 1. B, G are the input terminals, power terminal, ground terminal, 33Fi reset priority type flip-flop, S,
R and Q are the set input terminal, reset input terminal, and output terminal, B and G are the power supply terminal and ground terminal, and vac is the IC.
The power supply voltage is .

Inside the IC 30, there is a non-inverting buffer (hereinafter simply referred to as a buffer) 32a whose input terminal and power terminal B are connected to the power terminal 31 of the IC 30 and whose ground terminal G is grounded, and the output of the previous stage buffer is used as its input and power source. There are (n-1) buffers whose ground terminals are grounded, the set input terminal S and the power supply terminal B are connected to the power supply terminal 31 of the IC 30, and the output of the final stage buffer 32n is input to the reset input terminal R, and the power supply terminal 31 of the IC 30 is connected to the set input terminal S and the power supply terminal B. A reset priority type flip 70 knob (hereinafter referred to as FF) 33 whose terminal is grounded is provided, and the output of this FF 33 is used as a power-on reset pulse.
It is supplied to each part in C.

FIG. 4 is a diagram showing an example of signal waveforms at various parts when the circuit shown in FIG.
When the voltage rises to 1 and exceeds the minimum operating voltage level Vmtn of the element, the output of the first stage buffer 32a becomes "1#" (for example, 1j5V), and the FF 33 is set and its output becomes 1. As is well known, the buffers 32a to 32n have an input capacitance C1yl + output output C-out and a power supply terminal B-earth terminal G distance *Cna, so that the output of the previous stage buffer is 1'' for the subsequent buffer. However, the output does not become 1'' immediately, but after some delay time tc
After “IN”.

Therefore, the output of the final stage buffer 32n becomes 1'' with a delay of about nXtc, and the output of the final stage buffer 32n causes
Since the FF 33 is reset, the output of the FF' 33 becomes a rectangular signal with a pulse width of about nXtc as shown in FIG.

In this embodiment, n buffers 32FL to 32n
When constructing a delay circuit by cascade-connecting the buffers, the power for the buffers in the second and subsequent stages is obtained from the output of the buffer in the previous stage. This is due to the following reasons.

When configuring a delay circuit by cascading a plurality of buffers, the conventional method generally adopted is to take the power to each buffer directly from the power supply line. According to such a conventional method, the configuration shown in FIG. 3 becomes, for example, that shown in FIG. 5. However, as shown in FIG.
If the configuration is such that the ~50n power source is taken directly from the power line, the power terminal B to ground terminal G of each buffer CRG
iJ: Since it is charged by the power supply line, the input capacitance ifl'Cin and the output capacitance C6ut are the only capacitances that contribute to the delay in signal propagation, and the delay time per buffer stage is very small, on the order of several ns. On the other hand, CB
Since G is usually about 100 times as large as Cin or Coat, the configuration shown in FIG. 3 makes it possible to obtain a delay time nearly 100 times that of the configuration in FIG. Furthermore, in the configuration shown in FIG. 5, power is supplied to the final stage buffer 50n immediately after the IC power is turned on, so the output may sometimes become '1' immediately, albeit incompletely.
There is a possibility that the power-on reset pulse is reset immediately after being set, and a power-on reset pulse with the desired pulse width cannot be obtained. On the other hand, according to the configuration shown in FIG. 3, there is no such possibility since power is not supplied to the final stage buffer 32n.

In the above embodiment, the FF33 is used as the power-on reset generation circuit, but its output is set to 1" or "0" when the IC power supply voltage VCC rises, and the output is inverted upon receiving the output from the delay circuit. It is also possible to adopt other circuits if necessary.

As explained above, the present invention provides a first stage in which an input terminal and a power supply terminal are connected to a power supply terminal of the integrated circuit element in an integrated circuit element in which the inside of the integrated circuit element needs to be initialized when the power is turned on. ICIIt is a delay circuit consisting of a buffer and a plurality of buffers that are sequentially connected to this buffer and use the output of the previous stage buffer as its input and power supply.
It is equipped with a power-on reset pulse generation circuit that generates an output when the source voltage vcc rises and stops the output by using the buffer output of the final stage of the delay circuit. Since this can be realized without using terminals, the number of terminals can be reduced and terminals can be used efficiently. Further, since the power for the buffers in the second and subsequent stages of the delay circuit is obtained from the output of the previous stage, the number of buffers can be reduced and reliable operation can be achieved.

[Brief explanation of the drawing]

FIG. 1 is an explanatory diagram of a conventional IC, FIG. 2 is a diagram for explaining its operation, FIG. 3 is a block diagram of the main part of an embodiment of the present invention, and FIG. 4 is a diagram of the circuit shown in FIG. A diagram showing an example of signal waveforms at each part, and FIG. 5 is a diagram showing a modification of the circuit shown in the third diagram. (9) is an integrated circuit element, 31 is a power supply terminal, 32a to 32
n is a non-inverting buffer and a reset priority flip-flop. Patent applicant: Fujitsu Ten Ltd. Representative Patent Attorney: Hisashi Tamamushi (3 others)

Claims (1)

[Claims] In an integrated circuit device in which the inside of the integrated circuit device needs to be initialized when the power is turned on, a first stage non-inverting buffer whose input terminal and power terminal are connected to the power supply terminal of the integrated circuit device and the non-inverting buffer are sequentially A delay circuit comprising a plurality of non-inverting buffers connected in cascade and using the non-inverting buffer output of the previous stage as input and power supply, the final stage of the delay circuit generating an output at the rise of the power supply voltage applied to the power supply terminal of the integrated circuit element. 1. An integrated circuit device comprising a power-on reset pulse generation circuit that stops output by a non-inverting buffer output.