JP2578359B2 - Oscillation circuit - Google Patents

Description

Description: BACKGROUND OF THE INVENTION (Industrial application field) The present invention relates to an oscillator circuit composed of a three-stage inverter, and more specifically, to an integrated circuit having three terminals to which a resistor and a capacitor are externally connected. Oscillation circuit to be used.

(Prior Art) FIG. 7 is a conceptual diagram of a configuration of an inverter three-stage oscillation circuit. In the figure, reference numerals 1, 2, and 3 denote inverters, and when these are formed into ICs, the portion enclosed by a broken line is I
An external circuit including a resistor R for setting an oscillation cycle, a capacitor C, and a current limiting resistor Rs is connected to the three terminals Xi, Xc, and XR provided here.

FIG. 8 is an operation waveform diagram of the oscillation circuit thus configured.

(A) is a voltage waveform at a common connection point of the resistor R and the capacitor C, (b) is a waveform diagram of a signal appearing at a terminal Xc, and (c) is a waveform diagram of a signal appearing at a terminal XR.

Here, when the values of the resistor R and the capacitor C are changed,
The time constant of the charge / discharge waveform shown in (a) changes, and the oscillation cycle can be changed. This oscillation cycle T is given by T = 2, 2C · R.

(Problems to be Solved by the Invention) In an oscillator circuit having such a configuration, as shown in FIG. 9, an IC portion surrounded by a solid line receives another clock from the outside and receives the clock inside the IC. Considering the case where a clock is used and a signal obtained by dividing the frequency is output, the internal configuration is as shown in FIG. Here, a ▲ / EXT terminal connected to the inverter 3 and a terminal XQ for obtaining a frequency-divided signal are newly provided, and a total of five terminals are required.

11 and 12 receive another clock from outside,
This shows an example of use of an oscillator circuit having five terminals, which is configured to be able to use the clock inside the IC and output a signal obtained by dividing the clock.

Fig. 11 shows the case of using in the external mode, and the terminal XR / CLK
An external clock is applied to i and a frequency-divided clock output is obtained from terminal XQ. In this case, terminal Xi is connected to common, terminal Xc is open (open), and terminal ▲
▼ / EXT is connected to power supply Vcc.

Fig. 12 shows the case of using in CR oscillation mode.
A limiting resistor Rs, a resistor R, and a capacitor C are respectively connected to i, Xc, and XR, terminals ▲ / EXT are connected to a common, and a frequency-divided output is obtained from a terminal XQ.

In the present invention, the part to be integrated is connected by three terminals,
An object of the present invention is to provide an oscillation circuit capable of realizing an external mode and a CR oscillation mode as shown in FIGS.

(Means for Solving the Problems) FIG. 1 is a block diagram showing a basic configuration of the present invention. In the figure, Xi / ▲ ▼ is the first terminal, Xc /
▼ is the second terminal, and XR / CLKi is the third terminal.

4 is a frequency dividing circuit, 5 is the logic of the signal of the first terminal Xi / ▲ and the signal from the frequency dividing circuit 4, and the second terminal
An inverter for inverting the signal of Xc / ▲ ▼ and outputting the inverted signal to a third terminal XR / CLKi; 7 a clock supply circuit for applying a clock appearing on the third terminal XR / CLKi to an input terminal of the frequency dividing circuit 4; And 81 inhibit the output of the frequency dividing circuit 4 at one level of the signal of the first terminal Xi / TEST, and
A control circuit for setting the output of / CLKi to a high impedance state, and is configured by an inverter.

(Operation) By connecting the first terminal Xi / ▲ to the power supply Vcc, a frequency-divided output of the clock applied to the third terminal can be obtained from the second terminal, and the first, second, and second terminals can be obtained. By connecting a limiting resistor, a resistor and a capacitor to each of the terminals 3 respectively, the device operates in an oscillation mode.

(Example) Hereinafter, the example of the present invention is described in detail using drawings.

FIG. 2 is a configuration block diagram showing an embodiment of the present invention. In the figure, components corresponding to those in FIG. 1 are denoted by the same reference numerals.

The frequency dividing circuit 4 is composed of four flip-flops 41 to 44 connected in cascade with each other, and here divides the cycle of the input clock to 1/8. As the gate 5 for selecting two signals, a NAND gate is used. The output of the frequency dividing circuit 4 is applied to one input terminal A and the other input terminal B
The signal of the first terminal Xi / ▲ is applied through the buffer 10 and the inverter 11. The clock supply circuit 7 includes a buffer 71 and an inverter 72, and supplies the clock applied to the third terminal XR / CLKi to the flip-flop 4.
1 is applied to terminal T. 8 is an inverter, 81 is a buffer in which the output of the inverter 8 is applied to the control terminal, and the output signal from the inverter 8 is applied to the reset terminal of the frequency dividing circuit 4 to inhibit the output of the frequency dividing circuit 4; , Buffer 81
Cuts the signal path in response to the output signal from the inverter 8 to bring the output of the third terminal XR / CLKi into a high impedance state.

 The operation of the circuit thus configured will be described below.

FIG. 3 is a diagram showing an external connection state when the circuit of FIG. 2 is operated in an external mode, and FIG. 4 is an operation waveform diagram thereof.

When the power supply voltage Vcc is connected to the first terminal Xi / TEST as shown in FIG. 4 (b), the gate 5 selects the signal from the frequency dividing circuit 4, and the gate 5 selects the third terminal from the second terminal. The signal path to the terminal is interrupted by the buffer 81. Therefore, when an external clock as shown in (a) is applied to the third terminal XR / CLKi, the signal Q4 divided as shown in (c) is output from the second terminal Xc / ▲ ▼. can get.

FIG. 5 is a diagram showing an external connection state when the circuit of FIG. 2 is operated in the CR oscillation mode, and FIG. 6 is an operation waveform diagram thereof.

One end of the limiting resistor Rs is connected to the first terminal Xi / ▲, one end of the capacitor C is connected to the second terminal Xc / ▲, and one end of the resistor R is connected to the third terminal XR / CLKi. At the same time, one end of the resistor RL is connected as shown.

With this connection, one of the signal levels of the first terminal Xi / TEST is applied to the reset terminal R of the frequency dividing circuit 4, and its output is prohibited. In addition, the inverter 6 in the signal path from the second terminal to the third terminal becomes effective, and an inverter three-stage oscillation circuit is formed.

FIG. 6A shows a voltage waveform between a resistor R and a capacitor C in an external circuit, and FIG. 6B shows a second terminal Xc.
The voltage waveform generated at / ▲ ▼, (c) is the third terminal Xc / CL
The voltage waveforms generated at Ki are shown.

(Effects of the Invention) As described in detail above, according to the present invention, the entirety is 3
Oscillation circuits suitable for ICs that can realize an external mode that obtains a divided output by applying a clock and a CR oscillation mode that obtains an oscillation output by connecting a resistor and a capacitor externally, while being configured with pins. Can be provided.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention, and FIG.
FIG. 3 is a block diagram showing an embodiment of the present invention, FIG. 3 is a diagram showing an external connection state when the circuit of FIG. 2 is operated in an external mode, FIG. 4 is an operation waveform diagram thereof, and FIG. Is the second
FIG. 6 is a diagram showing an external connection state when the circuit shown in FIG. 1 is operated in the CR oscillation mode, FIG. 6 is an operation waveform diagram thereof, FIG. 7 is a conceptual diagram of a configuration of a three-stage inverter oscillation circuit, and FIG. Waveform diagrams, FIG. 9 is a conceptual diagram showing an example of use of such an oscillator circuit, FIG. 10 is a block diagram of an internal configuration in the case of assuming such an example of use, and FIGS. It is a figure showing the external connection state in the example of use. Xi / ▲ ▼ ... first terminal, Xc / ▲ ▼ ... second
, XR / CLKi... Third terminal, 4.
... gate, 6 ... inverter, 7 ... clock supply circuit, 8, 81 ... control circuit

Claims (1)

(57) [Claims] A first terminal, a frequency dividing circuit, a signal from the first terminal, and a signal from the frequency dividing circuit; A NAND gate (5) for outputting to the second terminal, a clock supply circuit (7) for supplying a clock appearing at the third terminal to an input terminal of the frequency divider, and a path from the second terminal to the third terminal An inverter (6) and a buffer (81) inserted and connected in series to each other, and a signal from the first terminal is supplied to a reset terminal of the frequency dividing circuit via an inverter (8), and the buffer (8)
An oscillation circuit including a signal path to be provided to the control terminal of 1).