JP2743407B2 - Clock pulse generation circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a clock pulse generation circuit, and more particularly to a clock pulse generation circuit of an information processing device.

2. Description of the Related Art Conventionally, a clock pulse generation circuit of this type only generates a clock pulse having a cycle length of a single pulse based on a fundamental frequency required for the operation of an information processing device, or generates a clock pulse having a plurality of frequencies. Are generated, and the period length is changed and transmitted by switching them.

The clock pulse generation circuit of this type generates a lock pulse having a cycle length of a single pulse width of the fundamental frequency required for the operation of the information processing device, or uses a plurality of frequencies to generate a pulse width dependent on the frequency. In some cases, the change in clock pulse width is performed by switching using the difference between the two.

However, in the conventional clock pulse generation circuit described above, when performing a margin check (Marginal Check) for the clock pulse of the information processing device, the clock pulse generator is changed to generate a clock pulse having a cycle length and a pulse width according to the margin check. In order to make it, there is a drawback that it takes a lot of man-hours to prepare it, and there is also a drawback that checking cannot be easily performed.

In addition, a clock pulse oscillator having a cycle length for the margin check is prepared in advance, and when switching and using it, the cost associated with mounting the clock pulse oscillator and the mounting area are secured. There was also the disadvantage of having to do it.

An object of the present invention is to provide a clock pulse oscillator that can easily perform a margin check on a clock pulse in an information processing device or the like.

The clock pulse generating circuit according to the present invention comprises: an oscillating unit for transmitting a clock pulse; a delay unit for delaying the clock pulse from the oscillating unit for a predetermined time to be transmitted; and a clock pulse transmitted from the oscillating unit. The clock pulse delayed by the delay unit is input, and the clock pulse and the delayed clock pulse are passed alternately.

Another clock pulse generating circuit according to the present invention includes an oscillating means for transmitting a clock pulse, a delay means for delaying the clock pulse from the oscillating means for a predetermined time and transmitting the clock pulse, and the clock pulse and a delayed output of the delay means. ORing means for transmitting a logical sum output which is a logical sum of the above, ANDing means for transmitting a logical product output which is a logical product of the clock pulse and the delay output of the delay means, and the logical sum output and the logic Output control means for alternately sending the product output.

Embodiment Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 shows a first embodiment of a clock pulse generating circuit according to the present invention.
FIG. 3 is a block diagram showing a configuration of the example. In the figure, a clock pulse generating circuit according to a first embodiment of the present invention
It comprises a clock generator (hereinafter abbreviated as OSC) 1, a delay circuit 2, and a multiplexer circuit 3.

The clock generator 1 sends out a basic clock signal a. Note that the signal a is a square wave.

The delay circuit 2 receives the signal a and sends a clock signal b delayed by a predetermined time tD. The delay time tD is a deviation time for performing a margin check with respect to the cycle of the basic clock signal a.

The multiplexer circuit 3 includes AND gates 31 and 32,
The circuit includes an OR gate 33, inverters 34 and 36, and a D-type flip-flop (hereinafter abbreviated as FF) 35, and sends out a clock signal d in response to the input of the output condition signal c. The output condition signal c is input to the clear terminal (CLR) of FF35. CK of FF35 is a clock terminal, and PR is a power supply terminal.

The operation of the clock pulse generation circuit according to the present embodiment having such a configuration will be described with reference to FIG. FIG. 2 is a time chart showing signals of respective parts in FIG.

In the figure, a signal a is a clock signal sent from the OSC1, its cycle is t3, and its pulse width is t1. Also,
The signal b is an output signal of the delay circuit 2 and is a signal delayed by tD from the signal a.

When the output condition signal c is at the low level, the signal e sent from the terminal of the FF 35 is always at the high level. At this time, the multiplexer circuit 3 sends out a signal having a phase shifted by a certain circuit delay time t P1 with respect to the signal a as a signal d. This signal d is used as a clock signal during normal operation. That is, when the margin check is not performed, the output condition signal c may be set to the low level.

On the other hand, when the output condition signal c is at a high level, the FF 35 performs a toggle operation in response to the rise of the signal b. for that reason,
The multiplexer circuit 3 sends out the signal a when the signal e is at a high level, and sends out the signal b when the signal e is at a low level. Therefore, a clock signal in which the signal a and the signal b are alternately switched is transmitted as the signal d.

In this case, the pulse widths t6 and t7 are the same as the pulse width t1 of the signal a, but the times t4 and t5 between the pulses are obtained by adding ± tD as a deviation to the time t2 between the pulses of the signal a. . This means that the period fluctuates by ± tD when viewed from the rising period of the pulse. By associating this time ± tD with the deviation time used for the margin check, the signal d
Contains the cycle number component to be checked. That is, when performing a margin check, the output condition signal c may be set to a high level.

As described above, if the output of the clock pulse generation circuit according to the present embodiment is input to an information processing device (not shown) and an operation check is performed, a margin check using a signal having a cycle length before and after the cycle of the basic clock signal can be performed. You can.

Next, a second embodiment of the present invention will be described with reference to FIG. FIG. 3 is a block diagram showing the configuration of a second embodiment of the clock pulse generating circuit according to the present invention.
Parts equivalent to those in the figure are indicated by the same reference numerals. In the figure, the clock pulse generating circuit according to the second embodiment of the present invention includes an OSC 1, a delay circuit 2, and a multiplexer circuit 3. Note that the OSC 1 and the delay circuit 2 have the same configuration as that of the first embodiment (see FIG. 1), and thus the description is omitted.

The multiplexer circuit 3 includes AND gates 31 and 32, OR gates 33, 38 and 39, inverters 34, 36 and 37, and FFs.
35. This multiplexer circuit 3 has an OR gate 3 on the input side of AND gates 31 and 32 in FIG.
8 and 39 are added, and an inverter 37 is added. The output f of the OR gate 38 is input to the AND gate 31 and the OR gate 39.

The operation of the clock pulse generating circuit according to the present embodiment having such a configuration will be described with reference to FIG. FIG. 4 is a time chart showing signals of respective parts in FIG.

In the figure, a signal a is a clock signal transmitted from the OSC1, and its period is t3 and its pulse width is t1. The signal b is an output signal of the delay circuit 2 and is a signal delayed by tD from the signal a.

When the output condition signal c is at the low level, the signal e sent from the terminal of the FF 35 is always at the high level. At this time, the output of the AND gate 32 is always at a low level, and the output of the inverter 37 is always at a high level. Therefore, the signal a is input via the AND gate 31 and the OR gate 33.
Is transmitted as the signal d. However, in this case, the phase shifts by a fixed circuit delay time tp1 due to the AND gate 31 and the OR gate 33.

The pulse width t5 of the signal d becomes equal to the pulse width t1 of the signal a. This signal d is used as a clock signal during normal operation. That is, when the margin check is not performed, the output condition signal c may be set to the low level.

On the other hand, when the output condition signal c is at a high level, the FF 35 performs a toggle operation in response to the fall of the signal b. for that reason,
The AND gate 32 derives the output of the OR gate 39 only during the low level of the output signal e of the FF 35. At this time, since the output of the inverter 37 is at the low level, the OR gate 38 always outputs the signal b. Therefore, since the OR gate 39 receives the signal b and the signal a as inputs, during the low level period of the output signal e of the FF 35, the AND gate 32 outputs the signal a, which is the output of the OR gate 39, with the logical OR of the signal b with the signal b (pulse). Will send out the width t9).

On the other hand, while the output signal e of the FF 35 is at the high level, no pulse appears at the output of the OR gate 32. Instead, the logical product output of the signal a and the signal b (pulse width t7) is output from the AND gate 31. Will appear.

As a result, during the low level period of the signal e, the AND gate 32
Is output from the OR gate 33, and during the high level period of the signal e, the AND output of the signal a and the signal b output from the AND gate 31 is output from the OR gate 33. Is sent out as a signal d. Note that t6 = tD + tp1 and t8 = t10 = t2.

As a result, the signal d is a signal obtained by alternately combining the pulse width t9 by adding the time deviation tD in the delay circuit 2 to the pulse width t1 of the signal a, which is the basic clock signal, and the pulse width t7 obtained by subtracting the pulse width t9. It becomes.

This means that the pulse width of the signal a fluctuates by ± tD. If this time ± tD and the fluctuation due to the maximum and minimum of the pulse width used for the margin check correspond, the signal d has a margin. It can be used as a clock pulse for checking.

In other words, when performing a margin check, the output condition signal c may be set to a high level.

As described above, if the output of the clock pulse generation circuit according to the present embodiment is input to an information processing device (not shown) and an operation check is performed, it is possible to perform a margin check using a signal having a pulse width before and after the pulse width of the basic clock signal. You can do it.

As described above, according to the present invention, the output of the OSC1 and the output of the delay circuit are alternately transmitted by the multiplexer circuit in response to an external command, so that the margin check for the clock pulse in the information processing device or the like can be performed. There is an effect that it can be easily performed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing the configuration of a clock pulse generating circuit according to a first embodiment of the present invention, FIG. 2 is a time chart showing the operation of FIG. 1, and FIG. 3 is a second embodiment of the present invention. And FIG. 4 is a time chart showing the operation of FIG. Explanation of Signs of Main Parts 1 ... Clock Generator 2 ... Delay Circuit 3 ... Mux Circuit

Claims (2)

(57) [Claims] An oscillator for transmitting a clock pulse; a delay unit for transmitting the clock pulse from the oscillator with a predetermined delay; and a clock pulse transmitted from the oscillator and delayed by the delay unit. A clock pulse generating circuit, comprising: a clock pulse input circuit; and a passing means for alternately passing the clock pulse and the delayed clock pulse. 2. An oscillating means for transmitting a clock pulse, a delay means for delaying a clock pulse from the oscillating means for a predetermined time and transmitting, and a logic which is a logical sum of the clock pulse and a delayed output of the delay means. ORing means for sending a sum output, ANDing means for sending a logical product output which is a logical product of the clock pulse and the delay output of the delay means, and sending the logical sum output and the logical product output alternately A clock pulse generation circuit, comprising: