JPH02123411A - Clock pulse generating circuit - Google Patents

Abstract

PURPOSE:To easily check a margin by providing the title circuit with a delay circuit for delaying a clock pulse for fixed time and alternately outputting a clock pulse and a delay output. CONSTITUTION:A part of a clock signal (a) outputted from a clock generator(OSC) 1 is inputted to an AND gate 31 and the residual is inputted to an AND gate 32 as a signal (b) delayed for a prescribed time by a delay circuit 2. When an output condition signal (c) is a high level, an FF 35 executes toggle operation in response to the rise of the signal (b). Thereby, a multiplexer circuit sends the signal (b) to the gate 32 when an output signal (e) from the F 35 is a low level, and at the time of its high level, outputs the signal (a) to the gate 31. Thus, a circuit 3 sends a signal (d) obtained by alternately switching the clock signal (a) and the delay signal (b). Thereby, the margin check of a clock pulse can easily be executed in accordance with a command from the external.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a clock pulse generation circuit, and more particularly to a clock pulse generation circuit for an information processing device.

BACKGROUND ART Conventionally, this type of clock pulse generation circuit only generates a clock pulse having a period length of a single pulse at the fundamental frequency necessary for the operation of an information processing device.
Alternatively, clock pulses of multiple frequencies are generated and the cycle length is changed by switching between them.

In addition, this type of clock pulse generation circuit generates a lock pulse with a period length of a single pulse width of the fundamental frequency necessary for the operation of information processing equipment, or uses multiple frequencies and has a pulse width that depends on the frequency. There are some that use the difference in clock pulse width to change the clock pulse width by switching.

However, in the above-mentioned conventional clock pulse generation circuit, when performing a margin check on clock pulses of an information processing device,
11 The drawback is that it takes many man-hours to prepare because the clock pulse generator is not changed to create a clock pulse with a cycle length and pulse width that correspond to the margin check. There are also two drawbacks.

In addition, if a clock pulse oscillator with a period length for margin clocking is prepared in advance and used by switching, the cost increases due to the implementation of the marginal pulse oscillator and its implementation. There was also the drawback that the area had to be secured in G'1.

OBJECTS OF THE INVENTION An object of the present invention is to provide a clock pulse oscillator that can easily perform a margin check on clock pulses in an information processing device or the like.

A clock pulse oscillator according to the present invention includes: an oscillating means for sending out a clock pulse; a delay means for sending out a clock pulse from the oscillating means with a predetermined time delay tl; It is characterized by having an output control stage T: which alternately sends out delayed outputs.

Another cross-pulse oscillator according to the present invention includes: oscillation means for sending out a clock pulse; delay means for delaying the cross-clock pulse from the oscillation means by a predetermined time and sending it out;
OR means for sending out a logical sum output which is the logical sum of the above-mentioned 11 clock pulses and the delayed output of the delay means, and a logical product output which is the logical product of the clock pulse and the delayed output of the delay means. The present invention is characterized in that it has an AND means, and an output control means for alternately sending out the IF logical sum output and the AND output.

Example Hereinafter, the present invention will be explained in detail using the drawings.

FIG. 1 is a block diagram showing the configuration of a first embodiment of a clock pulse generation circuit according to the present invention.

In the figure, the IE jitter generation circuit according to the first embodiment of the present invention is a clock generator (hereinafter abbreviated as O20).
1, a delay circuit 1i42, and a multiplexer circuit 3.

The clock generator 1 sends out the basic clock signal a. Note that the signal a is a square wave.

The delay circuit 2 receives the signal a and outputs a clock signal delayed by a predetermined time tD. The delay times t and D are basically the deviation times at which the margin check should be shifted with respect to the period of the 17th clock fS number a.

Multiplexer circuit 11=Ii3 includes AND gates 31 and 32, OR gates 1-33, and inverters 34 and 3.
6 and 1) type flip-flop (hereinafter abbreviated as FF) 3
5, and sends out the clock signal d in response to the input of the output condition signal C. The output condition signal C is input to the clear terminal (CLII) of the FF 35. Note that CK of FF35 is a clock terminal, P
R is a power supply terminal.

The operation of the D-sink pulse generating circuit of this embodiment having such a configuration will be explained with reference to FIG. 2.

FIG. 2 is a time chart 1 showing the signals of each part of FIG. 1.

In the figure, signal a is a clock signal sent from 08CI, its period is t, 3, and its pulse width is tl. In addition, the signal S is the output signal of the 74174 circuit 2,
This is a signal delayed by tD with respect to signal a.

When the output condition signal C is at a low level, the signal C sent from the d terminal of the FF 35 is always at a high level. At this time, the multiplexer circuit 3 sends out as the signal d a signal that is out of phase with the signal a by a certain circuit delay time tP1. This signal d is used as a clock signal during normal operation. In other words, when the margin check is not performed, it is ``good'' to shift the output condition signal C to the low level.

On the other hand, when the output condition signal C is at a high level, the FF 35 performs a toggle operation in response to the rise of the signal S. Therefore, the multiplexer circuit 3 sends out the signal a when the signal e is at a high level, and sends out the signal S when the signal e is at a low level. Therefore, the lock signal is sent out as the signal d by alternately switching between the signal a and the signal S.

In this case, the pulse widths t6 and tl are the pulse width t of the signal a.
1, but the time t4t5 between pulses is the time t2 between pulses of signal a plus ±tD as a deviation. This means that the period fluctuates by ±tD when viewed from the pulse rise period. This time ±
If tD is made to correspond to the deviation time used for the margin check, the signal d will contain the period number component to be checked. In other words, when performing a margin check, it is good to shift the output condition signal C to a high level.

As described above, when the output of the clock pulse generation circuit according to this embodiment is input to an unspecified information processing device and an operation check is performed, a margin check can be performed using a signal having a cycle length before and after the cycle of the basic clock signal. It can be done.

Next, a second embodiment of the present invention will be described using FIG. FIG. 3 is a block diagram showing the configuration of a second embodiment of the clock pulse generation circuit according to the present invention, and parts equivalent to those in FIG. 1 are designated by the same reference numerals. In the figure, the clock pulse generation circuit according to the second embodiment of the present invention includes 08CI, delay circuit 2, and multiplexer 8!
&3. Note that the OSCT and delay circuit 2 have the same configuration as in the first embodiment (see FIG. 1), so their explanation will be omitted.

The multiplexer circuit 3 includes ant gates 1, 31 and 32, OR gates 33, 38 and 39, and an inverter 34.
36 and 37, and an FF 35.

This multiplexer circuit 3 is an ant game 1-3 shown in FIG.
The configuration is such that OR gates 38 and 39 are added to the input sides of 1 and 32, and an inverter 37 is added. Note that the output f of the OR gate 38 is the output f of the AND gate 31.
and is input to the OR gate 39.

The operation of the clock pulse generation circuit of this embodiment having such a configuration will be explained using FIG. 4.

FIG. 4 is a time chart showing signals of each part in FIG. 3.

In the figure, signal a is a clock signal sent from 08CI, its period is t3, and its pulse width is tl. Further, the signal S is an output signal of the delay circuit 2, and is delayed by tD with respect to the signal a.

When the output condition signal C is at a low level, the signal e sent from the d terminal of the FF 35 is always at a high level. At this time, the output of the AND gate 32 is always at a low level,
Further, the output of the inverter 37 is always at a high level.

Therefore, the signal a is sent out as the signal d via the AND gate 31 and the 'OR gate 33. However, in this case, the phase will be shifted by a certain circuit delay time t111 due to the AND gate 31 and the OR gate 33.

The pulse width t5 of this signal d is equal to the pulse width t1 of the signal a. Note that this signal d is used as a clock signal during normal operation. In other words, when the margin check is not performed, the output condition signal C can be set to low level.

On the other hand, when the output condition signal C is at a high level, the FF 35 performs a toggle operation in response to the fall of the signal S. Therefore, the AND gate 32 derives the output of the OR gate 39 only during the period when the output signal e of the FF 35 is at a low level. At this time, since the output of the inverter 37 is at a low level, the OR gate 38 always outputs the signal S. Therefore, since the three OR gates use this signal S and the signal a manually, during the low level period of the output signal e of the FF 35, the AND gate 32 outputs the logical sum of the signal a which is the output of the OR gate 39 ( The pulse width t9) will be sent out.

On the other hand, during the period when the output signal e of the FF 35 is at a high level, the equivalent pulse does not appear at the output of the OR gate 32, and instead, the AND output (pulse width t7) of the signal a and the signal A is the output of the AND gate 31. It will appear in

As a result, during the low level period of the signal e, the AND gate 32
The OR gate 33 outputs the logical sum of the signal a and the signal S, which are the outputs of is sent out from the ORKATE 33 as a signal d. In addition, it is 762 tD + - tpl, and t8
=tlO=t2.

As a result, the signal d has a time deviation tD in the delay circuit 2 with respect to the pulse width t, 1 of the signal a, which is basically a corrupt signal.
The f-word is obtained by alternately synthesizing the pulse width 1-9 by adding , and the pulse width t7 by subtracting it.

This means that the pulse width of signal a fluctuates by ±t,D, and if we correlate this time ±t,D with the fluctuations due to the maximum and minimum pulse widths used for margin check, we get: The signal d can be used as a high-level pulse during the margin check (8) In other words, when performing the margin check, it is good to set the output condition signal to a high level.

The output of the clock pulse generation circuit according to this embodiment is inputted to an information processing device (not shown) as shown in the following.

When performing the operation check, it is possible to perform a margin check using signals with pulse widths before and after the pulse width of the basic clock signal.

As described in detail, the present invention provides clock pulses in information processing equipment, etc. by alternately sending out the output of the OSC i and the output of the delay circuit by a multiplexer circuit in response to an external command. This has the advantage that margin checks can be easily performed.

[Brief explanation of drawings]

FIG. 1 is a schematic diagram showing the configuration of the clock pulse generation circuit according to the first embodiment of the present invention, FIG. 2 is a time chart showing the operation of FIG. 1, and FIG. FIG. 4 is a block diagram showing the configuration of the zero pulse generation circuit according to the second embodiment, and FIG. 4 is a time chart 1 showing the operation of FIG. 3. Explanation of symbols for main parts 1...Tarlock generator...Delay circuit...Multiplexer circuit

Claims (2)

[Claims] (1) An oscillation means for sending out a clock pulse, a delay means for delaying the clock pulse from the oscillation means by a predetermined period of time, and an output control means for alternately sending out the clock pulse and the delayed output of the delay means. A clock pulse generation circuit comprising: (2) An oscillation means for sending out a clock pulse, a delay means for delaying the clock pulse from the oscillation means by a predetermined time and sending it out, and a logical sum output that is the logical sum of the clock pulse and the delayed output of the delay means. an AND means for outputting an AND output which is an AND of the clock pulse and the delayed output of the delay means; 1. A clock pulse generation circuit comprising: output control means.