JPH0221811Y2 - - Google Patents

Description

[Detailed Description of the Invention] [Technical Field of the Invention] This invention relates to a circuit for selecting two data, a so-called multiplexer.

[Technical background of the invention]

FIG. 1 shows a conventional example of a data selection circuit, a so-called multiplexer, that selectively selects two pieces of data at a predetermined period. In the figure, terminals 11 and 12
Data A and B are respectively input to the . Data A and B are latched into D flip-flop circuits 14 and 15, respectively, using a clock pulse _P1 applied to terminal 13.

A data selection circuit 16 selectively selects output data A', B' of the D flip-flop circuits 14, 15 at a predetermined period. That is, data A′,
B' is supplied to one input terminal of AND circuits 161 and 162, respectively. The AND circuit 161 uses the clock pulse P ₁ as a gate pulse, and the AND circuit 162 uses the clock pulse P ₁ as the gate pulse for the inverter circuit 1.
The pulse P ₂ inverted at 63 is used as a gate pulse.
Therefore, when clock pulse _P1 is "1", data A' is selected, and when clock pulse P1 is "0", data A' is selected.
B' is selected. The data A' and B' selected in this way are combined by an OR circuit 164,
be placed on the same transmission line.

FIG. 2 is a timing chart showing the operation of FIG. 1. Figures 2 a to d show pulses P ₁ ,
P ₂ indicates data A', B', and ta is the delay time of data A', B' with respect to clock pulse P ₁ due to the responsiveness of the D flip-flop circuits 14, 15.
Further, tb is the delay time of the clock pulse P ₂ with respect to the clock pulse P ₁ due to the responsiveness of the inverter circuit 163. 2e shows the composite data C of the output data of the AND circuits 161 and 162 before being passed through the OR circuit 164, and FIG.
This is composite data D of the output data of the AND circuits 161 and 162 appearing at the output terminal of the . In this case, tc is the time delay of the output with respect to its input due to the responsiveness of the AND circuits 161 and 162, and td is the time delay of the output with respect to its input due to the responsiveness of the OR circuit 164. Also, the data is clock pulse
The data is based on pulses P ₁₁ , P ₁₂ during clock pulse P ₁ , and the data is based on pulses P ₂₁ , P ₂₂ , P ₂₃ during clock pulse P ₂ .
It depends.

By the way, the following problem occurs when the clock pulse _P2 lags the clock pulse _P1 by a time tb. That is, due to this time delay, there is a period in which both clock pulses P ₁ and P ₂ are "0". If data A' and B' are both "1" during this period, composite data C and D will be fragmented as shown in FIG. 2 e and f. In other words,
A fragmented pulse P ₃ of negative polarity, a so-called whisker, occurs in the composite data CD. In this way, when clock pulse _P1 falls and clock pulse _P2 rises, if data A' and B' are both "1", it is necessary to output continuous pulses as composite data C and D. However, in reality, as shown above, clock pulse P ₂ is equal to clock pulse P _1.
Since it has a delay time of tb, the shredding pulse P ₃
will occur.

In order to remove this shredding pulse _P3 , conventionally the first
As shown in the figure, a D flip-flop circuit 165 is provided after the OR circuit 164, and the clock pulse
The synthesized data D was latched into the D flip-flop circuit 165 by a clock pulse _P4 (see 2nd g) having twice the frequency of _P1 .
In this way, the D flip-flop circuit 16
At the output terminal of 5, as shown in _FIG .
is obtained. Note that 17 is the input end of the clock pulse _P4 , and 18 is the output end of the composite data E.

[Problems with background technology]

However, in the case of the above configuration, the shredding pulse
In order to eliminate P ₃ , D flip-flop circuit 1
65 is not only required, but also a separate clock pulse.
There were drawbacks such as the need for a source of _P4 .

[Purpose of invention]

This invention was made in order to cope with the above-mentioned situation, and the object thereof is to provide a data selection circuit which has a simple structure and can eliminate cutoff pulses.

[Summary of the idea]

This invention generates correction data for removing shredded pulses by taking the AND of the two data, and uses this to replenish the data selection output to remove shredded pulses. .

[Example of idea]

Hereinafter, one embodiment of this invention will be described in detail with reference to FIG. In FIG. 3, the same parts as in FIG. 1 are given the same reference numerals. In FIG. 3, an AND circuit 166 is added to the previous FIG. 1, and the OR circuit 164 is converted into a three-input OR circuit 167. AND circuit 166 outputs data A',
B′ as input, OR circuit 167 is AND circuit 1
In addition to the outputs of 61 and 162, the output of an AND circuit 166 is input.

The operation of the above configuration will be explained with reference to FIG. FIGS. 4a to 4d show clock pulses P ₁ and P ₂ and data A' and B', respectively. Further, FIG. 4e shows composite data C of the output data of the AND circuits 161 and 162 which is not passed through the OR circuit 167.

The AND circuit 166 outputs "1" when both data A' and B' are "1", and data F as shown in FIG. 1f is obtained. However, in this case too,
The rising and falling edges of data F are data A′,
Compared to that of B', there is a delay of tc due to the responsiveness of the AND circuit 166. This data F is synthetic data C
This is the same data with the shredded pulse _P3 removed. Therefore, by supplying the output data F of the AND circuit 166 to the OR circuit 167, it is possible to obtain composite data D from which the cut pulse _P3 has been removed.

By the way, in Figure 1 above, AND circuit 1
The circuit consisting of 61, 162 and OR circuit 164 is
When data A' and B' are both "1", it is nothing but a circuit that takes the logical product of them. However, in the conventional circuit, a cut pulse _P3 occurs due to the time delay of the clock pulse _P2 caused by the inverter circuit 163, and an ideal AND output cannot be obtained. In contrast,
As in this embodiment, by providing the AND circuit 166 which inputs data A' and B', the data
Since it is possible to obtain the ideal AND output of both A′ and B′ when both are “1”, the shredded pulse
Synthetic data D from which _P3 has been removed can be obtained. In other words, the data F can mask the shredded pulse _P3 . Note that data A′,
Since the output of the AND circuit 166 is "0" during periods other than when B' are both "1", the combined data is disturbed by providing the AND circuit 166 during such periods. That's not the case.

As described in detail above, according to this embodiment, the D flip-flop circuit 1 latches the composite data D.
65 and its clock pulse P ₄ , simply adding an AND circuit 166 , and converting the OR circuit 164 into a three-input OR circuit 167 can eliminate the shredded pulse P ₃ . Therefore, when the circuit is integrated, there is no need to create a supply source for the D flip-flop circuit 165 or the clock pulse _P4 , so it is possible to lower the integration density or reduce the number of chips.

Further, even if there is a time difference due to the responsiveness of the circuit elements, it is possible to obtain composite data with almost no difference in real time between the data A' and B'.

In this embodiment, a case will be described in which the outputs of AND circuits 161, 162, and 163 are combined by one OR circuit 167 as a configuration in which correction data F is combined with the combined data of gate outputs of data A' and B'. However, it is not limited to this. For example, the synthesis of the gate outputs and the synthesis of the correction data F therefor may be performed using separate OR circuits.

[Effect of idea]

As described above, according to this invention, it is possible to provide a data selection circuit which has a simple structure and is designed to eliminate cutoff pulses.

[Brief explanation of the drawing]

Figure 1 is a circuit diagram showing a conventional data selection circuit.
Fig. 2 is a timing chart for explaining the operation of Fig. 1, Fig. 3 is a circuit diagram showing an embodiment of the data selection circuit according to this invention, and Fig. 4 is for explaining the operation of Fig. 3. This is the timing chart. 16...Data selection circuit, 161, 162, 1
66...AND circuit, 163...Inverter circuit, 167...OR circuit.

Claims (1)

[Claims for Utility Model Registration] A first device that selects the first data by logically ANDing the first data and the first selection signal.
a selection means for generating a second selection signal by inverting the first selection signal; and logic between the second data and the second selection signal output from the inversion means. By taking the product,
a second selection means for selecting the second data; a first synthesis means for synthesizing the selection outputs of the first and second selection means by logically ORing the selection outputs of the first and second selection means; 1. To remove the shredded pulse generated in the composite output of the first synthesizing means due to the time delay of the second selection signal with respect to the first selection signal by performing a logical product of the second data. correction data generation means for generating correction data; and a logical sum of the correction data outputted from the correction data generation means and the synthesis output of the first synthesis means. second synthesis means for removing the shredded pulses from the synthesis output.