JPS62217741A - Signal multiplexing circuit - Google Patents

Abstract

PURPOSE:To reduce useless power consumption by providing a multiplier circuit generating a clock signal fed to a synchronizing FF while multilying a clock signal to be fed to a signal synthesizing circuit. CONSTITUTION:Low-order group digital signals Di1-Di4 are inputted to a signal synthesizing circuit 10 via buffers 11-14 and multiplexed and synthesized into a negative serial digital signal and a normal high-order group digital signal obtained by applying waveform shaping the result by an FF 20 is sent to the next stage via a buffer 22. The second clock signal subjected to two-stage frequency division by frequency division circuits 16, 17 and the 1st clock signal from the circuit 16 via buffers 18, 19 are fed to the circuit 10. The clock signal fed to the FF 20 is obtained by multiplying the 1st clock signal to the circuit 10. That is, the clock signal outputted from a multiplier 30 multiplying the clock signal by 1/2 period via the buffer 19 is used as the synchronizing signal of the FF 20.

Description

[Detailed Description of the Invention] [Summary] Signal multiplexing in which a plurality of low-order group digital signals are multiplexed and combined using a signal synthesis circuit, and further waveform shaping is performed using a flip-flop circuit to obtain a regular high-order group digital signal. A multiplier circuit that multiplies the clock signal to be provided to the signal synthesis circuit to create a clock signal to be provided to the flip-flop circuit, in order to reduce as much as possible the wasted power consumption in the buffer that is used to align the phases of various clocks in the circuit. Equipped with

[Industrial Application Field] The present invention relates to a signal multiplexing circuit that multiplexes a plurality of low-order group digital signals, and more specifically, a signal multiplexing circuit that multiplexes a plurality of low-order liver digital signals having a predetermined pit rate. , a signal synthesis circuit that multiplexes and synthesizes each low-order group digital signal into a - series digital signal based on a clock signal of a predetermined period, and a signal synthesis circuit that synchronizes the serial digital signal from this signal synthesis circuit with its output period and shapes the waveform. The present invention also relates to a signal multiplexing circuit having a synchronous flip-flop circuit for obtaining regular high-order group digital signals.

[Prior Art] Conventionally, there is a signal multiplexing circuit of this type as shown in FIG. 7, for example.

In the figure, 10 indicates four low-order group digital signals Di1 . . . each having a pit rate of n bits/Sec. D
i2. D i3. D i4 4n pit, 'sea
This is a signal synthesis circuit that multiplexes and synthesizes serial digital signals of - with a pit rate of ) i1 to Qi4 are butufa 1
1 to 14, and the serial digital signals synthesized based on a clock signal of a predetermined period as will be described later are output from output ports (Q, Q).

Further, 20 is a synchronous flip-flop circuit, and this flip-flop circuit 20 inputs the serial digital signal output from the signal synthesis circuit 10 and corresponds to a pit rate of 4n bits/sea of the serial digital signal. It operates in synchronization with a clock signal with a period of
As a result, the serial digital signal is waveform-shaped. The signal output from this flip-flop circuit 20 is 4n bits/sec. The signal is transmitted as a regular high-order group digital signal with a pit rate of 1 to a subsequent line via the buffer 22.

Here, as mentioned above, the flip-flop circuit 20 has four
While operating in synchronization with a clock signal having a period corresponding to a bit rate of n bits/sea, the signal synthesis circuit 10 operates in synchronization with a clock signal having a period corresponding to a bit rate of 2n pits/sea and n bits. / sea
It operates based on a second clock signal having a period corresponding to the pit rate of .

Specifically, the clock is created by using a clock signal having a period corresponding to the fastest pit rate of 4n bits/sea as a reference clock signal. Then, the reference clock signal passed through the buffer 15 is frequency-divided by a frequency divider circuit 16 composed of flip-flops, and the clock signal obtained by the frequency division is further divided by a frequency divider circuit 17 similarly composed of flip-flops. By dividing the frequency, a second tack signal for the signal synthesis circuit 10 is created whose period is four times that of the basic tack signal (period corresponding to the pit rate of n pits/sea). At the same time, a clock signal whose frequency II is twice that of the basic clock signal obtained by frequency division by the frequency dividing circuit 16 (period corresponding to a pit rate of 2n bits/See) is applied to the signal synthesis circuit 10. This is the first clock signal. In reality, the clock signal output from the frequency dividing circuit 16 is input to the signal synthesis circuit 10 via the buffers 18 and 19 as the clock signal for the cylinder 1.

Here, the buffers 18 and 19 are required as follows:
Since the frequency of the output signal from the frequency dividing circuit 16 is further divided by the frequency dividing circuit 17 for the second clock signal, the delay in the frequency dividing circuit 17 causes the signal synthesis circuit 10 to
This is to prevent the phases of the first and second clock signals from being shifted. In particular, when multiplexing signals at high bit rates, delays in each circuit component become a problem.

Regarding the synchronous clock signal to the flip-flop circuit 20, since the flip-flop circuit 20 is operated in synchronization with a clock signal having a period corresponding to the pit rate of 4n pits/5o(j), the above reference clock signal is It is used as it is as the synchronous clock signal.Actually, because it is necessary to align the phase with the serial digital signal output from the signal synthesis circuit 10, the frequency division circuits 16 and 17 and the signal synthesis circuit 10 In consideration of the delay, the reference clock signal that has passed through the buffer 15 is further input to the flip-flop 20 through the number of stages of buffers 21 that can increase the delay.

As described above, the signal synthesis circuit 10 and the flip-flop 2
Four low-order group digital signals Di1 to Di4 each have a bit rate of n bits/sec by operating in synchronization with a clock signal created by taking into account the delay of circuit components etc. from the reference clock signal. is 4n bits/Se
It is multiplexed into a higher-order group digital signal with a bit rate of e.

[Problems to be Solved by the Invention] By the way, the conventional signal multiplexing circuit as described above has a problem in that it consumes a relatively large amount of power.

This is based on the following reasons.

The conventional signal multiplexing circuit as described above creates a clock signal to be provided to the signal synthesis circuit using the clock signal to be provided to the final stage flip-flop circuit as a reference, and when creating the clock signal, various frequency division methods are used. This will require a circuit. Therefore, due to delays in the various frequency dividing circuits, the signal synthesis circuit operates in synchronization with a clock signal whose phase is shifted by the If delay time from the reference clock signal. Therefore, for the clock signal provided to the final stage flip-flop circuit, in addition to the delay in the signal synthesis circuit, it is necessary to take into account the delay in the various frequency dividing circuits mentioned above. The clock signal is provided to the flip-flop circuit through a number of stages of buffers sufficient to increase the delay.

Further, although the buffer is composed of a gate circuit or the like, the power required to drive one gate is not a negligible value.

Therefore, is it necessary to provide a buffer that takes into account the delays of the various frequency divider circuits mentioned above? This results in more power being consumed than necessary.

Therefore, an object of the present invention is to reduce as much as possible the number of buffers that must be provided in consideration of delays caused by various circuit components.

[Means for Solving the Problems] As shown in FIG. 1, the present invention provides a plurality of low-order group digital signals SLI having a predetermined bit rate.

A signal synthesis circuit 1 which inputs SL2, SL3, . Then, the serial digital signal from this signal synthesis circuit 1 is waveform-shaped in synchronization with its output cycle,
A signal multiplexing circuit is assumed to have a synchronous flip-flop circuit 2 that obtains a regular high-order group digital signal SH, and technical means for solving the above problem in the signal multiplexing circuit are as follows: A multiplier circuit 3 is provided for multiplying a clock signal to be provided to a synchronous flip-flop circuit to generate a clock signal SLh to be provided to a synchronous flip-flop circuit.

[Operation] The signal synthesis circuit 1 multiplexes and synthesizes the low-order group digital signals SL1 to Sun based on the clock signal @CL to create a faster serial digital signal SS. The flip-flop circuit 2 operates in synchronization with the clock signal from the multiplier circuit 3, performs waveform shaping on the serial digital signal SS, and outputs a normal high-order group digital signal SH.

In this case, when determining the phase of the clock signal generated by the multiplier circuit 3, only the redundant time in the signal synthesis circuit 1 needs to be considered.

[Embodiments of the invention] Embodiments of the present invention will be described below based on the drawings.

FIG. 2 is a circuit diagram showing an example of a signal multiplexing circuit according to the present invention.

This example is similar to the one shown in FIG.
The purpose is to multiplex four low-order group digital signals Di1 to Di4 to bit rate 1 of eC8 to obtain a high-order group digital signal having a bit rate of 4n bits/sec.

The configuration is also basically the same as that shown in FIG. That is, the signal synthesis circuit 10 inputs each low-order group digital signal Di1 to Di4 via the buffers 11 to 14 and multiplexes and synthesizes it into a - series digital signal, and the flip-flop 20 shapes the waveform of this series digital signal. The normal high-order group digital signal obtained by 1q is transmitted to the next stage via the buffer 22. Furthermore, the signal synthesis circuit 10
In this case, a reference clock signal having a period corresponding to a bit rate of 4n bits t"/sec is divided into frequency dividing circuits 16 and 17.
The second clock signal (n bits/sec
A clock signal (with a period corresponding to a bit rate of 2n bits/5f30.) is supplied from the frequency dividing circuit 16 (with a period corresponding to a bit rate of 2n bits/5f30.).
is supplied as a first clock signal via buffers 18 and 19.

Here, the clock signal supplied to the flip-flop 20 is obtained by multiplying the first clock signal supplied to the signal synthesis circuit 10. That is, the clock signal is outputted from a multiplier circuit 30 that multiplies a clock signal having a period corresponding to a bit rate of 20 bits/sec via the buffer 19 to 1/2 the period (corresponding to a bit rate of 4n bits/sec). The clock signal is used as a synchronization signal for the flip 70 and the knob 20.

A specific configuration of the multiplier circuit 30 is shown in FIG. 3, for example.

This is a resonant circuit whose resonant frequency is set to a frequency f corresponding to 4n bits/SeC, and its basic configuration is a capacitor Co for determining the resonant frequency.
, an R10 circuit consisting of an inductor LO and a resistor RO, a differential pair of transistors Tr1 and Tr2, and their peripheral circuits (transistors Tr3, Tr4, Tr5, resistors R1, R
2).

The buffer 1 is connected to the base of the transistor Tr1.
9 or the clock signal @(CI/2) is input, and the reference voltage vrar is input to the base of the transistor Tr2, and the voltage level of the input clock signal exceeds the reference voltage V ref and the following conditions. and the relevant transistor Trl.

Tr2 is switched on and off.

Then, the resonance frequency f included in the input clock signal is
The component will be output from terminal C in FIG. That is, through the buffer 19 or the OFF signal (2n
A clock signal (corresponding to the bit rate of 4n bits/SeC, bits) having a frequency twice that of bit/5e (corresponding to the bit rate of j) is output from the multiplier circuit 30.

Note that the actual characteristics of the above-mentioned resonant circuit are such that the Q value at the resonant frequency f is as large as possible and the gain is set to about 20 dB.

The phase relationships of the various clock signals generated as described above are shown in FIG. 4, for example.

The clock signal output from the frequency divider circuit 16 is delayed by tpdl with respect to the reference clock signal with period tw (actually the signal @ via the buffer 15 in FIG. 2), and the clock signal output from the frequency divider circuit 17 is delayed by tpdl. The signal is further delayed by tpd2 than the clock signal from frequency divider circuit 16. Therefore, the second clock signal for the signal synthesis circuit 10 is delayed by tpdl + tpd2 with respect to the reference signal. Then, buffer 1 in FIG.
8. The delay in 19 is the same as the delay in the frequency divider circuit 17 above.
pd2, and the first clock signal to the signal synthesis circuit 10 has the same phase as the second clock signal (similar to that shown in FIG. 7).

Further, the phase of the serial digital signal that is multiplexed and synthesized based on the first and second clock signals and output from the signal synthesis circuit 10 is further tpd3 from the clock signal.
There will be a delay. On the other hand, a delay also occurs in the multiplier circuit 30, and the delay is only tpd4 with respect to the second clock signal.

Here, since the circuit scales of the signal synthesis circuit 10 and the multiplier circuit 30 are approximately the same, the delay times tpd3 and t
pd4 are approximately equal. Therefore, the phase of the serial digital signal from the signal synthesis circuit 10 is delayed by tDdl + tDd2 + tpd3 with respect to the reference clock, and the clock signal to the flip-flop 20 is delayed by tpdl + tpd2 + tpd4 with respect to the reference clock. The phases of are aligned.

FIG. 5 shows another embodiment of the multiplier circuit 30.

In this example, the output S and the inverted output S of the buffer 19 in FIG. 2 are input to create a clock signal having a frequency of 18 of the clock signal from the buffer 19.

Specifically, transistor Tr6. A first differential pair consisting of transistor Tr7 and transistor Tr8. The second differential pair consisting of Tr9 and its peripheral circuit (transistors Tr10, Tr
ll, resistors R3, R4, R5, R6), and further includes a transistor T in the first differential pair.
A buffer 19 is connected to the base of r6 via a capacitor C1.
The output S of the buffer 19 is input to the base of the transistor Tr8 in the second differential pair, while the inverted output S of the buffer 19 is input to the base of the transistor Tr8 in the second differential pair. A reference voltage Vrer is applied to the bases of the transistors Tr7 and Tr8, respectively.

When the clock signal from the buffer 19 is input to the transmitter 8 circuit as shown in FIG. On the other hand, the transistor Tr
The voltage waveform applied to the base of 8 becomes the differential waveform of the inverted output. Then, a rectangular wave is formed in a portion where each differential waveform exceeds the reference voltage Vref, and a clock signal having a period twice that of the input clock signal is output from the output terminal C (C).

Even with such a multiplier circuit, its circuit scale is comparable to that of the signal synthesis circuit 10, and the delay tpd4 in the multiplier circuit is also the same as the delay tpd3 and WFj in the signal synthesis circuit 10.

As described above, according to this embodiment, the first clock signal for the signal synthesis circuit 10 is multiplied to obtain an output voltage for the flip-flop 20, and the circuit scale of the multiplication circuit 30 is the same as that for the signal synthesis circuit 10. , so there is no need for a buffer that takes delay into account.

Furthermore, the consumption t in the multiple stages of buffers 21 in FIG.
The power consumption in the multiplier circuit 30 as shown in FIGS. 3 and 5 is actually lower than the If power.

[Effects of the Invention] As explained above, according to the present invention, only the delay in the signal synthesis circuit needs to be considered for the phase of the clock signal created by the multiplier circuit. Buff? can reduce the number of Therefore, the power consumed by the buffer including a gate circuit or the like can be minimized, and as a result, unnecessary power consumption can be reduced.

[Brief explanation of drawings]

Fig. 1 is a principle diagram of the present invention, Fig. 2 is a circuit diagram showing an example of a signal multiplexing circuit according to the invention, Fig. 3 is a circuit diagram showing an example of the configuration of a multiplier circuit, and Fig. 4 is a circuit diagram showing each clock signal. 5 is a circuit diagram showing another configuration example of the multiplier circuit, FIG. 6 is a timing diagram showing the differential of the multiplier circuit shown in FIG. 5, and FIG. 7 is a conventional FIG. 2 is a circuit diagram showing an example of a signal multiplexing circuit. 1.10...Signal synthesis circuit 2...Flip-flop circuit 3...Multiplier circuit 20...Flip-flop 30...Multiplier circuit Patent applicant: Fujitsu Limited, Ni. Agent Patent Attorney Igata Sada --- -〇' Ren 1st Rei SX Odo's 4 Toys 19 71i? N fri1 (third cause

Claims (1)

[Claims] A plurality of low-order group digital signals SL having a predetermined bit rate.
1. Input SL2, SL3, ..., SLn in parallel,
A signal synthesis circuit (1) that multiplexes and synthesizes each low-order group digital signal into a serial digital signal SS based on a clock signal CL having a predetermined period; A synchronous flip-flop circuit (2
), comprising a multiplier circuit (3) that multiplies the clock signal CL to be provided to the signal synthesis circuit (1) to create a clock signal CLh to be provided to the synchronous flip-flop (2). A signal multiplexing circuit characterized by: