JPH0345546B2 - - Google Patents
Info
- Publication number
- JPH0345546B2 JPH0345546B2 JP57084337A JP8433782A JPH0345546B2 JP H0345546 B2 JPH0345546 B2 JP H0345546B2 JP 57084337 A JP57084337 A JP 57084337A JP 8433782 A JP8433782 A JP 8433782A JP H0345546 B2 JPH0345546 B2 JP H0345546B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- level
- terminal
- circuit device
- external terminal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000010355 oscillation Effects 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
Description
【発明の詳細な説明】
本発明は、集積回路装置に関し、特に、発振器
を内蔵する集積回路装置に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device having a built-in oscillator.
集積回路の集積度の向上にともない１つの集積
回路を汎用的に使用する事は困難になりつつあ
る。しかし、集積回路は、少品種大量に生産され
てこそ価格の低下が期待でき、従つて汎用的でな
くなることは、多品種少量生産につながるためあ
まり好ましい事ではない。このため大規模集積回
路装置（以下LSIと略す）に於いては、ほとんど
プログラマブルなものになつておりその応用され
る分野を広くする努力がはらわれている。 As the degree of integration of integrated circuits increases, it is becoming difficult to use one integrated circuit for general purposes. However, the price of integrated circuits can only be expected to fall if they are produced in small quantities in large quantities, and it is not very desirable for integrated circuits to become less versatile, as this will lead to the production of a large variety in small quantities. For this reason, most large-scale integrated circuit devices (hereinafter abbreviated as LSI) are programmable, and efforts are being made to widen the fields in which they can be applied.
しかし、プログラマブルにしてもLSIの外部端
子の数は変らないため、応用範囲の拡大もそれな
ど大きなものではなかつた。 However, since the number of external terminals on an LSI remains the same even if it is made programmable, the expansion of the range of applications was not significant.
本発明は、発振器を内蔵し、外部に２端子の共
振回路を接続して使用する集積回路装置で、その
発振器を使用せず、外部から供給されるクロツク
で動作する所謂外部クロツク・モードに於いて、
発振のために使用されていた端子をその他の目的
に使用できる手段を有する集積回路装置を提供す
るものである。 The present invention is an integrated circuit device that has a built-in oscillator and is used with a two-terminal resonant circuit connected to the outside. There,
It is an object of the present invention to provide an integrated circuit device having a means for using terminals used for oscillation for other purposes.
本発明による集積回路装置は、集積回路装置の
外部に接続される共振回路と共同して発振回路を
構成し動作の基本となるクロツクを発生する回路
手段と、この回路手段の一方の端子と集積回路装
置内の所定の信号とを切り換えて第１の外部端子
に接続する選択手段と、集積回路装置の内部に所
定の情報を第１および第２のレベルを使つて伝達
するための信号が入力される第２の外部端子と、
この第２の外部端子に接続され、第２の外部端子
が第１又は第２のレベルであることを検出すると
ともに第１および第２のレベルのいずれとも異な
る第３のレベルであることを検出して、第１又は
第２のレベルを検出したときは選択手段に対して
第１の外部端子に回路手段の一方の端子を接続す
るように指令し、第３のレベルを検出したときは
選択手段に対して集積回路装置内の所定の信号を
接続するように指令する制御手段とを具備する事
を特徴とする。 An integrated circuit device according to the present invention includes a circuit means that forms an oscillation circuit in cooperation with a resonant circuit connected to the outside of the integrated circuit device and generates a clock that is the basis of operation, and one terminal of this circuit means and an integrated circuit. a selection means for switching between a predetermined signal within the circuit device and connecting it to a first external terminal; and a signal for transmitting predetermined information to the inside of the integrated circuit device using the first and second levels. a second external terminal,
is connected to this second external terminal, detects that the second external terminal is at the first or second level, and detects that the second external terminal is at a third level different from both the first and second levels. When the first or second level is detected, the selection means is instructed to connect one terminal of the circuit means to the first external terminal, and when the third level is detected, the selection means is instructed to connect one terminal of the circuit means to the first external terminal. It is characterized by comprising a control means for instructing the means to connect a predetermined signal within the integrated circuit device.
上記第２の外部端子はリセツト端子が好まし
く、このリセツト端子に該第１のレベルが供給さ
れたときは集積回路装置の内部回路は初期状態に
設定され、リセツト端子に第２のレベルが供給さ
れたときは内部回路の初期状態は解除され、リセ
ツト端子に第３のレベルが供給されたときは内部
回路は初期状態の解除状態となる。 Preferably, the second external terminal is a reset terminal, and when the first level is supplied to the reset terminal, the internal circuit of the integrated circuit device is set to the initial state, and the second level is supplied to the reset terminal. When this happens, the initial state of the internal circuit is released, and when the third level is supplied to the reset terminal, the internal circuit becomes the initial state released.
以下、図面を用いて本発明の一実施例について
説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第１図は、本発明の一実施例のブロツクダイア
グラムである。 FIG. 1 is a block diagram of one embodiment of the present invention.
発振器１の入力端子は、外部端子４に接続さ
れ、出力端子は、選択回路２及び第１図の回路を
内蔵する集積回路内部の他の複数の機能ブロツク
９に接続され集積回路内の各ブロツクの同期を取
るために使用される。選択回路２は３値レベル検
出器３からの切り換え信号８が高レベルの時は外
部端子５に発振器１の出力を接続し、切り換え信
号８が低レベルの時は、外部端子５に該集積回路
内の特定の信号線７を接続する。 The input terminal of the oscillator 1 is connected to an external terminal 4, and the output terminal is connected to the selection circuit 2 and a plurality of other functional blocks 9 inside the integrated circuit including the circuit shown in FIG. used to synchronize. The selection circuit 2 connects the output of the oscillator 1 to the external terminal 5 when the switching signal 8 from the three-level level detector 3 is at a high level, and connects the output of the oscillator 1 to the external terminal 5 when the switching signal 8 is at a low level. Connect a specific signal line 7 within.
３値レベル検出器３は、外部端子６に加えられ
た＋１、０、−１の３つのレベルを検出し、その
レベルが＋１の場合は、切り換え信号８を高レベ
ルにし、集積回路内の特定の機能ブロツクへの信
号１０を高レベルにする。外部端子６に０レベル
が加えられると、切り換え信号８は高レベルとな
り、信号１０は低レベルとなる。また、外部端子
６に−１レベルが加えられると、切り換え信号８
は低レベルとなり信号１０は高レベルとなる。 The ternary level detector 3 detects the three levels +1, 0, and -1 applied to the external terminal 6, and when the level is +1, it sets the switching signal 8 to high level and detects a specific signal in the integrated circuit. The signal 10 to the functional block is set high. When a 0 level is applied to the external terminal 6, the switching signal 8 becomes high level and the signal 10 becomes low level. Also, when -1 level is applied to external terminal 6, switching signal 8
becomes low level and signal 10 becomes high level.
次に、第１図の実施例の具体的応用例を示す。 Next, a specific application example of the embodiment shown in FIG. 1 will be shown.
外部端子６は該集積回路のリセツト信号入力端
子及びクロツク切り換え端子として機能する。つ
まり、該集積回路を内部クロツク・モードで使用
する場合には、外部端子６は０レベル・アクテイ
ブのリセツト端子として使用され、その場合には
端子６には＋１または０レベルが入力され、共振
回路が外部端子４及び５間に接続される。このモ
ードでは、外部端子６のレベルが＋１、０のどち
らのレベルであれ、外部端子５には発振器１の出
力が接続されるため、発振器１は、上記共振回路
の共振周波数で発振をし続ける。また、このモー
ドでは、信号１０は、該集積回路の低レベル・ア
クテイブのリセツト信号として動作する。 The external terminal 6 functions as a reset signal input terminal and a clock switching terminal for the integrated circuit. That is, when the integrated circuit is used in the internal clock mode, the external terminal 6 is used as a 0 level active reset terminal, in which case a +1 or 0 level is input to the terminal 6, and the resonant circuit is connected between external terminals 4 and 5. In this mode, regardless of whether the level of external terminal 6 is +1 or 0, the output of oscillator 1 is connected to external terminal 5, so oscillator 1 continues to oscillate at the resonant frequency of the above-mentioned resonant circuit. . Also in this mode, signal 10 operates as a low level active reset signal for the integrated circuit.
次に、該集積回路を外部クロツク・モードで使
用する場合には、外部端子６は、０または−１レ
ベルが入力される０レベル・アクテイブのリセツ
ト端子として動作する。このモードでは、該集積
回路の外部発生されたクロツク信号を外部端子４
に入力するが、外部端子５は、前期内部クロツ
ク・モードの時とは異なり、該集積回路にリセツ
トがかかつていない通常動作の場合には、該集積
回路の特定の機能ブロツクの信号線７が接続され
る。つまり、外部クロツク・モードに於いては、
内部クロツク・モードの時とくらべて１端子だけ
有効外部端子が増加する。 Next, when the integrated circuit is used in the external clock mode, the external terminal 6 operates as a 0 level active reset terminal to which a 0 or -1 level is input. In this mode, the integrated circuit's externally generated clock signal is transferred to the external terminal 4.
However, unlike in the previous internal clock mode, the signal line 7 of a specific functional block of the integrated circuit is Connected. In other words, in external clock mode,
The number of valid external terminals increases by one terminal compared to the internal clock mode.
以上説明した通り、発振器を内蔵する集積回路
が内部クロツク・モードと外部クロツク・モード
の２つのモードで使用される可能性がある場合、
本発明によれば外部クロツク・モードで使用する
場合には、有効な外部端子を１つ増加させる事が
でき、端子数の制約のきびしい集積回路に於いて
は大きな利点となる。 As explained above, if an integrated circuit containing an oscillator can be used in two modes: internal clock mode and external clock mode,
According to the present invention, when used in external clock mode, the number of effective external terminals can be increased by one, which is a great advantage in integrated circuits where the number of terminals is severely restricted.
なお、第１図に於いて、発振器１の帰環抵抗は
固定抵抗の様に描いているが、これは固定抵抗で
ある必要はなく、MOSトランジスタのON抵抗
を利用したものでもよい。その場合には、外部ク
ロツク・モードに指定された場合は、該MOSト
ランジスタをOFFして、発振器を単なるインバ
ータとして動作させてもよい。また、実施例の説
明では、選択回路の切り換え手段として、リセツ
ト端子を例にあげたが、これも他の端子、たとえ
ばLSIのTEST端子等でも同様の機能が得られる
事は言うまでもない。 Note that although the return resistance of the oscillator 1 is depicted as a fixed resistance in FIG. 1, it does not need to be a fixed resistance and may be one that utilizes the ON resistance of a MOS transistor. In that case, if the external clock mode is designated, the MOS transistor may be turned off and the oscillator may operate as a mere inverter. Further, in the description of the embodiment, the reset terminal was used as an example of the switching means of the selection circuit, but it goes without saying that the same function can be obtained with other terminals, such as the TEST terminal of an LSI.
TEST端子を使用する場合には、LSIの製造者
が出荷時等に行う検査をより簡単に、また、高速
に行う手段として本発明により増加した端子を使
用する事ができる。 When using TEST terminals, the number of terminals increased according to the present invention can be used as a means for easier and faster testing performed by LSI manufacturers at the time of shipment.
第１図は、本発明の一実施例のブロツク・ダイ
アグラムである。
なお図において、１……発振器、２……選択回
路、３……３値レベル検出器、４，５，６……外
部端子、７……信号線、８……切り換え信号線、
９……機能ブロツク、１０……信号線、である。
FIG. 1 is a block diagram of one embodiment of the invention. In the figure, 1... oscillator, 2... selection circuit, 3... ternary level detector, 4, 5, 6... external terminal, 7... signal line, 8... switching signal line,
9...Function block, 10...Signal line.
Claims (1)
部に接続される共振回路と共同して発振回路を構
成し動作の基本となるクロツクを発生する回路手
段と、該回路手段の一方の端子と該集積回路装置
内の所定の信号とを切り換えて第１の外部端子に
接続する選択手段と、該集積回路装置の内部に所
定の情報を第１および第２のレベルを使つて伝達
するための信号が入力される第２の外部端子と、
該第２の外部端子に接続され、該第２の外部端子
が該第１又は第２のレベルであることを検出する
とともに該第１および第２のレベルのいずれとも
異なる第３のレベルであることを検出して、該第
１又は第２のレベルを検出したときは該選択手段
に対して該第１の外部端子に該回路手段の一方の
端子を接続するように指令し、該第３のレベルを
検出したときは該選択手段に対して該集積回路装
置内の所定の信号を接続するように指令する制御
手段とを具備する事を特徴とする集積回路装置。 ２ 特許請求の範囲第１項記載の集積回路装置に
おいて、該第２の外部端子はリセツト端子であ
り、該リセツト端子に該第１のレベルが供給され
たときは該集積回路装置の内部回路は初期状態に
設定され、該リセツト端子に該第２のレベルが供
給されたときは該内部回路の初期状態は解除さ
れ、該リセツト端子に該第３のレベルが供給され
たときは該内部回路は初期状態の解除状態となる
ことを特徴とする集積回路装置。[Scope of Claims] 1. In an integrated circuit device, a circuit means that forms an oscillation circuit in cooperation with a resonant circuit connected to the outside of the integrated circuit device and generates a clock that is the basis of operation, and a circuit means for generating a clock that is the basis of operation. selecting means for switching between one terminal and a predetermined signal within the integrated circuit device and connecting it to a first external terminal; a second external terminal into which a signal for transmission is input;
connected to the second external terminal, detects that the second external terminal is at the first or second level, and is at a third level different from both the first and second levels; When it detects that the first or second level is detected, it instructs the selection means to connect one terminal of the circuit means to the first external terminal; an integrated circuit device, comprising control means for instructing the selection means to connect a predetermined signal within the integrated circuit device when the level of the integrated circuit device is detected. 2. In the integrated circuit device according to claim 1, the second external terminal is a reset terminal, and when the first level is supplied to the reset terminal, the internal circuit of the integrated circuit device When set to the initial state and the second level is supplied to the reset terminal, the initial state of the internal circuit is canceled, and when the third level is supplied to the reset terminal, the internal circuit is reset. An integrated circuit device characterized by being in a released state from an initial state.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57084337A JPS58201352A (en) | 1982-05-19 | 1982-05-19 | Integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP57084337A JPS58201352A (en) | 1982-05-19 | 1982-05-19 | Integrated circuit device |
Related Child Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1293017A Division JPH02177356A (en) | 1989-11-10 | 1989-11-10 | Integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS58201352A JPS58201352A (en) | 1983-11-24 |
| JPH0345546B2 true JPH0345546B2 (en) | 1991-07-11 |
Family
ID=13827685
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP57084337A Granted JPS58201352A (en) | 1982-05-19 | 1982-05-19 | Integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS58201352A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0210869A (en) * | 1988-06-29 | 1990-01-16 | Hitachi Ltd | Semiconductor device |
| JPH02177356A (en) * | 1989-11-10 | 1990-07-10 | Nec Corp | Integrated circuit device |
| JP2682895B2 (en) * | 1990-09-05 | 1997-11-26 | シャープ株式会社 | Semiconductor integrated circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745942A (en) * | 1980-09-02 | 1982-03-16 | Toshiba Corp | Semiconductor integrated circuit device |
-
1982
- 1982-05-19 JP JP57084337A patent/JPS58201352A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5745942A (en) * | 1980-09-02 | 1982-03-16 | Toshiba Corp | Semiconductor integrated circuit device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS58201352A (en) | 1983-11-24 |
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