JPS59161761A - State setting circuit of data processor - Google Patents

Abstract

PURPOSE:To obtain a circuit which sets >=3 kinds of modes selectively by sampling and latching signals supplied to one pin at mutually different timing, and decoding sampled signals and generating state setting signals. CONSTITUTION:The mode setting pin 7 is connected to data input terminals D of FFs 8a and 8b as sampling means formed in a semiconductor chip 1. Clock signals phi1 and phi2 differing in timing are inputted from a CPU2 to clock terminals C of the FFs 8a and 8b. Consequently, the outputs of the sampled FFs 8a and 8b are supplied to the decoding circuit 9 consisting of an NAND circuit G1, inverter G2, and NOR circuits G3-G5 and decoded. Consequently, mode setting signals SS1-SS4 are generated and supplied to the CPU2 to determine the mode of the system.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field] The present invention relates to a state setting circuit in a single-chip data processing device such as a single-chip microcomputer.

[Background technology]

In a single-chip microcomputer (referred to as a single-chip microcomputer), for example, if the storage capacity of the internal ROM or RAM becomes 9, it is necessary to reduce the internal ports and connect an external bus. 1
A mode (operating state) is now being provided in which the memory area can be expanded by externally attaching a ROM or RAM.

When a single-chip microcomputer is provided with various modes as described above, a mode setting bin is required to select and set one of the modes. Moreover, if a single-chip microcontroller has two modes, only one mode setting bin is required, but as the number of functions increases and fc is equipped with three or more modes, two mode setting bins are required.
More mode setting bins are required.

However, if there is a constraint on the overall number of bins for a single-chip microcontroller, providing mode setting bins will reduce the number of active pins, restricting design freedom and limiting the functionality of the single-chip microcontroller. There is a problem that there is a risk that the performance will be lowered.

Furthermore, if an attempt is made to use the mode setting bin as a 10 port, a complicated external circuit is required, which is an inconvenience.

[Purpose of the invention]

Therefore, this invention proposes that by providing only one dedicated bin for setting the mode of a single-chip microcomputer, etc., three or more modes can be set by simply attaching an extremely cylindrical external circuit. The purpose is to make it possible to select and set one of the following.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Summary of the Invention] A brief overview of typical inventions disclosed in this application is as follows.

In other words, by sampling and latching the signal supplied to a dedicated bin (external terminal) using two or more internal clock signals, and decoding the signal to form a mode setting signal, the above can be achieved. The number of modes that can be selected according to the type of signal supplied to the bin and the clock signal for sampling has been increased, and it is now possible to select and set three or more modes with just one mode setting pin. This is what I am trying to do.

This invention will be explained below using the drawings.

〔Example〕

FIG. 1 shows an embodiment I of a single-chip microcomputer equipped with a state setting circuit according to the present invention. [In this case, 1 is a semiconductor chip made of a silicon dynamic conductor, and on top of this semiconductor chip are 0PU (microprocessor) 2, ROM (read only memory) 3, and RAM (random access memory). 4.Each circuit element constituting the port 5 and the like is integrally formed using a known semiconductor manufacturing technique.

The ROM 3, RAM 4, and port 5 of the machine 10 are connected to the 0PU2 via the internal pin 6, so that the RO
A microcomputer system is configured to process various data according to the program stored in M3.

7 is a bottle (external terminal) provided on the semiconductor chip 1
In this embodiment I, only this bin is used exclusively as a mode setting bin.

The mode setting bin 7 has a preset 5. buflop 8a
and the data input node of 8b, one child is connected. This flip-flop has a CP terminal on the terminal C of blocks 8a and 8b.
Clocks 1. with different timings as shown in FIG. 2 supplied from U2. The signals φ1 and φ2 are respectively input. In other words, each time the flip-flops 8a and 8b receive the black and white signals φ1 and φ2,
At that time, the signal supplied to the mode setting bin 7 is taken in from the data input terminal.

Therefore, when the clock signals φ1 and φ2 are input, the level of the signal supplied to the mode setting bin 7 is PJU.
(If the high level material is a low novel, then the outputs Q and Q of flip-flops 8a and 8b are the same.) If they are different, then the outputs Q and Q of flip-flops 8a and 8b are the same. There are many things that are not done.

In the microcomputer system fB, circuits within the system are generally synchronized using two or more system clock signals. Therefore, in the embodiment, the above-mentioned Furi, Pflo 1. Clones 1. for sampling supplied to the tubes 8a and 8b. The system clock signal is used as it is as the signals φ1 and φ2. However, the frequency of the system clock signal may be further divided to form the clock signals φl and φ2, or a signal with an appropriate high frequency may be output from the middle of a frequency dividing circuit for forming the system clock signal. signal φl
, φ2.

This is how I pretended to sample.

The outputs Q and Q of the flops 8a and 8b are connected to a NAND circuit G.
, and the inverter G2 and NO which inverts its output
The ROR circuits -3 to G5 are supplied to the decoder circuit 9 and decoded. As a result, mode setting signals (state setting signals) SS, -S84 are generated and supplied to 0PU2 to determine the mode of the system.

Therefore, if mode setting bin 7 is not fixed at high level, free 1. The outputs Q of the block flops 8a and 8b are set to a high level, and the outputs Q of the block flops 8a and 8b are set to a low level.

Therefore, in the decoder circuit 9, only the output of the inverter G2 is set to high level, and the other NOR circuits 03 to
All outputs of G5 are set to low level. As a result, the mode setting signal BB is supplied to the CPU 2.

Next, if the mode setting bin 7 is fixed at low level, the free 1. The outputs Q of the flip-flops 8a and 8b are both set to low level, and the output Q is set to high level. Therefore, only the output of NOR circuit G3 in decoder circuit 9 is set to high level, and inverter G2 and NOR circuit G
4, all outputs of G5 are set to low level. As a result, a mode setting signal SS2 is formed and supplied to the CPU2.

Also, if the signal E is not supplied to the mode setting bin 7, for example as shown in FIG. 2 (0), the flip-flop 8
The output Q of a is set to low level, and the flip-flop 8b
The output Q becomes high level.

Therefore, in the decoder circuit 9, only the output of the NOR circuit G4 is set to high level, and the output of the inverter G2 and the NO
The outputs of R circuits G3 and G5 are set to low level. This forms mode setting signal SS3.

Furthermore, when the tallock signal E having the opposite phase to the clock signal E shown in FIG. The output Q of 8b goes to low level. Therefore, only the output of the NOR circuit G5 is driven to a high level to form the mode setting signal SS4.

Thus, this embodiment I''''C can form four types of mode setting signals depending on the signal or level (signal in a broad sense) supplied to the kneader with only one mode setting bin. Moreover, by increasing the types of sampling flip-flops, double-flops, and tallock signals connected to the mode setting bin 7, even more mode selection signals can be generated with one bin.

Actually, in 1, the single-chip microcontroller is the 2nd one.
Taking note of the fact that the tarock signal E shown in Figure (0) is also used as a system clock signal, it is temporarily taken out of the chip 1 and then used as is or inverted to enable the mode. By supplying the setting bin 7, the external circuit can be simplified.

However, when forming the mode setting signals S81 and ss2, a high level signal or a low level signal to be supplied to the mode setting bin 7 can be easily and easily provided by connecting a pull-up resistor or a pull-down resistor to this bin. 1. −& Exterior can be realized with a circuit.

In the above embodiment, it is used as a means for sampling the material signal supplied to the fixed bin 7.

Although flip-flops 8a and 8b are used, the present invention is not limited to this. For example, as shown in FIG. 3, the sampling switch M connected to the mode setting bin 7
O8FETQ,, and this switch MOS F
Inverter jt, 12 and inno (-1120M3) connected to mode setting bin 7 via E T Q, ,
Switch M that returns power to the inverter 110 input terminal
From O8FE'rQ2.

A sampling means can be constituted by the child circuit 10. This circuit samples the signal that is not being supplied to the mode setting bin 7 with the switch MOSFETQ, which is turned on by the clock signal φ1 or φ2, and converts the sampled level to the high level of the control signal φC. It can be held in the Sochi circuit 10 for a period of . Furthermore, the decoder circuit 9 is not limited to the configuration shown in FIG.

〔effect〕

As mentioned above, according to the present invention, the signal supplied to a dedicated bin (external terminal) is sampled using two or more internal black and white signals, and the signal is then decoded. By forming a mode setting signal, the number of modes that can be selected is increased depending on the type of signal supplied to the above pin and the clock signal for sampling, and there are 3 types with only one mode fixed bin. The effect is that the above modes can be selectively set.

This also allows the number of active pins to be increased by varying the number of mode setting bins without the need for any additional circuitry.

Above all, the invention developed by Nagisa has been specifically explained based on the practical example 1, but the present invention is not limited to the above practical example 1, and various modifications may be made without departing from the gist thereof. It goes without saying that it is possible.

[Application field]

In the above explanation, the present invention was mainly applied to a single-chip microcomputer.
The present invention is not limited to small scale devices, but can be applied to data processing devices in general, such as LSIs for desktop calculators and other single-chip data processing devices.

[Brief explanation of the drawing]

FIG. 1 shows an actual example of a single-chip microcomputer [1f1. 2 is a timing chart showing an example 1 of the timing of black and vine signals used in the single-chip microcomputer, and FIG. 3 is a circuit diagram showing another configuration 1jl of the sampling means. . 1...Semiconductor chip, 6...Internal bus □, 7...
Mode setting bins, 8a, 8b...sampling means (
Free 9. 9...decoder circuit, φl
, φ2... Ri1 Rovk signal, ss1 to SS4... Mode setting signal. Agent Patent Attorney Akio Takahashi

Claims (1)

[Claims] 1. In a data processing device that is formed on a semiconductor chip and has a clock signal inside, a signal is connected to one pin provided on the semiconductor chip and supplied to this bin from the outside. It consists of a plurality of sampling means that perform sampling and a decoder circuit that decodes the output signal of the sampling means, and the plurality of sampling means perform the sampling at different timings based on the clock signal 1c. A state setting circuit in a data processing device whose mission is to form three or more state setting signals by sampling a signal supplied to a pin.