JPH0396034A - Advance priority selection circuit - Google Patents

Abstract

PURPOSE:To execute advance priority selection control even with a slight time difference by inputting a strobe signal representing the input of a signal to a selection control circuit so as to output a signal inputted precedingly. CONSTITUTION:When a signal data A is inputted to a terminal a of a selection circuit 1, a strobe signal S(A) ('0') is fed to an OR circuit 5-1. As a result, a level '0' is outputted from the OR circuit 5-1 and a level '1' is outputted from a NOT AND circuit 6-1. On the other hand, an inverted strobe signal inverse of S(A) is inputted to an OR circuit 5-2, from which a level '1' is outputted and the NOT AND circuit 6-1 outputs '1'. That is, while the signal data A is inputted to the terminal a of the selection circuit 1, even when a signal data B is inputted to other terminal b, the output of the NOT AND circuit 6-1 remains logical 1 and the signal data A is outputted succeedingly from the selection circuit 1.

Description

[Detailed Description of the Invention] [Summary] This invention relates to a first priority selection circuit used in communication devices, etc., which has two input terminals and selects and outputs the signal from the terminal input first. The purpose of this circuit is to provide a first priority selection circuit that can realize first priority even if there is a slight difference in terms of performance. In a first priority selection circuit having a selection circuit that selects and outputs an input signal, a strobe signal indicating that a signal is input is input, the selection circuit selects and outputs the signal input first, and one of the signals is selected and output. A selection control circuit is provided to output a control signal to the selection circuit so as not to output a signal input later to the other terminal while a signal is being input to the other terminal.

[Industrial application field]

The present invention relates to an improvement in a first priority selection circuit used in communication devices and the like, which has two input terminals and selects and outputs the signal from the terminal inputted first.

For example, when carrying out expansion work on a communication device, etc., connect a connector to each input terminal of a device that has multiple input terminals and input No. f data, memorize the connection and input order of signal data. It is necessary to output the input signal data in the order of input (giving priority to the first one) from the viewpoint of preventing destruction of the signal data.

For this reason, there is a need for a first priority selection circuit that is compact and can implement first priority even if there is a slight difference in time.

[Conventional technology]

FIG. 3 is a block diagram showing the structure of a prior art priority selection circuit.

In FIG. 3, signal data A is a selection circuit (hereinafter SEL).
) 1, or signal data B is input to terminal b. Now, for example, signal data A is SEL 1
Suppose that an input is made to terminal a of . At the same time, a strobe signal S (A) indicating that signal data A has been input is input to the D terminal of the flip-flop circuit (hereinafter referred to as FF) 2-1. Then, CF'U (
F
By adding it to the C terminal of F2-1, S(
A)' is output.

This output S(A)' is input to the control circuit 3, and SEL1
A control signal for selecting signal data A is output to SEL1. In SEL 1, signal data A is selected and output by this control signal input.

Also, stop inputting signal data A and SEL signal data B.
Suppose that an input is made to terminal b of No. 1. Then, the strobe signal S is applied to the D terminal of FF2-2 in the same way as in the above case.
(B) is input, and S(B)' is input to the control circuit 3 from the Q terminal by the sampling clock input to the C terminal. The control circuit 3 outputs a control signal for selecting signal data B at SEL1 to SEL1. SEL
1, signal data B is selected and output by this control signal input.

In this way, they made choices that prioritized the first.

[Problem to be solved by the invention]

However, the above-mentioned circuit requires a clock and a register for sampling, so there is a problem that the hardware becomes large.

Furthermore, since the strobe signal is sampled using a clock, there is a problem that there is a delay of one clock in the sampling clock from when the strobe signal is actually generated until switching is performed by SEL.

Furthermore, as shown in Fig. 4, even if there is a certain time difference between the strobe signals A and B, if the sampling points are the same, the strobe signals can be seen at the same time, so the one that is not actually given priority is selected. There is a problem that there are cases where the signal data is destroyed, and the signal data may be destroyed.

SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a first priority selection circuit which is small in size and can realize first priority even if there is a slight difference in time.

[Means to solve the problem]

The above problem is solved by the circuit structure shown in FIG.

That is, in FIG. 1, the first priority selection circuit is a circuit having two input terminals and into which signals can be input, and has a selection circuit 100 that selects and outputs the signal input first. 600 inputs a strobe signal indicating that a signal has been input, selects and outputs the signal input earlier in the selection circuit, and while a signal is input to one terminal, outputs the signal input later to the other terminal. This is a selection M control circuit that outputs a control signal to the selection circuit to prevent this from occurring.

[For production]

In FIG. 1, a strobe signal indicating that a signal has been input is input to the selection control circuit 600, and the selection circuit 100
A control signal is output to the selection circuit 100 to select and output the signal inputted earlier, and to prevent the signal inputted later from the other terminal from being outputted while the signal is inputted to one terminal.

As a result, priority can be achieved even if there is a slight difference in time. Further, since it is not necessary to use as many gate circuits as in the conventional example, the circuit can be made smaller.

〔Example〕

FIG. 2 is a block diagram showing the structure of a circuit according to an embodiment of the present invention.

The same reference numerals indicate the same objects throughout the figures.

In FIG. 2, it is assumed that when signal data A is input to terminal a of SEL 1, the strobe signal S (A) becomes "0" (the circuit configuration is reversed from the conventional example). This S(A) ("0#) is added to a logic phase circuit (hereinafter referred to as OR circuit) 5-1. OR circuit 5-1 is supplied with strobe signal S(B) (in this case, signal data B is SEL Since it is not input to l, S(B) is “1”
) is inverted to "O" via the inverter 4-1. Furthermore, a protect signal (usually "0"), which will be described later, is also applied to the OR circuit 5-1.

As a result, "0" is output from the OR circuit 5-1, and is applied to one input terminal C of a negative AND circuit (hereinafter referred to as a NAND circuit) 6-1. A NAND circuit has a property of outputting "0" when both inputs are "L", and outputting "1" when one input is "0".

Therefore, in this case, the NANO circuit 6-1 outputs "1". This output "l" is applied to one input terminal e of the NAND circuit 6-2.

On the other hand, the strobe signal S (A) (
(in this case, "0") is inverted via the inverter 4-2 to become "1" and input. Further, S(B) (“l” in this case) and a protect signal (“0”) are also input.

As a result, "1" is output from the OR circuit 5-2, and N
It is added to the other input terminal [ of the AND circuit 6-2. N
This means that "l" is added to both of the two input terminals of the AND circuit 6-2, and due to the nature of the NANO circuit, "0" is applied to both input terminals.
Output. This output "0" is applied to the other terminal d of the NAND circuit 6-1. As a result, NAND circuit 6-
1 outputs "l". That is, the NAND circuit 6-1
, 6-2 holds the output of "1" in this case, so it has the characteristics of a set/reset holding circuit (hereinafter referred to as an S, R latch circuit).

Next, while inputting signal data A to terminal a of SEL 1,
Assume that signal data B is input to terminal b of SEL1. At this time, the strobe signal S (B) becomes "O",
In addition to being added to the OR circuit 5-2, the inverter 4-
1, it is inverted to become "1", and is applied to the OR circuit 5-1. As a result, the OR circuits 5-1 and 5-2 both output "1m." The output of the OR circuit 5-1 is "l
'' is applied to the input terminal C of the NAND circuit 6-1.N
Since the output of the AND circuit 6-1 has been holding "1" until now, "1" is added to both the two input terminals e and f of the NAND circuit 6-2.
2 outputs "0". As a result, NANO circuit 6
"1" and "O" are applied to the two input terminals c and d of -1, and "1" is output from the NAND circuit 6-1.

That is, while inputting signal data A to terminal a of SEL 1,
Even if signal data B is input to terminal b of SEL l, the output of the NAND circuit 6-1 remains at "do", and SEL
1 continues to output signal data A.

Conversely, when signal data B is input to terminal b of SEL 1 without inputting signal data A to SEL 1 and signal data B is being output from SEL 1, when signal data A is input to terminal a of SEL 1. Similarly to the above case, SE
Signal data B continues to be output from L1.

Also, input signal data A to SEL 1 and
Even if signal data B is input to SEL 1 while signal data A is being output from , the output of SEL 1 will not change as described above, but if the input of signal data A is subsequently removed,
The strobe signal S (A) changes from "0" to "■", and the OR circuits 5 to 1 receive "1" as S (8), S (B)
("0") is inverted by the inverter 4-1 and "1" is input, and "1" is output from the OR circuit 5-1.

On the other hand, S (A) (“l”) is inverted by the inverter 4-2 and input as “0” to the 012 circuits 5 to 2, and “O” is input as S (B). , O
"O" is output from the R circuit 5-2. This output “0”
” is applied to the input terminal r of NAIJ[1 circuit 6-2,
Since "1", which had been held at the output of the NAND circuit 6-1, is added to the other input terminal e, "1" is output from the NAND circuit 6-2, and one of the NAND circuits 6-1 outputs "1". applied to input terminal d. As a result, "1" is added to both the two input terminals c and d of the NAND circuit 6-1, and the NAND circuit 6-1 outputs "0".

That is, the output of the NAND circuit 6-1 changes from "1" to "On", so that SEL 1 selects and outputs signal data B.

Note that the protect signal normally outputs "0", but especially the output of the S, R latch circuit (output of the NAND circuit 6-1)
When it is desired to hold S(A) and S(B) at a constant value, "l" is output, and the outputs of the S and R latch circuits are held constant regardless of the values of the strobe signals S(A) and S(B).

〔Effect of the invention〕

As described above, according to the present invention, it is possible to realize a first-priority selection circuit without sampling the strobe signal, thereby making it possible to reduce the amount of hardware.

In addition, since it uses a method based on the strobe signal level (“0”■”), strobe signals with a small time difference are not treated as simultaneous, unlike when sampling, and even a small time difference can be detected first. Priority can be achieved.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle of the present invention. FIG. 2 is a block diagram showing the circuit configuration of an embodiment of the present invention. FIG. 3 is a block diagram showing the configuration of a conventional prioritization selection circuit. FIG. 2 is a diagram illustrating a case where first priority is not realized in the conventional example. In the figure, 600 indicates a selection control circuit.

Claims (1)

[Claims] A first priority selection circuit which has two input terminals and into which signals can be input, and which has a selection circuit (100) that selects and outputs the signal input first. , a strobe signal indicating that the signal has been input is input, and the selection circuit selects and outputs the signal input earlier, and while the signal is input to one terminal, the signal input later to the other terminal is input. 1. A first priority selection circuit comprising a selection control circuit (600) for outputting a control signal to the selection circuit so as not to output the first priority selection circuit.