JPH0324661A - Bus access device for microprocessor - Google Patents

Abstract

PURPOSE:To execute bus access by the small number of external circuits by providing the bus access device with the 1st and 2nd bus access end deciding means and an end condition selecting means. CONSTITUTION:An end condition status is inputted from an external terminal 10 and the end condition of a bus cycle is formed by the 1st bus cycle end deciding means 1 in accordance with the specified number of circles. A ready signal or a wait signal is inputted from a terminal 11 and the 2nd bus cycle end deciding means 2 forms the end condition of the bus cycle. The end condition selecting means 3 includes a selector 31 and a decoder 32 and selects either one of the output conditions of the means 1, 2 in accordance with specification signals from two input terminals. When a microprocessor 6 starts bus access is said constitution, the bus access can be attained by the small number of external circuits.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention is utilized for data transfer performed by a microprocessor via a bus. The present invention relates to microprocessor bus access.

〔overview〕

The present invention provides a bus access device for a microprocessor that generates a bus cycle termination condition based on a specified number of cycles and a bus cycle termination condition based on a ready signal or wait signal, and selects one of these two conditions. , which allows bus access with fewer external circuits.

[Conventional technology]

Conventionally, when a microprocessor starts a bus access, it uses an external ready signal or wait signal as a means to end the bus cycle. (described uniformly in ready signals).

In a normal microprocessor system, when the microprocessor starts a bus access, an external circuit performs timing control to match the access time of the hardware resource being accessed, returns a ready signal at an appropriate time, and Ending the cycle.

[Problem that the invention seeks to solve]

Modern microprocessors have higher operating frequencies, making it difficult to control timing with external circuits. In addition, although the access time of external hardware resources, especially the input/output system, has hardly changed, microprocessors have become faster, resulting in the need to use expensive and power-consuming ICs for their control circuits. It has occurred.

The present invention solves these problems and aims to provide a device that can perform bus access with a small number of external circuits.

[Means for solving problems]

The present invention provides a first bus cycle end determination tool that determines the end condition of a bus cycle according to the number of cycles specified by an external terminal to which the end condition status is input, and an external terminal to which the ready signal or wait signal is input. a second bus cycle end determining means for determining a bus cycle end condition in accordance with a signal from a terminal; an output condition of the first bus cycle determining means; and an output of the second bus cycle end determining means. The present invention is characterized by comprising a termination condition selection means for determining which of the conditions to use based on specifications from the two external terminals.

[Effect]

The first bus cycle end determining means activates the bus cycle end condition with the number of cycles specified by manual input from the end condition status terminal, and the second bus cycle end determining means inputs a ready signal or a wait signal. A bus cycle termination condition is generated based on the signal input from the terminal. A termination condition selection means determines which of these two bus cycle termination conditions is to be used, and allows it to be specified from an input terminal. This allows bus access to be performed with fewer external circuits.

〔Example〕

Next, embodiments of the present invention will be described based on the drawings.

FIG. 1 is a block diagram showing the structure of an embodiment of the present invention.

The embodiment of the present invention includes a termination condition status input terminal 10, a ready signal input terminal 11, a latch 5 connected to the termination condition status input terminal 10, and a termination condition status input terminal 10 and a ready signal input terminal 11 connected to the termination condition status input terminal 10 and the ready signal input terminal 11. a bus access control circuit 4 included in a microprocessor control unit 6 that controls bus access by;
Furthermore, the embodiment of the present invention is characterized by a first bus cycle termination determination means l for generating termination conditions for a bus cycle according to the number of cycles specified by an external terminal 10 whose termination condition status is inputted manually, and a ready signal. The first bus cycle end determining means includes a second bus cycle end determining means 2 that generates a bus cycle end condition according to a signal from an external terminal 11 to which an input or wait signal is input, a selector 31, and a decoder 32. The bus cycle end determining means 3 is provided with an end condition selecting means 3 which determines which of the output condition of the first bus cycle end determining means 2 and the output condition of the second bus cycle end determining means 2 is to be used based on specifications from the two input terminals.

The microprocessor control unit 6 outputs clock, address, status, strobe, end condition status, and ready signals, and the present invention deals with the end condition status signal.

In this embodiment, the status information input manually from the termination condition status input terminal 10 is 3 bits and has the meanings shown in the table.

FIGS. 2(a) and 2(b) are diagrams showing the operation timing of the embodiment of the present invention. The microprocessor outputs an address and status information such as read or write at timing T1, and outputs a strobe signal indicating that the address and status information have been determined at timing T2. Further, at timing T3, the termination status is latched from the termination condition status input terminal 10 shown in FIG. This latched status information is input to the termination condition selection means 3, and it is determined which of the first and second bus cycle termination determination means 1 and 2 is to be used.

FIG. 2(a) shows an example in which the termination condition determining means 1 is used, in which 000 is received as the termination condition status at T3 and the bus cycle is terminated at T4. If the termination condition status is 001, the bus cycle is terminated at T5. FIG. 2(B) is an example when the termination condition determination means 2 is used, and in T3, the termination condition status is 1.
11 and waits for the ready signal to become active to complete the bus cycle.

In the embodiment of the present invention described above, a detailed explanation of the circuit of each bus cycle end determination means is omitted, but this can be easily constructed using a well-known circuit system.

〔Effect of the invention〕

As explained above, according to the present invention, the bus cycle termination condition is determined based on the specified number of cycles from the input terminal,
The pass cycle end condition is activated by the ready signal input from the input terminal, and when the microprocessor starts bus access by specifying either of these two bus cycle end conditions from the input terminal, the For items such as memory and input/output interfaces where the number of cycles required for bus access can be determined in advance, using a bus cycle termination condition based on the number of cycles has the effect of allowing path access to be performed with fewer external circuits. .

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the structure of an embodiment of the present invention. FIGS. 2(a) and 2(b) are diagrams showing the operation timing of the embodiment of the present invention. 1. First bus cycle end determination means, 2. Second bus cycle end determination means, 3. Termination condition selection means, 4. Bus access control circuit, 5. Latch, 6... Microprocessor control unit, lo... End condition status manual terminal, 11... Ready signal input terminal, l2... First bus cycle end condition signal, l3
. . . second bus cycle end condition signal, 14 . . . selected bus cycle end condition signal, 31 . . . selector, 32 . . . decoder.

Claims (1)

[Scope of Claims] 1. A first bus cycle end determination means that generates the end condition of a bus cycle according to the number of cycles specified by an external terminal to which the end condition status is input, and a ready signal or wait signal is input. a second bus cycle end determining means for generating a bus cycle end condition according to a signal from an external terminal; an output condition of the first bus cycle end determining means; and an output condition of the second bus cycle end determining means. 2. A microprocessor bus access device, comprising: termination condition selection means for determining which one to use based on designation from the two external terminals.