JPS642971B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a data processing device suitable as a microcomputer system. In recent years, microprocessors have been applied to various industrial products. On the other hand, a microcomputer with a microprocessor as its central functional element
The system is commercially available at a relatively low price and is becoming established as a hobby. When attempting to add an I/O (input/output) interface to such a microcomputer system, it is often connected to the main body on a board-by-board basis. Such boards usually consist of I/O hardware and software to drive it, and the software is ROM.
It is mounted on the I/O board or main body in the form of The memory space allocated to these software is usually small, and is desirably small from the standpoint of overall system design. This means that even if the services requested of the processor are executed by software that can be stored individually in a small memory area, when the number of types of services increases, the address This can also be said from the fact that it is impossible to realize in space. By the way, there are two methods for processing the above-mentioned service programs by a processor using an interrupt, such as a so-called software polling method in which the presence or absence of a service request is finally checked, a hardware interrupt method, and the like. However, in this case, since the processor needs to select the service program, there is a problem that both the hardware and the software become complicated. The present invention has been made in view of the above circumstances, and is based on the premise that service (requests) requests do not come at intervals shorter than the time required for one service, and that they occupy the same address space for processors. A data processing device that can realize switching between programs with relatively simple hardware by associating programs on several memory banks (memory areas) and separating the means for switching between these programs and the processor side. This is what we are trying to provide. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic configuration diagram of the bank switching unit of the same embodiment, where 1 is a processor, 2 is a master bank, 3 ₁ , 3 ₂ , . . . are slave banks, 4 is a bank switching device, and 5 is a memory space. It shows. The processor 1 is connected to the master bank 2, slave banks 3 ₁ , 3 ₂ , . . . through address lines A ₁ to An and data lines D ₁ to Dm, and the bank switching device 4 is connected to bank selection lines BEl, BE1, BE2, . ..., master bank 2, slave bank 3 ₁ , 3 ₂ , ...
and processor 1 is connected to memory selection line ME.
(memory enable) and is connected to the bank switching device 4 through address lines A ₁ to An. The bank switching device 4 receives external request strobe signals S, request designation signals R ₁ to R _k , etc.
The configuration is such that one of the bank selection lines BEl, BE1, BE2, . . . is selected. FIG. 2 shows programs in a master bank and one slave bank, and JMP (jump) is used as the program instruction name, which is a relative or absolute unconditional branch instruction. Here, A, B, and START are addresses, A is the entrance of the slave bank common to all slave banks, and B is the exit. START is the actual start address of each slave bank's operation. The operation of this system is as follows. First, when processor 1 has finished servicing a certain request, it executes an infinite loop with the last "JMP B" instruction of the corresponding slave bank. At this time, when a signal requesting the execution of the service appears on the request strop S, the bank switching device 4 first selects the master bank 2 for a time sufficient to execute the "JMP A" command. If addresses A and B are selected to differ only in one specified unit of the processor's program counter (one unit that captures the operation code from the data line) in the lower bit (last unit of data), bank switching is possible. Even if it is performed asynchronously, switching from the slave bank to the master bank is performed stably. After executing the "JMP A" command on the master bank 2, the processor 1 immediately enters an infinite loop of "JMP A", but the bank switching device 4 now responds to the contents of the request designation lines _R1 to _Rk . Select a slave bank and switch to the slave bank that performs the desired processing. For example, in Figure 2,
For example, when executing an infinite loop at address B with slave bank 3 ₁ , master bank 2 is
When is selected, the instruction at address B in master bank 2 is executed, and with this instruction an infinite loop at address A in master bank 2 is entered. Similarly, when a desired slave bank is selected by an external signal while executing this loop, the instruction at address A of this selected slave bank is executed, and the actual work of the slave bank is executed. It is something that In Figure 1, a bank selection line is used to switch banks, but if the master bank and slave bank are located on memories with consecutive addresses, etc., the memory line can be used instead of the bank selection line. The bank switching device may generate the high-order bits. In this embodiment, a portion of the memory space of a microcomputer system is shared among several memory banks, and depending on an external request and switching instruction information, one of the service programs on each memory bank can be When trying to select a memory bank, divide the memory bank into one master bank and other slave banks,
A JUMP (BRANCH) instruction for the processor on the bank at the position corresponding to the same address, a JUMP (BRANCH) instruction for itself on the slave bank, and a JUMP of the same format for another address on the master bank.
This is achieved by placing the (BRANCH) instruction and by setting the start point of the program on each slave bank to the same address for the processor. FIG. 3 shows one of the more specific embodiments. The bank is 256 bytes long and occupies microprocessor addresses "00" to "FF" (hex). It is assumed that four banks consisting of one master and three slaves are used to respond to three types of service requests. When the request strobe is input with the request specification, that is, when the signal becomes high level, the request specification (in this case “01”,
"10" and "11") are latched by the latch 10, but at the same time, the monomulti 11 is operated by the request strobe, and the buffers 12 ₁ and 12 ₂ are in a high impedance state, so the pull-down low resistance 13 ₁ and 13 ₂ , addresses A9 and A10 temporarily become "00" and master bank 2 is selected. In this case, the output pulse width of the monomulti 11 is
It is assumed that the execution time is longer than the execution time of the “JMP A” instruction.
When the output pulse of monomulti 11 ends, buffer 1
2 ₁ and 12 ₂ are turned on, and the output of latch 10 is transmitted to A9 and A10, so that control is transferred to the bank that has the service program according to the request specification. Fig. 4 shows that it is only necessary that one instruction is actually stored in the master bank, that is, "JMP A".
Note that all you have to do is give the command,
This is an example of using special hardware for the master bank. In this example, the bank is also 256 bytes long and occupies microprocessor addresses "00" to "FF" (hex). Further, it is assumed that the JMP instruction used for switching between the master bank and the slave bank uses absolute address specification, and that both the processor address and the data bus are 8 bits. If the slave-to-master bank switching address for processor 1 is A1 (corresponding to B above), and the master-to-slave bank switching address is A2 (corresponding to A above), then the master bank is determined by the JMP instruction code as shown in the figure. This can be realized by hardware that alternately sends the JMP command code and the address A2 from the generator 21 ₁ and the A2 address code generator 21 ₂ to the data bus in accordance with the memory read by the processor 1. In addition, R- in the figure
The operation of the S flip-flop 22 is as shown in the following table. Since the terminal of this flip-flop is connected to the D terminal, the flip-flop output Q is inverted every time the clock CLK is input.

[Table] Also, in FIG. 4, when the output of the monomulti 11 is at a high level, the AND gates 23 ₁ and 23 ₂ are opened alternately according to the value of the output Q of the flip-flop 22, and the outputs of the devices 21 ₁ and 21 ₂ are Batsuhua 24 ₁ ,
24 ₂ to processor 1 alternately.
Further, when the output of the monomulti 11 is at a low level, the buffer 26 ₁ or 26 ₂ is enabled via the AND gates 25 ₁ and 25 ₂ . this battle 2
6 ₁ is used on the data writing side, and buffer 26 ₂ is used on the data fetching side. As explained above, according to the present invention, since the processor is separated from the bank (memory area) switching system, the amount of hardware used for switching between several service processing programs selected by external signals can be reduced. I can do it.
Furthermore, since there is no need to perform a program to check the type of request, the program can be simplified accordingly. Furthermore, since each slave bank is logically closed, it is possible to easily increase the number of service programs by providing many types of external request signals. Further, in the present invention, a master bank 2 is provided, and a plurality of slave banks 3 ₁ , 3 ₂ , . . . are provided,
Of these, the slave bank at the pre-selection stage continues to point to the address at the end of the job.
Next, master bank 2 is selected, jumps from the address at the end of the job to the entry point common to each bank, and then
It jumps to the entry point of the slave bank selected by R ₁ to R _K , and then jumps to the address where the actual work is performed. Therefore, the request specification line
Since it automatically jumps to the address where the actual work is to be performed in response to the signals R ₁ to R _K , rapid processing can be performed.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing one embodiment of the present invention, FIG. 2 is a program layout diagram for explaining the operation of the same configuration, and FIG. 3 is a more detailed concrete diagram of the embodiment of FIG. 1. FIG. 4 is a diagram showing a modification of the same configuration. 1...Processor, 2...Master bank, 3
₁ , 3 ₂ ... slave bank, 4 ... bank switching device, 21 ₁ ... jump instruction code generator, 21 ₂ ... address code generator.

Claims (1)

[Claims] 1 a processor; a master bank and a plurality of slave banks whose addresses are selected by the processor and which occupy the same address space for the processor; and bank switching means for sequentially selecting one of the following, wherein the master bank selects the job of the slave bank selected by the external request signal from the job end address according to the program of the slave bank selected in the previous step. The master bank and the plurality of slave banks each have the same address as an entrance from the other and an address as the exit from the other, and the bank switching means In response to a work processing request from the outside, the master bank and the slave bank that will perform the work from now on are selected in sequence, and the master bank switches to the entrance address of the slave bank that will perform the work from now on, and the selected slave bank A data processing device characterized in that a program is executed and a standby is performed according to an exit address of the slave bank.