JPS6359167B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a reset circuit for resetting input/output circuits while the central processing circuit of a microcomputer is in operation.

Conventionally, reset circuits for microcomputers have been designed to ensure that all circuits are reset when the power is turned on, because the types of control signals used in microcomputers and the number of LSI terminals that make up each circuit are limited. or configured to manually reset all circuits.
Therefore, if it becomes necessary to reset the input/output circuit while the central processing circuit is in operation, the central processing circuit is also reset at the same time.

Also, depending on the LSI used for the input/output circuit,
Some LSIs share the reset terminal with other control signal terminals, and such LSIs can be reset under certain conditions, for example, if a reset signal is applied when no control signal is applied to the other control signal input terminals. It's summery. Therefore, it is impossible to reset the central processing circuit when it is in operation, ie, when it is sending control signals to the memory circuit, input/output circuit, etc.

The present invention aims to provide a reset circuit that can reset the input/output circuit while the central processing circuit is in operation.

The present invention will be explained below based on an illustrated embodiment. Note that explanations and illustrations of parts that are the same as those of a general microcomputer, such as a storage device, will be omitted, and only those related to the reset circuit will be explained.

In FIG. 1, reference numeral 2 denotes a central processing circuit, and this central processing circuit 2 has an interrupt signal input terminal 4. As shown in FIG.
An interrupt signal generation circuit 6 that can manually generate an interrupt signal is connected to the interrupt signal input terminal 4, and this interrupt signal causes the central processing circuit 2 to write data to a storage circuit at a specific address. Programmed to be a write cycle.

Address decoder 1 is on address bus line 8.
0 is connected, and the address decoder 10 is configured such that the address decoder output signal 12 becomes low level only when a specific address signal is generated on the address bus line 8 by an interrupt signal.

The output terminal of the address decoder 10 is connected to one input terminal of an inverted input AND circuit 16 in the reset signal generation circuit 14, and the other input terminal of the inverted input AND circuit 16 is connected to the central processing circuit 2.
Connected to MREQ terminal 18.

The terminal 18 receives a signal 20 indicating that a valid address is being output to the address bus line 8 when writing to or reading from the memory circuit.
The signal 20 goes low only when a valid address is being sent at the terminal to which the address is sent.

The output terminal of the inverting input AND circuit 16 is a NAND
It is connected to one input terminal of the circuit 22, to a CL (clear) terminal 25 of a hexadecimal preset counter 24, and to a D input terminal 27 of a D-type flip-flop 26.

The output terminal of the NAND circuit 22 is connected to an LD (load) terminal 28 of a hexadecimal preset counter 24. Data input terminals A, B, C, and D of the hexadecimal preset counter 24 are connected to the switch 3, respectively.
0a, 30b, 30c, and 30d, and a power terminal (not shown) via a resistor 32.
It is connected to the. This hexadecimal preset counter 24 is connected to switches 30a, 30b, 30c, 30d.
By opening and closing , the number of counts from the start of counting until the carry output is sent from the CY (carry) terminal 34 can be arbitrarily selected.

Output terminal 36 of D-type flip-flop 26
is connected to the other input terminal of the NAND circuit 22 and also to the EP (enable) terminal 40 of the hexadecimal preset counter 24 via the NOT circuit 38. Further, the Q output terminal 42 is connected to the terminal 46 of the central processing circuit 2 via the NOT circuit 44.
It is connected to the.

When the low level signal 48 is supplied to the terminal 46, the central processing circuit 2 outputs an address signal,
The MREQ signal 20 and a signal 50 to be described later are expanded.

Clock pulse input terminal 5 of central processing circuit 2
2. Clock pulse input terminal 54 of D-type flip-flop 26 and hexadecimal preset counter 24;
56 is connected to a clock pulse generation circuit 57.

Further, 58 is a reset pulse generation circuit that generates a low level reset pulse 60 when the power is turned on.
It is connected to the terminal 62 of the central processing circuit 2 and also to one input terminal of the NOR circuit 66 via the NOT circuit 64 . NOR circuit 6
The other input terminal of 6 is connected to the CY (carry) terminal 34, and the output terminal is connected to the D-type flip-flop 26.
is connected to the CD (clear data) terminal 68 of.

Furthermore, the reset pulse generation circuit 58 is connected to one input terminal of the NOR circuit 70 with an inverted input.
The other input terminal of the NOR circuit 70 with inverted input is
It is connected to the output terminal of the NAND circuit 72.
The output terminal of the inverting input NOR circuit 70 is connected to the terminals 76 of the input/output circuits 74a to 74n.

One input terminal of the NAND circuit 72 is an inverted input
It is connected to the output terminal of the AND circuit 16, and the other input terminal of the NAND circuit 72 is connected to the (write) terminal 80 of the central processing circuit 2 via the NOT circuit 78.

The (write) terminal 80 is also connected to a memory circuit (not shown), and the signal 50 sent from this (write) terminal is the signal 2 during the memory write cycle T _WR as shown in FIG.
0, clock pulses T1, T2, T3 and the address signal 82 sent to the address bus line 8.

Reset signal generation circuit 1 configured in this way
The microcomputer with 4 operates as follows.

Now, when a power switch (not shown) is turned on, a reset pulse 60 is sent out from the reset pulse generating circuit 58. The reset pulse 60 is
It is sent to the RESET terminal 62, resets the central processing circuit 2, passes through the NOT circuit 64 and the NOR circuit 66, resets the D-type flip-flop 26, sets the Q output terminal 42 to low level, and resets the Q output terminal 36.
is set to a high level. At the same time reset pulse 60
is sent to the terminal 76 through the NOR circuit 70 with an inverted input, and resets the input/output circuits 74a to 74n.

In this state, since the Q output terminal 42 is at a low level, the terminal 46 is at a high level and the central processing circuit 2 can operate.

Next, in the program, the input/output circuits 74a to 74
n, or input/output circuit 74a.
74n malfunctions and requires reset, the interrupt signal generation circuit 6 manually generates an interrupt signal. The interrupt signal causes the central processing circuit 2 to enter a write cycle and send a specific address signal to the address bus line 8. This address signal causes the address decoder output signal 12 of the address decoder 10 to go low. Now, as shown in FIG. 3, if decoder output signal 12 becomes low level in synchronization with the rising edge of clock pulse T1 during memory write cycle _TWR , signal 20 also becomes low level with the falling edge of clock pulse T1. Become.

When the signal 20 and the decoder output signal 12 go low, the output of the inverting input AND circuit 16 goes high, and the D input terminal 27 of the D flip-flop 26 goes high. At this time, the output terminal 36 of the D-type flip-flop 26 is at a high level, so the output of the NAND circuit 22, that is, the LD (load) terminal 28 is at a low level, and the hexadecimal preset counter 24 switches 30a, 30.
The preset values set by b, 30c, and 30d, for example 1101, are read.

Next, due to the rise of the clock pulse T2, the Q output terminal 42 of the D-type flip-flop 26 goes to a high level, and the output terminal 36 goes to a low level.
A low level signal 48 is sent to the terminal 46, and the EP (enable) terminal 40 becomes high level, so that the hexadecimal preset counter 24 starts counting from the next clock pulse T _W1 .

When the signal 48 is supplied, the central processing circuit 2 sends out the signal 50 at the falling edge of the clock pulse T2, then stops the operation, and starts processing based on the preset value of the hexadecimal preset counter 24 from the rising edge of the next clock pulse _W1 . The signal 20, the address decode signal 12, and the signal 50 are stretched by the number of clock pulses determined by the clock pulse.

The low level signal 50 is supplied to one input terminal of the NAND circuit 72 via a NOT circuit 78. The other input terminal of this NAND circuit 72 is
Address decoder signal 12 and signal 20
The output of the NAND circuit 72 becomes low level at the same time as the signal 50 is supplied. Therefore, the input/output circuit 74a
Low level terminals 76 to 74n
RESET signal 84 is supplied, input/output circuit 74a
74n are reset.

Since the preset value of the hexadecimal preset counter 24 is now 1101, the CY (carry) terminal 34 becomes high level with the rise of the third clock pulse T _W3 after counting starts, and the NOR circuit 66
The D-type flip-flop 26 is reset via the D-type flip-flop 26.

When the D-type flip-flop 26 is reset, the Q output terminal 42 is at a low level and the output terminal 36 is at a low level.
becomes high level, the signal 48 becomes high level, the EP (enable) terminal 40 becomes low level, and the CY (carry) terminal 34 becomes low level.

When the signal 48 becomes high level, the central processing circuit 2 starts calculation again, and with the fall of the final clock pulse T3 of the memory write cycle _TWR , the signals 20 and 50 become high level, and the signal 84 becomes high level. .

As described above, according to the present invention, when the central processing circuit 2 is in operation, the input/output circuit 74a
74n can be reset. moreover
Depending on the preset value of the hexadecimal preset counter 24, a signal 8 with a maximum clock pulse length of 16
4 can be obtained, so even if an LSI or the like that takes time to reset is used in the input/output circuits 74a to 74n, the preset value of the preset counter can be selected according to the input/output circuits 74a to 74n. Reset can be performed reliably.

In the above embodiment, the interrupt signal is generated manually, but the input/output circuits 74a to 7
A circuit for detecting an abnormality in the 4n may be provided, and an interrupt signal may be automatically generated by the output of this circuit.

[Brief explanation of drawings]

Figure 1 is a circuit diagram of a microcomputer using a reset circuit according to the present invention, Figure 2 is a timing diagram of each signal during a memory write cycle of the microcomputer, and Figure 3 is a diagram of the timing diagram of each signal when an interrupt signal is generated. FIG. 3 is a timing diagram of each signal during a memory write cycle. 2...Central processing circuit, 6...Interrupt signal generation circuit (reset request signal generation circuit), 8...Address bus line, 10...Address decoder, 16...
Inverted input AND circuit (command signal generation circuit), 18...
...terminal (memory request terminal), 22...
...NAND circuit, wait signal stop circuit, 24...
...Preset counter, wait signal stop circuit,
26...Flip-flop, wait signal supply circuit, 44...NOT circuit, wait signal supply circuit,
74a to 74n...input/output circuits.

Claims (1)

[Claims] 1 It is programmed to send a specific address signal to the address bus line when a reset request signal is supplied, as well as a memory request signal and a write signal, and is programmed to send out a memory request signal and a write signal at that time while a wait signal is being supplied. a central processing circuit connected to the address bus line and configured to continue sending out each signal, and to stop sending out each signal being sent at that time when the supply of the wait signal is stopped; an address decoder that sends out a decoded signal when a specific address signal is supplied; and a command signal generation circuit that is configured to generate a command signal during a period in which the decoded signal and the memory request signal are supplied. a reset signal generation circuit configured to generate a reset signal over a period in which the command signal and the write signal are supplied; and a control signal connected to the central processing circuit and receiving the control signal from the central processing circuit. an input/output circuit configured to send and receive data to and from the central processing circuit in accordance with the above, and to be reset when the reset signal is supplied to a reset terminal for a predetermined period of time;
a wait signal supply circuit that starts supplying the wait signal to the central processing circuit upon receiving the command signal; A stop circuit for stopping the supply of the wait signal, and a reset request signal generation circuit configured to generate the reset request signal in response to a switch operation or in response to detection of runaway of the input/output circuit. reset circuit.