SU1532899A1 - System for program control of automatic electric circuits - Google Patents

Abstract

The invention relates to automation and computing and can be used in microprocessor-based process control systems for software implementation of control algorithms for electrical automation. The purpose of the invention is to expand the scope. The system contains a software block, a clock generator, a system controller 3, an address buffer, a memory address decoder, a permanent memory, a random access memory, a bus memory driver, an address input device decoder, a register, a bus input / output drivers, a bus shaper input, bus shapers low address and high address, bus shapers record and control, decoder, multiplexer, trigger, first-sixth OR elements, first-third elements And, one-shot, delay elements, ready input, in the reset input of the read / write, idle, and outputs the control, first - fourth group of information inputs, a first and a second group of information outputs, output prohibition request input. New elements of the system are the decoder, multiplexer, the fifth element OR, the sixth element OR. The introduction of new elements allows to expand the scope of the system by introducing the discipline of accelerated transition along critical arcs of the control graph. 2 ill., 1 tab.

Description

The invention relates to automation and computing and can be used in microprocessor-based process control systems for software implementation of control algorithms for electrical automation.

The purpose of the invention is to expand the field of application by providing diagnostic functions.

The essence of the invention is the introduction of the discipline of accelerated transition along critical arcs of the control graph.

The essence of the proposed new discipline is as follows: to permanently fix the current internal state of the control algorithm on the register at the end of the input processing cycle

ten

signals of the state of elektroavtomatika; in decoding the code of the vertices and weights of the arcs of the control graph of the decoder, initiating an accelerated transition; in the output of control signals to the register in the process of direct access to the memory according to the signal of the decoder, taking into account the current internal state fixed in the register,

Fa FIG. 1 is a functional diagram of a system for programmed control of electroautomatic; in fig. 2 - time diagram of her work.

The system for electro-automatic program control contains a program block having first and second clock inputs 1.1 and 1.2, ready input 1.3, input 1.4, you have synchronization progress 1.5, address outputs

1.6, data outputs / inputs 1.7, control outputs 1.8 containing the output

1.8.1 admissions, yield 1 3.2 Confirms 5328994

the left 30 and second 3 elements of the tat, ep / kk; readiness input 32, reset input 33 read / write input 34; control output; wait output 36; the first group of information inputs 37, containing the subgroup 37.1; the second group of information inputs 38; the third group of information inputs 39; the fourth group of information inputs 40; the first group of information outputs 41, the second group of information outputs 42; exit 43 of the ban; input 44 request.

The purpose of the main elements of the system.

Program block 1 is designed to execute a program, i.e. a sequence of commands used to implement the control algorithm; to control the bus microprocessor system. Software unit 1 senses external clock signals as well as control signals and generates

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capture day, entry 1.9 capture; So-25 signals of address 1.6, data 1.7 and a wholesale generator 2, having synchronization input 2, first s second clock inputs 2.2 and 2.3, readiness output 2.4, reset output 2.5 and output of system resetting 2.6; system controller 3 having data outputs / inputs 3.1, which are the system data bus, control outputs 3.2, which are the system control bus and containing, in turn, memory read output 3.2.1, memory write output 3.2.2, output 3 ; 2.3 input; output 3.2.4 output; buffer 4 addresses, having outputs 4.1, which are bus addresses of the system; a memory address decoder 5 having a output of 5.1 connecting a block of permanent memory and an output of 5.2 connecting a RAM block; block 6 of permanent memory, block 7 of operational package, bus driver 8 of memory, decoder 9 addresses of input / output devices having first output 9.1, second output 9.2 and group of outputs S.3; register 10 bus driver 11 input / output; bus driver 12 input; bus driver 13 junior address; bus driver 14 high address; bus 15 write driver, bus driver 16 control

laziness; decoder 17; multiplexer 8, trigger 19, the first - the sixth elements OR 20-25; the first - the third elements And 26-28; Simulator 29, per0

Directions 1.8, 36. Software block 1 can be implemented, for example, on a standard integrated circuit KR580IK80A (foreign analogue 8080A).

The clock generator 2 is designed to generate the synchronization signals of the software block 1, the system controller 3, and the system reset and readiness signals.

The system controller 3 is designed to form a control bus 3.2 of the system and to organize bidirectional data transmission over the data bus 3.1,

The address buffer A is designed to form the 4.1 bus address and turn it off when the 1.8.2 signal is activated by changing its outputs / inputs to a high-impedance state.

Decoder 5 of the memory address is designed to decipher the address information from the output of the OR element 20 by the address information on the address bus 4.1 to be connected to the chip selector inputs, either the permanent memory unit 6 (output 5.1), or the operational memory unit 7 (output 5.2), I

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Block 6 of the permanent memory is intended for storing programs and data that are not destroyed when the power is turned off, including the dispatcher program for loading the main memory and the program for controlling electroautomatics, and

also to issue this information in the memory reading mode (direct memory access).

The RAM block, 7, is intended for recording and storing programs and data only during system operation. When writing, the enable and write signals are activated, and when reading, only the enable signal is activated. Information from the RAM block 7 is provided in a read or direct memory access mode. In the capture mode (direct memory access), information can also be recorded in the RAM block 7.

The bus driver 8 of memory is designed to increase the load capacity of data bus 3.1 and to ensure the connection to it of blocks of constant 6 and memory 7 of RAM.

When reading information from block 6 constant or block 7 operational. The memory activates both the enable inputs of the bus driver 8 of the memory and the information is transmitted to the data bus 3.1. When writing to the RAM block 7, only its first enabling input is activated, and information from the data bus 3.1 is transmitted to the data inputs of the RAM block 7.

Decoder 9 addresses of input / output devices are designed to decipher by the enable signal from the output of the OR 22 element of address information for connecting the corresponding I / O bus 11 from the corresponding bit of output group 9.3 to write information to the register 10 through the OR 25 element to output 9.2 control of the register, as well as to connect the bus driver 12 input to the output 9.-1

Register 10 is intended for recording, storing and issuing information of a generalized electroautomatic control output signal generated by the PLA procedure and outputted during software output when the output 9.1 of the I / O device address decoder is excited, or during direct memory access (capture) when activated element outlet I 27.

The input / output bus driver 11 is designed to increase the load capacity of the data bus.

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3.1, for entering information from inputs 37.1, 37 (with both enable inputs enabled), for outputting information to outputs 41 (with only the first allowing input activated). In all other cases, the inputs / outputs of the bus driver 11 are in a high impedance state and are not

JQ affects data bus 3.1.

Bus input driver 12 is designed to enter information from inputs 38 when activating output 9.1 of the decoder device addresses 9

5 I / O 9 and output 3.2.3 control bus 3.2. Otherwise, its outputs / inputs are in a high-impedance state.

The junior address bus driver 13 is designed to provide information on the lower bits of the required memory cell in the process of capturing the bus for the lower bits of the address 4.1, which in this case is previously

5 is set to inputs 38j. Otherwise, its outputs / inputs are on. The motion is in a high-impedance state.

Tire shaper 14 senior

The 0 address is intended for issuing in the process of capturing for higher bits of the bus address 4.1 information about the higher bits of the required memory cell when implementing a critical transition from a critical vertex of the control graph of electroautomatics along a critical arc.

Otherwise, the outputs / inputs of the bus driver 14 of the senior address are in a high impedance state.

The write bus driver 15 is designed to output information from the inputs 39 to the data bus 3.1 in the capture process for writing it to the desired cell of the RAM 7. In this case, both inputs of the driver of the driver 15 are activated. Otherwise, the outputs / inputs of the bus 0 Record former 15 are in a high-impedance state.

The control bus driver 16 is designed to generate control signals in the capture: read 3.2.1 or write 3.2.2 when activating both control inputs of the output of the OR 23. In other cases, the outputs of the bus driver 16 are 5

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DTS is in a high impedance state and does not affect control bus 3.2.

Decoder 17 is designed to decipher the pulse at the output 3.3 of the clock generator 2 information on the second group of outputs of the register 10 and information on inputs 33 to identify the critical arc from the critical vertex of the electroautomatic control graph and initiate internal memory (direct memory access), multiplexer 18 it is intended to connect to the information inputs of a clay shaper 4 high addresses or information inputs 40 In normal operation, or information from the second group of outputs of register 10 to p in the mode of accelerated transition along the critical arcs of the control graph, JieHrifl electroautomatic, and its address input in this mode is activated by the output of the decoder 17.

Trigger 19 predn. .. (to generate a capture signal to the corresponding input 1.9 of microprocessor 1 when activating it, the controller is set) by the output of the element OR 24 either when it is captured at input 44 or when it is captured internally (the mode of the accelerated transition through the critical arcs of the graph Control), the flip-flop 19 is reset by a pulse from the output of the delay element 30.

Input 32 is for receiving an external readiness signal, input 33 is for receiving an external reset signal for zeroing the program counter of microprocessor 1, output 36 for producing a wait signal that is activated if input 32 of readiness is not activated.

The first group of information inputs 37 is intended for receiving external information. The group of inputs 37.1 is intended for receiving information from the second group of information outputs of the register SO, i.e., a format for the code of the current vertex of the control.

The second group of information inputs 38 is intended for receiving information on the state of electrical automation (input signal), or on lower addresses of memory cells (when charging, for example, RAM block 7 in direct memory access mode) ,

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Third group of information; The n ix nxj-dov 39 is intended for receiving data for writing it to the RAM in the direct memory access mode, for example, during initial loading.

The fourth group of information inputs 40 is designed to receive information about the upper addresses of the memory cells (also during initial loading, for example, of the RAM block 7 in the direct memory access mode).

The first group of information outputs 41 is intended for issuing information to external equipment (for example, diagnostic or control signals for recording information into the RAM block 7 from external storage media under the control of a monitor recorded in the permanent memory block 6).

The second group of information outputs 42 is designed to issue CHI control electro-automatics - when implementing the control graph both programmatically and accelerated.

The output 43 is intended to prohibit the formation of a request for direct memory access by external signals if the decoder 17 output is energized. The active output 43 signals that the system is in an accelerated transition mode and gives an alarm to the operator

Input 44 is designed to receive a request for direct memory access, i.e. synchronization pulse of external capture, for example, when loading RAM.

Input 34 is designed to receive a read / write signal for direct memory access. When recording from input 44, external devices reduce the active level of the signal. In all other cases, this input is activated.

Output 35 is intended to inform external devices about the end of the capture cycle and the possibility of starting a new cycle (if there is no ban on output 43),

The system for programmed control of electro-automatics works as follows.

Normal mode of operation

In this mode, the system works similarly to the prototype. After powering up the clock generator 2 on

It begins to form two non-overlapping clock sequences of pulses, which are from its outputs 2 and 2.3. supplied to inputs 1.1 and 1.2 of software block 1. Software block 1 begins to generate output signals: 1) after a signal has been sent Reset to its input 1.4, the external signal being preloaded Reset is input to the system, gated in clock generator 2 and from its output 3.5 to the corresponding input 1.4 of program block 1; 2) after establishing the level of logical 1 at the input 32 of the system, and from the output 2.4 of the clock generator 2, the gated readiness signal is fed to the input 1.3 of the program block 1. If the signal 32 has a logical signal O, then the output 36 sets the signal logical 1, indicating that program block 1 is in the idle state.

Software unit 1 outputs the status word to the data outputs / inputs 1.7 on the output 1.5 clock signal, which is fed to input 2.1 of the clock generator 2, from output 2.6 of which the system strobe goes to the synchronization input of the system controller 3. By the system gate to the system controller 3 records the state word from the outputs / inputs of data 1.7 of software block 1. According to the status word and information at the outputs 1.8 of the software block I, the system controller 3 forms the system control bus 3.2. The system controller 3 also forms the system data bus 3.1 and provides bidirectional data transmission over it.

The address bus 4.1 of the system by address signals 1.6 of program block 1 forms a buffer 4 addresses.

After forming the address busses 4.1, data 3, and control 3.2, program block 1 starts reading and executing the program recorded in persistent memory block 6, starting at zero address (after reset, the program counter of program block 1 is reset). The decoder 5 of the memory address activates its output 5.1, since the address of the block 6 of the permanent memory is set on the system 4.1 address bus (zero after reset), and

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20

25

right

532899Ü

control bus 3.2 has an active read memory signal 3.2.1, and therefore the OR element 20 activates the enable input of the memory address decoder 5. Active level at the exit

A 5.1 memory address decoder 5 connects a permanent memory unit 8 to the first resolution input through an OR 21 element. On the second permission input, the bus memory driver 8 is configured to transfer information from the outputs of the constant memory unit 6 to the system data bus 3.1, how output 1.8.1 of control output 1.8 of program block 1 is activated. Commands and data are read into program block 1 according to the address provided on the 4.1 address bus. For example, a boot program from external storage devices in the RAM unit 7 can be executed. To write the information to the RAM block 7, control bus output 3.2.2 is activated.

3.2 systems and, accordingly, the output 5.2 of the memory address decoder 5, since the address of the operational memory block 7 is set on the address bus 4.1 in this case.

The bus driver 8 of the memory with the inactive level at the output 1.8.1 of the outputs of the control 18 of the program block 1 is transferred to the information output state on the data bus 3.1, which is recorded in the operational memory block 7 by the addresses set on the address bus 4.1. In this case, the enable input of the RAM block 7 is activated by the output 5.2 of the memory address decoder 5, the write input is activated by the output 3.2.2 of the control bus 3.2, and the first enable input of the bus driver 8 of the memory is activated by the output of the OR 21 element.

When reading information from the RAM block 7, the system works similarly, except that the output 3.2.2 of the control bus 3.2 is not activated, the output 3.2.1 of the control bus 3.2 and the output 1.8.1 of the control outputs 1.8 of the program block 1 are activated. Information from memory unit 7 via the bus driver 8 memory is read on the data bus 3.7 of the system through the system controller 3 to the outputs / inputs 1.7 of program block 1 in accordance with the addresses set on the bus

35

40

45

50

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addresses 4.1. Thus, a program with a program, in the block 6, in block 6, either permanently or in block 7 of the operational memory. This includes the electro-automatics control program, the standard algorithm of which is considered, for example, in 4. For switching to subroutines, a part of the operational memory of block 7 is used as a stack.

The system enters data from its information inputs 37 and 38 or outputs data to its information outputs 41, 42. When data is entered / output by active signal levels 3.2.3 or 3.2.4 (input or output), the output of the OR 22 element activates the decoder enable input addresses of I / O devices 9, which decrypts the address of an I / O device installed on the 4.1 bus address. Thus, including a trogram from external drives, RAM unit 7 can be entered. Also, information from the inputs 38, which characterizes the state of the electric driver, is entered through the bus driver 12, and the output 9.1 of the decoder 8 of the device I / O device address is activated. When information is output to output 42, output 9.2 of the decoder 9 addresses the I / O devices is activated, the output of the element OR 24, is activated by the leading edge of the signal on which information is set to the register 10 from the data bus 31, then set at outputs 42. This information is used to control electroautomatic.

The system also performs data input and output in capture mode.,

At the same time, the trigger pulse at input 44 (Fig. 2) passing through the OR 24 element is set to the trigger state 19, the output signal of which supplies input signal 1.9 of the program block 1 to the capture signal. The software unit 1 transfers the outputs of address 1.6 and the data outputs / inputs 1.7 to the high impedance state, forms at input 1.8.2 a capture confirmation signal that translates the OUTPUTS / INPUTS 3.1 and outputs 3.2 of the system controller 3 to the high impedance state, and this The same state of the first and second resolution inputs translates outputs 4.1 of buffer 4.

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The confirmation signal capture, -, activates the output of the And 26 element, which connects the first and second / resolution inputs to the bus drivers of the younger 13 and older 14 addresses. Therefore, the higher address addresses from the output of multiplexer 18 are supplied to the address bus 4.1, since the inputs 40 are connected to its outputs by an inactive level at the output of the decoder 17, and the lower addresses from inputs 38 to which they are fed in advance before the signal is formed at input 44. These addresses select a specific memory location. A read or write control signal is generated at input 34. The single-oscillator 29 generates a pulse that, at the outputs of the element 27 (reading) or element 28, goes through the bus driver 16 to the outputs 3.2.1 or .2 of the system control bus 3.2. In this case, the bus driver control 16 is connected via the first and second inputs of the resolution by the output of the element OR 23.

Thus, information is recorded in block 7 of RAM from information inputs 39 via a group of information outputs of bus driver 15 to data bus 3.2, and the write signal is fed to input 3.2.2 of the control bus, and in this case the voltage O is applied to input 44 In this way, programs or data can be stored in RAM memory 7 from HIGH-TIME RANGE memory devices.

When reading information in the sub-capture mode, the active level of the signal from the output of the And 27 element goes through the delay element 31 to the second input of the OR element 25. In this connection, the register 10 records information from the data bus 3.1 and enters the outputs 42. The read signal from the output bus driver 15 is supplied to output 3.2.1 of the control bus 3.2. Reading information from a constant block 6 or a memory block 7 in a capture submode is used, for example, to record information in external high-speed storage media. Moreover, the formation of a sequence of addresses to the inputs 38, 40, data to the inputs 39 of the control signal, to the input 44 to write or read information arrays is also performed using technical means of external devices using the control output 35, indicating that the next write (read) is completed words of information.

The implementation of the discipline of accelerated transition along critical arcs of the control graph,

In this mode, the system implements the PLA control electro-automatic algorithm, similar to 4 J, and the register 10 is used as the memory register of the sequential automaton, the first group of information outputs 42 of which is the actual output control signals, and the second group of information outputs which is subsequent information state, i.e. in fact, this is the vertex code of the control graph. Input signals that do not characterize the state of electroautomatics in this mode are fed to the inputs 38 and input from them via the bus driver 12, as in a normal operation mode. These input signals (input vector) are in contact with the signals of the current state (the current vertex code), which are input from inputs 37.1 - from the second group of information outputs of register 10. Then the generalized input vector is processed in accordance with algorithm 4, the generalized output vector is output to Register 10 in the output cycle, similar to that described, while activating output 9.2 of the decoder 9 addresses of input / output devices.

Subsequently, after a certain time interval, the state of inputs 38, 37.1 is polled again after a certain time interval and the cycle is repeated. Interrogation and processing of input signals from inputs 38, 37.1 can be done by a subroutine connected by the dispatcher program.

Thus, software control of electro-automatics from outputs 42 is carried out.

Suppose that after the next cycle of processing input signals from inputs 38, the code of the critical vertex was set on the second group of information outputs of register 10. If the code installed at the system inputs 38 is equal to the code of the critical arc of the graph (FIG. 2), then accelerated

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transition to a new state. Such a transition is carried out as follows: the output of the decoder 17 is activated by the pulse at the output 2.3 of the generator 2 (its two groups of information inputs simultaneously have the codes of the critical vertex and the critical arc), therefore the output 43 of the prohibition is activated, which signals an external device to prohibit request for input 44, as well as the alarm (for example, the operator).

Through the OR element 24, the trigger 19 is set to one state, the output signal of which transfers program block I on input 1.9 to the capture state in the same way as described. After the program block 1 enters the capture state, at the end of the current cycle, a capture confirmation signal is generated at the output 1.8.2 of the control output 1.8 of the program block 1.

The output element And 26 activates the first and second resolution inputs of bus drivers 13,14, which are configured to transmit information to the address bus 4.1, which is converted to high impedance. Since the output of the decoder 17 is activated, the output of the multiplexer 18 is connected to the second group of outputs of register 10, the information on which represents the code of the critical vertex. This information in the form of higher addresses goes to the higher bits of the address bus 4.1 of the system, to the lower bits of which the information about the code of the critical arc from the inputs 38 through the bus driver 13 arrives.

Thus, on the address bus 4.1 of the system, the cell address of the block 6 of the permanent (memory block 7) memory is set, in which the generalized output signal for the given case is stored (for the vertex code and the arc code).

The information is read in the same way as described: the one-shot 29 generates a pulse, since a logical 1 signal is set at the input 34 (it is always set, except when recording is captured — then the input 34 is zeroed by an external device), so this pulse passes through element 27 through the bus driver control 16 to the output 3.2.2 of the system control bus 3.2.

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The control bus driver i6 is connected to the activated output of the element OR 23.

The memory cell is read, the information from which it is set to (on the data bus 3.1. After this, through delay element 31, the output of the element OR 25 is activated and the information is recorded from the data bus 3.1 to the register 10., on the first group of outputs A2 which are transmitted electro-automatic control signals.

Consequently, acceleration occurs (within one capture cycle) of generating control signals in a critical situation. Further on, the output of the delay element is 30

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y24i

X-, X, -, X, are the signals of the state of the electro-automatics (fed to the inputs 38); Z ,, Z ,,, Z4 - control output signals (received at output 42); Y, Y, - vertex codes that are set by software (code 00 is first set) are written to register 10 in the second

group of its outputs (at the entrances

37.3).

Vertex 3 (Y) and Zug., - critical, i.e. transition from the top

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The impulse that flushes trigger 19, which removes the pickup signal from input 1.9 of program block 1, is being simulated.

Program block 1 continues you-. program completion: the information from register 10 is reintroduced from inputs 37.1, 38, contacts and the process proceeds similarly until the next critical situation. I

Consider an example of a specific implementation of the proposed microsystem for controlling electroautomatics on a microprocessor 580.

Assume that it is necessary to implement the following graph control electroautomatic:

i i g

3 to 4 must be made quickly.

The graph is shown in the following transition table,

where Yj (t), Y, (t) are the current states of the inputs 37.1 (vertex codes), a Ya (t + l), Y., (t + l) is the next state into which it is necessary to transfer by software, or accelerated; ZJf Zv Z, - sets of control output signals.

We obtain the following system of Boolean functions (for simplicity, we will not minimize):

7 - L 3

Y, Y, X, UUD, ,, Z, Y Y vY-iY.X ,, Z, YaY, X, X, VY, Y, X, vY, Y, X3v

Y, (t-H) Y, Y, X1VY7Y, X1VY1Y1X3X1X

YXt +) Y.Y jX Y XjVYj.Y, X, v VY XiXjX ,.

The indices of the current states of the vertex codes are not indicated.

Such a system of Boolean functions is implemented by the procedure PLA. The generalized input vector is: Y. ,, by which PLA forms a generalized output vector, Yt (t + l) Y / t + l). The generalized output vector is transferred from the battery to the register 10 by an output command (after the PLA procedure is completed, the result remains in the microprocessor's battery, and before accessing the PLA procedure, the concatenation of signals at inputs 37.1 (Y, Y,) and 38 (XEH) ., X,) input commands).

At the next transition to state 3, the first group of inputs of the decoder 17 sets the code 10 (.,) And when the second group of its inputs appears (after outputting to the register 10) the code 111 (,) the pulse 2.5 output of the clock generator 2 occurs the accelerated transition to state 4. Therefore, the code 1 1 100 (Y ZjZ-zZ,) is read from memory location 10111.

In the future, the next call to the PLA 4 procedure will occur

concatenation of signal Y

eleven

with current

input signal and, if it becomes equal to X3, a transition is made to state 1.

Thus, the algorithm of functioning of the proposed microsystem for controlling electroautomatics using the procedure PLA 4} can be represented as follows.

AVT: IN PORT 1 (input from inputs 37. b)

A 2

(shift for further concatenation) (memorization in C 00 0 YaYn OOC) (input of information from inputs 38) (concatenation, in A-00 O,)

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CALL PLA (procedure call

PLA 14)

OUT PORT 3 (pin + R, (t + l) to register 0) RET (return to the background

program)

TA3L PB (masks of conjunctive terms in accordance with 4).

And at address 101P (full address, say 00.000.010.11OOOOOOOg), the output signal code is recorded in a critical situation 00 011.1005.

Obviously, the structure of standard software is not destroyed. The PLA procedure does not change. Concatenation commands provide the implementation of a sequential automaton (ie, a transition graph) by this procedure. The only difference is in the output and input of information into (from) the register 10, which is the memory of the machine.

Claims (1)

Invention Formula An electro-automatic software control system comprising a program block, a clock generator, a system controller, an address buffer, a memory address decoder, a fixed memory block, a random memory block, a bus driver, an I / O address decoder, a register, I / O bus driver, bus input driver, bus driver Junior Address, Bus Driver, Senior Address, Bus Recording Driver, Bus Control Driver, Trigger, First - Fourth Elements OR, First - Third Elements And, the one-shot, the first and second delay elements, and the synchronization output of the program block is connected to the clock synchronization input, the output of the system strobe of which is connected to the synchronization input of the system controller, the first group of information inputs / outputs of which are connected to the group of information inputs / outputs of the software unit, the address and control of which are connected respectively to the inputs of the address buffer and the system controller, and the standby output is the system standby output, per1915 The high and low clock outputs, the ready output and the reset output of the clock generator are connected respectively to the first and second clock inputs, the readiness input and the reset input of the program block, and the readiness and reset inputs of the clock generator are the readiness and reset inputs of the System, the second group of information passes / the outputs of the system controller is the bus of the data system and is connected to the inputs / outputs of the bus memory controller, register inputs, inputs / outputs of the bus I / O driver, inputs / output bus input driver and I / O bus records driver, the control outputs of the system controller are the system control bus, the first and second addresses of the address buffer enable are connected to the control output of the software block acknowledgment output, the addresses of the Address Address 9 bus are the system address bus and connected with the address inputs of the blocks of a constant and operative frame, with the information inputs of the decoder of the address of memory ixdecoder of the address of input / output devices, with the outputs of bus formers ml The first address of the memory address decoder is connected to the first input of the second element OR and the first and second inputs of the resolution of the constant frame unit, the outputs of which are connected to the L outputs of the memory unit AND connected to the inputs of the memory driver, the second the output of the memory address decoder is connected to the enable input of the or operative memory block and the second input of the second OR element, the output of which is connected to the first input is enabled by the bus memory driver, the outputs of which are connected to by the formation inputs of the operating memory block whose recording input is connected to the control bus write write, in the enable input of the bus driver, the memory is connected to the receive output of the program block, the first output of the I / O device address decoder is connected to the first input input of the bus driver, the second the resolution input of which is connected to the input of the system control bus, the output group of the decoded T-ora of the address 3289920 I / O devices connected. The first enable inputs of the bus I / O driver, the second permitting inputs of which are connected to the input of the system control bus, the first group of information outputs of the register is the second group of information outputs of the system five 0 five 0 five 0 five 0 five we, and the second group of information outputs of the register are connected to the first group of inputs of the multiplexer and the second group of inputs of the bus I / O driver, the first group of inputs of which is the first group of information inputs of the system, and the outputs are the first group of information outputs of the system, the first the output of the control driver bus is connected to the memory read of the system control bus, and the second output is connected to the write memory of the memory and to the first and second inputs of the bus write driver enable, the inputs which are the third group of information inputs of the system, the output of the trigger is connected to the capture input of the program block and the first input of the first element I, the second input of which is connected to the output of confirmation of the capture of the software block, and the output connected to the first and second inputs of the resolution of bus drivers for junior and senior addresses and with the input of the one-shot, the output of which is connected to the first inputs of the second and third elements AND, is the control output of the system and is connected to the input of the first delay element, output the first and second inputs of the first element OR are connected respectively to the memory read and write bits of the system control bus, and the output is connected to the enable input of the memory address decoder, the first and second inputs of the third OR element connected to the input and output bits of the system control bus, respectively, and the output to the enable input of the decoder for the address of input / output devices; control bodies, output of the second AND element is connected to first inputs of the bus control driver and the fourth OR gate and to the input of the second element zaderzhkis the output of the third element AND is connected to the second inputs of the bus driver control and the fourth element OR, the second input of the second and second inverse of the third elements AND are combined and are the read / write input of the system, which in order to expand the scope of the system, it introduced a decoder, a multiplexer, the fifth and sixth elements OR, and the enable input of the decoder is connected to the second clock output of the clock generator, the first group of inputs to the decoder is connected to the second group of information the register outputs, the second group of inputs of the decoder and the inputs of the bus driver of the input and the bus driver of the junior address are combined and are the second group of information Y2 (t) jY, (t) X3 Ј X, X, Ј Y t + oTY t + l) I Z3 J Zt Z, the system inputs, the descrambler output is the system inhibit output and is connected to the multiplexer address input and the first input of the fifth OR element, the output of which is connected to the trigger setup input, and the second input is the system request input, the multiplex outputs are connected to the bus inputs the former address generator, the second group of information inputs of the multiplexer is the fourth group of information inputs of the system, the first and second inputs of the sixth OR element are connected respectively to the second output th address decoder I / O devices and the output of the second delay element, the output of the sixth OR gate is connected to the synchronization input of the register.