JP2622791B2 - Elevator control information reading device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an elevator control information reading apparatus for reading detailed control information of an elevator in real time.

[0002]

2. Description of the Related Art As a conventional technique for reading operation information of an elevator, there is known a technique described in Japanese Patent Application Laid-Open No. 2-86583. This conventional technique monitors a communication line for transmitting and receiving operation information to and from a device provided in an elevator hall of each car and each floor, and displays the operation information on a hall information / notification device provided in each elevator hall, thereby displaying a waiting time for a customer. To communicate.

[0003]

In the above-mentioned prior art, since the communication line for transmitting and receiving the operation information of the elevator is monitored, the operation of the elevator is limited to an elevator at a stop floor or a car position of a registered car on the communication line. It becomes information that cannot be monitored and detailed information cannot be monitored, and the timing of monitoring is delayed from the actual operation because the amount of information is large with respect to the capacity of the communication line. There is no problem if the information is provided to humans as in the prior art, and if it is used for a guidance device.However, when the purpose is to collect data used for elevator maintenance and management, there are few types of information and abnormalities. When used in an elevator control diagnostic device or the like for operating the elevator to grasp the control state for investigating the cause when the error occurs, it is a problem that information delayed from the actual control is brought about.

An object of the present invention is to read detailed control information of an elevator in real time.

[0005]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a microprocessor for performing a control operation of an elevator, a first control information memory for storing control information used for the operation of the microprocessor, the microprocessor and the control unit. A data address bus for transmitting information between information memories; and a bus control signal line for transmitting a control signal for the data address bus. An input circuit connected via a transmission line to input the information, an access signal generation circuit connected to the input circuit, the microprocessor detecting information for accessing the control information memory and outputting an access signal; A data address bus connected to an access signal generating circuit and an input circuit when the access signal is input; It is achieved by having a second control information memory for inputting and stores the control information transmitted.

The above object is attained by the bus control signal line connected to the input circuit being a signal line for controlling reading and writing from the microprocessor to the first control information memory.

The above object is attained by the input circuit comprising a resistor connected in series to the transmission line, and a one-way buffer connected to the resistor.

[0008]

According to the above construction, when the microprocessor in the elevator control device accesses the first control information memory, the control information is directly input from the data address bus to the second control information memory and stored. Thus, detailed control information of the elevator control device can be read in real time.

In addition, since the data address bus and the bus control signal are inputted in one direction from the elevator control device via the resistor, the data address bus and the bus control signal of the elevator control device are provided in response to the failure of the fetch device. The signal can be protected.

[0010]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings.

First, the configuration of an embodiment of the present invention will be described.

FIG. 1 is a block diagram showing the overall configuration of an embodiment of the present invention.

In FIG. 1, reference numeral 1 denotes a conventional elevator control device for controlling an elevator, 2 denotes an elevator control information reading device of the present invention, 3 denotes a connector for connecting the elevator control device 1 and the elevator control information reading device 2,
4 is a bus control signal of the elevator control device 1, 5 is a data address bus of the elevator control device 1, 6 is an input circuit of the bus control signal 4 and the data address bus 5, and 7 is a control memory access of the elevator control device 1. An access signal generating circuit for generating an access signal, 8 is a control information memory for storing data on the data bus of the data address bus 5 when the access signal is generated by the access signal generating circuit 7, and 11 controls the elevator control information reading device 2. A control memory for storing a program for controlling the elevator control information reading device 2;
Reference numeral 10 denotes a work memory of the elevator control information reading device 2.

FIG. 2 is a block diagram showing a detailed circuit configuration of the embodiment of the present invention.

As shown in FIG. 1, the input circuit 6 includes an input signal generator 6, an access signal generator 7, and a control information memory 8. The input circuit 6 includes a protection resistor 61 and a one-way buffer 62. Is constituted by a decoder circuit.

FIG. 3 is an explanatory diagram showing an address map of the elevator control device 1 shown in FIG. As shown in the figure, a chip select signal is generated from the address AD1000, which is a control information memory area of the address map of the elevator control device 1, to the control information memory 8 at the time of accessing AD17FF. A circuit using a dual-port RAM capable of bidirectional access as the control information memory 8 is shown.

The operation of one embodiment of the present invention will be described below.

The elevator control device 1 is constituted by an address map shown in FIG. 3, and the control programs stored in the control memory area from AD0000 to AD0FFF are provided for the car / hall call, the car position and the elevator tower. Control information necessary for control, such as the operating state of the device, is transmitted from the AD1000 to the AD17FF.
The control of the elevator is performed while always reading and writing the control information memory area.

The elevator information reading device 2 receives control information from the data address bus 5 of the elevator control device 1 via the connection connector 3, inputs an E signal as a basic clock and a VMA signal indicating external access of the MPU,
The access signal generation circuit 7 generates a chip select signal CSL of the control information memory 8 when the control information memory area is accessed, and stores the data on the data bus in the control information memory 8 at the timing of the E signal. . Also, various input signals are input via the protection resistor 61 and the one-way buffer 62, so that the input side of the one-way buffer 62 can be controlled by the protection resistor 61 even when a hardware failure such as a power supply or ground short circuit occurs. Various input signals of the control device 1 can be protected.

In this embodiment, when the control information memory area of the elevator control device 1 is accessed by the read and write commands, the data can be read, and the dual-port RAM is used for the control information memory 8. When the data stored in the control information memory 8 is used by another device, the elevator control information reading device 2 does not depend on the access of the MPU of the elevator control device 1.
Data can be read from the control information memory 8 by accessing the MPU 11 on the side.

In this embodiment, an example in which a dual-port RAM is used for the control information memory 8 has been described. Of course, a single-port RAM is used to control access switching between the elevator controller 1 and the information reader 2. The data may be read while reading.

According to this embodiment, since the data is read when the control information memory in the elevator control device is accessed, the elevator control system is not changed,
Detailed control data can be read in real time. In addition, since the data address bus and the bus control signal are input in one direction from the elevator control device via a resistor, the data address bus and the bus control signal of the elevator control device can be used in response to the failure of the loading device. Can be protected.

[0023]

According to the present invention, when the microprocessor in the elevator control device accesses the first control information memory, the control information is transferred from the data / address bus to the second control information memory.
By inputting and storing the information in the control information memory, detailed control information of the elevator control device can be read in real time.

Further, since the data address bus and the bus control signal are inputted in one direction from the elevator control device via the resistor, the data address bus and the bus control signal of the elevator control device are provided in response to the failure of the take-in device. The signal can be protected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an overall configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a detailed circuit configuration of an embodiment of the present invention.

FIG. 3 is an explanatory diagram showing an address map of the elevator control device shown in FIG.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 elevator control device 2 elevator control information reading device 3 connector 4 bus control signal 5 data address bus 6 input circuit 7 access signal generation circuit 8 control information memory 9 control memory 10 work memory 11 microprocessor 61 protection resistor 62 one-way buffer

 ──────────────────────────────────────────────────続 き Continuation of the front page (72) Inventor Hajime Okamoto 1-6-6 Kandanishikicho, Chiyoda-ku, Tokyo Within Hitachi Building System Service Co., Ltd. (56) References JP-A-2-89781 (JP, A)

Claims (3)

(57) [Claims] 1. A microprocessor for performing a control operation of an elevator, a first control information memory for storing control information used for the operation of the microprocessor, and transmission of information between the microprocessor and the control information memory. A data address bus to be performed, and a bus control signal line for transmitting a control signal of the data address bus, wherein the elevator control device is connected to the data address bus and the bus control signal line via a transmission path, and An input circuit for inputting information; an access signal generation circuit connected to the input circuit, the microprocessor detecting information for accessing the control information memory and outputting an access signal; and an access signal generation circuit and the input circuit. Connected and receives the control information transmitted on the data address bus when the access signal is input. An elevator control information reading device, comprising: a second control information memory for storing force. 2. The elevator according to claim 1, wherein the bus control signal line connected to the input circuit is a signal line for controlling reading and writing from the microprocessor to a first control information memory. Control information reading device. 3. The elevator control information reading device according to claim 1, wherein the input circuit comprises a resistor connected in series to the transmission line, and a one-way buffer connected to the resistor.