JP3053661B2 - Serial access memory - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION The present invention, Li - the serial access memory de (read) and the write (write) is performed asynchronously, relates to a serial access memory having a determined test function the quality of memory cells It is.

[0002]

Conventionally, the Te and test function semiconductor memory <br/>, for example, JP 59-63099, JP-Sho 5
No. 9-166879, and Japanese Utility Model Application Laid-Open No. Sho 62-19860.
No. 0 publication and the like.

In a semiconductor memory, for example, dynamic R
There are various memories such as AM, static RAM, and serial access memory.

Conventionally, for example, in the test function dynamic <br/> click RA M, 1 inverted row address stroke - strobe signal RA
During Sn cycle, lights and re - performed with a time difference de La Itode - motor and Li - de de - by detecting the coincidence of the data, has been possible to determine the acceptability of the memory cell.

[0005] Such dynamic R with test function
In the A M, La intended behavior and Li - de operation is performed in synchronization with each other,
Light / Re - Dokontoro - because Le is performed in the same circuit, it allows the determination of the quality of the memory cells in a short time may efficiency.

However, in a serial access memory,
Since the write operation and the read operation are performed asynchronously and the write / read control is executed by separate circuits, it is impossible to directly use the test function used for the dynamic RAM.

[0007] Therefore, in the conventional test function serial access memory, for example, writes to all memory cells, then the written de - Raitode in the tester with the tester reads the data - The memory cell is tested by determining the match / mismatch with the data.

[0008]

SUMMARY OF THE INVENTION However, the conventional
The test function serial access memory, writes to all bits, then Raitode read Te within the tester - Because so as to determine a match / mismatch between the data, large-capacity, high-speed serial access To perform a memory test, a high-performance tester is required, and the operation of the tester becomes complicated. Therefore, it has been difficult to relatively easily test the serial access memory.

The present invention, as a problem which the prior art has had, a write system control - Le and Re - de system control - against Le is a separate serial access memory, without using a high-performance testers, simple it is intended to provide a solution to the test function of the serial <br/> Al access memory for that at Do operation it is difficult to test.

[0010]

According to a first aspect of the present invention, there is provided a memory cell array for storing data in which a plurality of memory cells are arranged, and a write control clock. And write means for writing input data to a predetermined address of the memory cell array based on the read control clock, and read data from a predetermined address of the memory cell array asynchronously with the write means based on a read control clock. In a serial access memory having read means and output means for outputting read data read out by the read means to the outside, the following test is performed.
A mechanism is provided.

That is, in the test mechanism of the serial access memory of the present invention, a serial control memory for generating the write control clock and the read control clock from an externally input control clock based on a mode switching signal. Control clock generating means, and a NOR switch for switching the input data to the write means side of a normal light or the test light determination side based on the mode switching signal.
Multi-write / test-light input switching means, input data switched to the judgment side, and read from the read means.
A coincidence determining means for determining whether or not the data matches or not, and outputting a result of the determination.

According to a second aspect of the present invention, in the first aspect, based on the mode switching signal, the judgment result of the coincidence judging means or the read data from the read means is switched and the output is performed. Normal read / test output switching means for outputting to the means is provided.

According to a third aspect of the present invention, in the first aspect, the output operation of the output means is controlled based on the mode switching signal, and a test result for outputting the judgment result of the coincidence judgment means to the outside. Output means is provided.

According to a fourth aspect of the present invention, in the first, second or third aspect, the mode switching is started by starting a counting operation based on a control signal and counting a predetermined number of the control clocks. Clock counting means for outputting a signal is provided.

[0015]

According to the first aspect of the present invention, as described above, the test function
Since it is configured serial access memory attached, the external input control - when supplied to Rukurokku generating means, said serial control - - Rukurokku serial controller in Rukurokku generating means, mode - write based on de switch signal control - the Rukurokku Occur. The write means is activated based on the write control clock, and writes input data from the normal write / test write input power switching means to the memory cell array.

Thereafter, the serial control clock generating means and the normal write / test write input switching means are switch-controlled by the mode switching signal, and the serial control clock generating means generates a lead control clock. Then, the read means is activated, and data at the time of writing is read from the memory cell array. The read / write data and the input data from the normal write / test write input switching means determine whether the read / write data matches or not, and the result of the determination is output. From this determination result, the quality of the memory cell can be determined.

According to the second aspect of the present invention, the normal read / test output switching means is controlled to be switched by the mode switching signal, and outputs the determination result by the coincidence determination means to the output means in the test mode. At the time of normal data reading, the read data read by the read means is normally read / read.
Output to the output means via the test output switching means.

Therefore, in the test mode, the quality of the memory cell can be determined by detecting the output data of the output means. Further, the normal read / test output switching means switches between the normal read data and the judgment result by the coincidence judging means and outputs the same to the output means. The structure can be simplified.

According to the third aspect, the test result output means outputs the judgment result of the coincidence judgment means to the outside in the test mode. Therefore, the quality of the memory cell can be determined by detecting the output of the test result output means.

According to the fourth aspect of the present invention, the clock counting means, control based on the control signal - counts the Rukurokku, mode - since so as to generate a de-switching signal, the serial access with the test function memory attained is simplification of the circuit configuration of the control signal generating circuit provided outside. Therefore, the above problem can be solved.

[0021]

EXAMPLES First Embodiment FIG. 1 is a block diagram of a schematic of a test function serial <br/> Al access memory showing a first embodiment of the present invention.

In a serial access memory, a memory cell array 1 for storing data in which a plurality of memory cells are arranged.
The writing means 2 and the reading means 3 are connected to the memory cell array 1. The write means 2 is reset by the inverted write reset signal WRn, converts the serially input data into parallel based on the internal write control clock WCK1, and selects it by a decoder (not shown). Memory cell array 1
It has a function of writing to a predetermined address in the register, and is composed of a shift register, a transfer gate and the like.

The read means 3 outputs an inverted read reset signal R
Rn, the data at a predetermined address in the memory cell array 1 selected by a decoder (not shown) is read out in parallel based on the internal read control clock RCK1, and the parallel data is read out as serial data.
This is a circuit that converts the data into data and outputs it, and is composed of a shift register, a transfer gate, and the like.

In such a serial access memory ,
Serial controller constituting the test mechanism - Rukurokku generating means 10 is provided. The serial control clock generating means 10 generates a signal based on the mode switching signal Pt.
Either the write control clock WCK of the external input or the read control clock RCK of the external input is selectively taken in, the write means 2 and the read means 3
Write control clock WCK1 to supply to
And a circuit for generating a read control clock RCK1.

The serial control clock generating means 10 is provided with an externally input write control clock WC.
Tri-state inverters 11 and 12 connected to K
And a tri-state inverter 13 connected to a read control clock RCK of an external input, which are turned on and off via inverters 14 and 15 for inverting a mode switching signal. It has become so. From the output of the tri-state inverter 11, an internal write control clock WCK1 is output via an inverter 16 for signal inversion. Further, the internal read control clock RCK1 is output from the 3-state inverters 12 and 13 via an inverter 17 for signal inversion.

Further, an input means 20 for inputting input data Din based on an externally input write control clock WCK is provided. The input means 20 is composed of a buffer or the like. The output side of the input means 20 is connected to the writing means 2 via a normal light / test light input switching means 30 and a normal light / test light input switching means. The coincidence determination means 40 is connected via the inverter 30 and the inverter 35. The normal light / test light input switching means 30 converts the input data Din from the input means 20 into the normal light writing means 2 side or the test light coincidence judging means 40 based on the mode switching signal Pt. It has the function of switching to the side.

The normal light / test light input switching means 30 includes a tri-state inverter 31 for outputting input data S31 to the writing means 2, and an inverter 35.
Tri-state inverter that outputs input data S32 to
And a tri-state inverter 3
1 and 32 receive a mode switching signal P via an inverter 33.
On and off operations are complementarily performed by t. The input data S32 output from the normal light / test light input switching means 30 is inverted by the inverter 35 to become data S35, and the data S35 and the data S35 are read out.
The read data S3 of the loading means 3 is connected to the input side of the coincidence determination means 40.

The coincidence judging means 40 reads the data S35
This is a circuit for judging the coincidence / non-coincidence with the data S3 and outputting the result of the judgment, and is composed of, for example, an exclusive OR gate (hereinafter referred to as ExOR) 41.
An output means 60 is connected to the output side of the coincidence determination means 40 and the output side of the lead means 3 via a normal lead / test output switching means 50.

Normal read / test output switching means 50
Has a function of switching either the judgment result of the coincidence judging means 40 or the read data S3 of the reading means 3 and sending it to the output means 60 based on the mode switching signal Pt. . This normal lead / test output switching means 50
Tri-state inverter for sending the judgment result to output means 60
And a tri-state inverter 52 for sending the read data S3 of the read means 3 to the output means 60, which are complemented by the mode switching signal Pt via the inverter 53. It is configured to perform on and off operations.

The output means 60 drives the output of the normal read / test output switching means 50 and outputs the output data Dout.
And outputs to the outside in the form of an output buffer and the like.

Next, the operation of FIG. 1 will be described with reference to FIG.

FIG. 2 is a time chart showing the operation of FIG. Ta indicates a serial write mode period, Tb indicates a test mode period, and HZ indicates a high impedance.

In the serial write mode period Ta from time t0 to time t1 in FIG. 2, the write reset signal WRn and the read reset signal RRn become "L" at time t0, and the write means 2 and the read means 3 Is reset.
At this time, the externally-written write control clock WCK
Rises to "H", and each circuit is initialized in synchronization therewith.

In the serial write mode period Ta, the mode
Since the mode switching signal Pt is "L", the tri-state inverter 1 in the serial control clock generating means 10 is used.
Only 1 is turned on, and the external input write control
The control signal WCK is input to the tri-state inverter 11 and is output via the inverter 16 in the form of an internal write control clock WCK1. At this time,
The output data Dout of the output means 60 is in a high impedance HZ state.

In the serial write mode period Ta,
External input read control clock RCK is "L"
In the subsequent test mode period Tb,
Although "L" is maintained, the clock may be input to the serial control clock generating means 10.

The input means 20 serially inputs 01101... From the first bit of the input data Din in synchronization with the rise of the write control clock WCK. Since the mode switching signal Pt is "L", only the 3-state inverter 31 in the normal write / test write input switching means 30 is turned on, and the input data Din input from the input means 20 is input. Is sent to the writing means 2 in the form of S31.

The write means 2 converts the input data S31 into parallel data based on the internal write control clock WCK1, and converts the parallel data into the memory cell array 1 selected by a decoder (not shown). At a predetermined address.

When the mode switching signal Pt becomes "H" and the test mode period Tb starts, at time t1, the write reset signal WRn and the read reset signal RRn become "L", and the write means 2 and the read means The means 3 is initialized and the access address becomes the head address.

When the mode switching signal Pt becomes "H", only the tri-state inverter 12 in the serial control clock generating means 10 is turned on. further,
Only the tri-state inverter 32 in the normal light / test light input switching means 30 is turned on, and only the tri-state inverter 51 in the normal read / test output switching means 50 is turned on. Becomes

Then, the externally input write control clock WCK is output in the form of the internal read control clock RCK1 via the tri-state inverter 12 and the inverter 17 in the ON state. 3 starts the read operation. At this time, the supply of the write control clock WCK1 to the writing means 2 is stopped, so that the writing operation of the writing means 2 is stopped.

The read means 3 reads the write data in parallel from the head address in the memory cell array 1 and outputs it to the coincidence determination means 40 in the form of serial read data S3. The input data Din input from the input means 22 is sent to the coincidence determining means 40 via the tri-state inverter 32 and the inverter 35 in the normal light / test light input switching means 30.

The coincidence judging means 40 judges whether the data S35 from the inverter 35 matches the read data S3. The judgment result of the coincidence judging means 40 is sent to the output means 60 via the tri-state inverter 51 in the normal read / test output switching means 50, and the output means 60 outputs the output data Dout. Is output to outside.

At time t1, since the input data Din is 0, the data S35 of the inverter 35 is 0, and the read data S3 is also 0, the coincidence determination means 40 sets the data S35.
It is determined that read data S3 and read data S3 match. Therefore, the output data Dout becomes "L". As described above, in the test mode period Tb, the memory test is started from the first bit, and since the write data from the first bit is 01101..., After time t1, the read data S3 becomes 01101. Is the normal state.

However, at time t2, for example, 011
As in the case of 11..., The output of all the bits is correctly 0 but 1 is 1. Therefore, the coincidence determination means 40 outputs the data S3
5 and the read data S3 are detected to be inconsistent, and the output data Dout becomes "H" indicating the inconsistency.

In this manner, the determination of the match / mismatch between the input data Din and the read data S3 from the memory cell array 1 is performed.

This embodiment has the following advantages.

In this embodiment, an internal input write control clock WCK is supplied to the serial control clock generating means 10, and the serial control clock generating means 10 outputs an internal write control clock WCK1. 2 is operated to write the input data Din into the memory cell array 1. After that, the output of the serial control clock generating means 10 is switched by the mode switching signal Pt, and the internal read control clock RCK1 is converted from the externally input write control clock WCK by the serial control clock generating means 10. Then, the read means 3 is operated by the read control clock RCK1, and the read data is read by the read means 3 from the memory cell array 1 in the form of read data S3.

Then, the coincidence judging means 40 judges whether or not the input data Din (S35) and the read data S3 match or not, and switches the normal / test output switching based on the judgment result. The data is output to the output means 60 via the means 50.

As described above, by repeating the input of only the single external input write control clock WCK twice, it is possible to determine the quality of the memory cells in the memory cell array 1. Therefore, the write control clock WCK of the external input can be used without using a conventional high performance tester.
The memory test can be easily and accurately performed by a simple operation of inputting the two times and inputting the mode switching signal Pt.

In this embodiment, when the memory cell is operating normally, the output data Dout, which is the test result, is output.
Is "L", and at the time of abnormal operation, it is "H". Therefore, the output data Dout at time t1 is "L". On the other hand, as shown in the waveform diagram in parentheses in FIG. 2, the output data Dout-1 of the test result is:
When the memory cell is normal, the high impedance HZ, 0
The condition for setting the judgment result is such that it becomes "L" when an expected failure (failure when the write data is 0) and "H" when an expected failure (failure when the write data is 1). You may. With such a setting, it can be determined whether the memory cell is 0 and defective or 1 and defective.

[0051] Second Embodiment FIG. 3 is a block diagram of a schematic of a test function shea <br/> real access memory according to a second embodiment of the present invention,
Elements common to those in FIG. 1 are denoted by common reference numerals.

This serial access memo with test function
In Li, instead of the output unit 60 in FIG. 1, is provided with different output unit 60A of configuration, further Roh 1 - Maruri - instead of de / test output switching means 50, provided the test result output means 61 Have been.

The output means 60A is a circuit for controlling the output of the read data S3 based on the mode switching signal Pt.
In the serial read mode period, the read data S3 from the read means 3 is output to the outside in the form of output data Dout, and the serial write mode period Ta and the test mode are output.
In the data period Tb, the output data Dout has a function of setting to high impedance HZ. The test result output means 61 outputs the judgment result of the coincidence judgment means 40 to the judgment result P
This is a circuit for outputting to the outside in the form of K.

FIG. 4 is a time chart showing the operation of FIG.

This serial access memo with test function
The serial write mode period Ta and the test mode
In the mode period Tb, the output data Dout of the output means 60A is in the high impedance HZ state by the mode switching signal Pt. Then, as in the first embodiment, in the serial write mode period Ta, the input data D
“in” is written into the memory cell array 1 by the write means 2. During the serial write mode period Ta, since the coincidence determination means 40 does not operate, the test result output means 6
The determination result PK of “1” is “L”.

In the test mode period Tb, as in the first embodiment, the internal read control clock RC is used.
K1 causes the read means 3 to read the write data from the memory cell array 1. At this time, since the output data Dout of the output means 60A is in the high impedance HZ by the mode switching signal Pt, the read data S3 is transmitted from the read means 3 to the coincidence determination means 40. Can be

In the coincidence judging means 40, as in the first embodiment, the normal light / test light input switching means 30
Of the input data S35 (Din), and outputs the determination result to the outside through the test result output means 61. The judgment result PK output from the test result output means 61 becomes "L" when the memory cell operates normally and becomes "H" when the memory cell operates abnormally. Time t2 in FIG.
Since the data S35 is 0 and the read data S3 is 1, the coincidence judging means 40 judges that they do not match, and the judgment result P
K becomes "H".

In this way, the judgment on the defective bit in the memory cell array 1 can be determined from the judgment result PK, and the same advantages as in the first embodiment can be obtained. In the second embodiment, since a dedicated test result output means 61 for detecting the determination result PK is provided, the test result can be known by detecting the output. The judgment result PK is high impedance HZ when normal, "L" when 0 expected failure, "H" when 1 expected failure.
The circuit configuration may be as follows.

[0059] Figure 5 is a third embodiment, a third block diagram of a schematic of a test function shea <br/> real access memory of an embodiment of the present invention,
Elements common to those in FIG. 1 are denoted by common reference numerals.

This serial access memo with test function
In the first embodiment, a clock counting means 70 is provided in the first embodiment, and the mode switching signal Pt is
Is generated.

The clock counting means 70 is reset by the inverted read reset signal RRn, activated by the control signal P and starts counting operation, counts the number of write control clocks WCK of the external input, and counts all the clocks. An "L" inverted read reset signal RR for resetting the read means 3 after the end of bit writing.
na and outputs a mode switching signal Pt of "H". With the mode switching signal Pt, the switching operation of the serial control clock generating means 10, the normal write / test write input switching means 30, and the normal read / test output switching means 50 is performed.

FIG. 6 is a time chart showing the operation of FIG.

This serial access memo with test function
At time t, the control signal P becomes "H" and the operation shifts to the serial write mode period Ta at time t0. When the control signal P becomes "H", the clock counting means 70 counts the number of clocks of the externally applied write control clock WCK. In the serial write mode period Ta, the input data to the memory cell array 1 is changed in the same manner as in the first embodiment.
Data Din is written.

When the writing of all bits is completed, the clock counting means 70 sets the mode switching signal Pt to "H". Further, the clock counting means 70 sets the read reset signal RRna to "L" at time t1, and initializes the read means 3. As a result, the process moves to the test mode period Tb, and the memory test is executed as in the first embodiment. The output data Dout becomes "L" when the memory cell operates normally, and becomes "H" when the memory cell operates abnormally. Therefore, the same advantages as in the first embodiment can be obtained.

As described in the first embodiment, the output data Dout, which is the result of the judgment, is high impedance HZ during normal operation, “L” when 0 expected failure,
The configuration may be such that it becomes "H" at the time of one expected failure. In the second embodiment, since the mode switching signal Pt is generated by the clock counting means 70 based on the control signal P, an external control signal circuit system is simpler than the first embodiment.

[0066] Taimuchiya Fourth Embodiment FIG. 7, the fourth block diagram of a test function is shown an embodiment with shea <br/> real access memory schematic of the present invention, and FIG. 8 showing the operation ―

This serial access memo with test function
In Li, clock counting means 70 of FIG. 5 in the apparatus of FIG. 3
Is provided.

Therefore, as in the second embodiment, switching between the serial write mode period Ta and the test mode period Tb is performed by the mode switching signal Pt generated by the clock counting means 70. During the storage period Tb, the match determination unit 40 determines the match / mismatch.
This determination result is output to the outside via the test result output means 61 in the form of a determination result PK.

The determination result PK is determined by the high impedance HZ and the test mode period T during the serial write mode period Ta.
At b, it becomes "L" during normal operation and "H" during abnormal operation. Therefore, the same advantages as those of the second embodiment can be obtained, and the mode switching signal Pt is generated by the clock counting means 70, so that an external control signal generating circuit is simplified.

The present invention is not limited to the above embodiment,
Various modifications are possible. For example, serial control
The normal clock generating means 10, the normal write / test write input switching means 30, and the normal read / test output switching means 50 are constituted by using a tri-state buffer or another gate circuit, or the like. The coincidence determination means 40 is connected to another gate such as an exclusive OR gate (ExOR).
May be configured.

[0071]

As described above in detail, according to the first aspect, since the serial control clock generating means, the normal write / test write input switching means, and the coincidence determining means are provided, external input is provided. Only the control clock of either the read control or the write control is supplied twice to the serial control clock generating means, and the write control clock or the read control clock output from the serial control clock generating means is supplied twice. By switching and outputting with the mode switching signal,
Switching between serial write mode and test mode. Then, in the test mode, the input data and the read data by the read means are compared by the coincidence judging means, and the quality of the memory cell is judged. Therefore, a memory test can be accurately performed with a simple operation without requiring a conventional tester.

According to the second aspect of the present invention, since the normal read / test output switching means is provided, the judgment result of the coincidence judging means or the read from the reading means is provided by the mode switching signal. The data can be switched and output to the output means. Therefore, by detecting the output data of the output means, the quality of the memory cell in the test mode can be easily detected.

According to the third aspect of the present invention, since the test result output means is provided, the output of the test result output means is detected, so that it is possible to easily know the determination result of the memory cell in the test mode. Can be.

According to the fourth aspect, since the clock counting means is provided, the mode switching signal can be generated by the clock counting means. Therefore, it is possible to simplify the control signal generation circuit external to the control signal given to the test mechanism of the serial access memory.

[Brief description of the drawings]

1 is a block diagram of a schematic of a serial access <br/> memory showing a first embodiment of the present invention.

FIG. 2 is a time chart showing the operation of FIG.

3 is a block diagram of a schematic of a serial access <br/> memory of a second embodiment of the present invention.

FIG. 4 is a time chart showing the operation of FIG. 3;

5 is a block diagram of a schematic of a serial access <br/> memory of a third embodiment of the present invention.

FIG. 6 is a time chart showing the operation of FIG. 5;

7 is a block diagram of a schematic of a serial access <br/> memory of a fourth embodiment of the present invention.

FIG. 8 is a time chart showing the operation of FIG. 7;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 memory cell array 2 write means 3 read means 10 serial control clock generating means 20 input means 30 normal write / test write input switching means 40 coincidence determining means 50 normal read / test output switching means 60 output means 61 Test result output means 70 Clock count means

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) G11C 29/00 G11C 8/04

Claims (4)

(57) [Claims] 1. A memory cell array for storing data in which a plurality of memory cells are arranged, a write means for writing input data to a predetermined address of the memory cell array based on a write control clock, and a write control means based on a read control clock. Read means for reading data from a predetermined address of the memory cell array asynchronously with the write means, and output means for outputting the read data read by the read means to the outside. In the serial access memory, a serial control clock generating means for generating the write control clock and the read control clock from an externally input control clock based on a mode switching signal; and based on the mode switching signal. The input data is transmitted to the writing means side of a normal light or A normal light / test light input switching means for switching to the determination side of the stride; and a match / mismatch between input data switched to the determination side and read data from the read means. serial access memory, characterized in that the coincidence judgment means for outputting a determination result performed determination, comprising the. 2. A method according to claim 1 serial access memory to <br/> Oite described, the mode - de on the basis of the switching signal, the determination result of said match determination means or the Li - Li from de means - de de - switching the data outputted to the output means Roh - Maruri - de / test serial access memory provided with the output switching means. 3. A serial access memory to <br/> Oite of claim 1, wherein the motor - the configuration for controlling the output operation of the output means based on de switching signal, and the determination result of said match determination means serial access memory in which a test result output means for outputting to the outside. 4. A serial access memory according to claim 1, wherein Oite, to start the counting operation based on the control signal the control - the de switching signal - the motor by counting a predetermined number of Rukurokku serial access memory having a clock counting means for outputting.