SU1425693A1 - Storage - Google Patents

Abstract

The invention relates to digital computing and can be used in microprocessor systems and microcomputers. The aim of the invention is to expand the functionality of the device by providing an erase mode. The storage device contains a memory block 1, a data register 2, an address register 3, a bus data generator 4, two address decoders 5.6, a synchronization unit 7, a control unit 8, a response signal conditioner 9, a 1U cycle conditioner, a decoder 1.1, and a mode register 12. The introduction of a second address decoder and mode register, which made it possible to organize the modes of electrical erasure of information and reprogramming, is new in the device. 4 il. i SL With Fig.1

Description

The invention relates to the field of digital computing and can be used in microprocessor systems and microcomputers.

The purpose of the invention is to expand the functionality of the device by providing an erase mode.

Fig, 1 shows the functional diagram of the storage device; figure 2 - the timing diagram of the device in the read mode; FIG. 3 is a time diagram of the operation of the device in the Record mode; , figure 4 - time diagram of the device in the Programming mode.

The storage device contains a 1-unit block, a data register 2, an address register 3, a data bus driver 4, two decoder 5 and 6 addresses, a synchronization block 7, a control block 8, a response signal driver 9, a cycle driver 10, a decoder 11, and a register 12 modes.

The entire address space of the processor is 2, where p is the width of the processor address, divided into t equal banks, with (t-1) junior banks allocated for processor memory banks, the senior bank is the bank allocated for external device registers.

Memory unit 1 of the memory device can occupy from one to i memory banks in the address space of the processor, moreover i6 (t-1), the register of 12 modes occupies one address in the bank of external devices of the processor. The external memory block in the next G device is divided into memory modules, with the lower address bits of the processor being used directly to address the memory cell inside the memory module of the memory device, the high address bits are used. select the required memory bank, and the total number of banks in the address space of the processor is determined by the ratio. The number of memory modules in one memory ank is determined by the j address bits, which are intermediate between the lower and middle address bits and equal to 2, where (m + n). The total number of memory modules R is determined by the ratio R i-2

The address of memory block 1 is decrypted and the number of memory banks is selected using the first device address decoder 5, whose information inputs are connected to the m old address bits required for selecting memory banks.

The device works as follows.

The device provides modes

5 works: Reading, Programming and Erasing, and the data is read in Read cycles (THB), and programming and data erasure takes 0 seconds in Write cycles (MT).

The programming of data in memory block 1 is possible only when the enable signal of the operation of the generator 10 of the cycle 5, formed by the register of 12 modes, is set. The mode of erasing data in memory block 1 is possible only when the erase enable signal and the ramp signal of the shaper 10 are formed, which are generated by a register of 12 modes. The signals at the outputs of the register of 12 modes can be set and reset in the Record cycle. In addition, the register of 12 modes is reset when

5 Signal Appearance Setup (SET). It is only possible to read data from the device.

In the Read loop, the processor sets the information on the device I / O to the address of one of the memory cells of the device memory 1, which is via the data bus 4 and the ad-i register 3. Rece is transmitted to the device address bus. Next, the Exchange signal (MBP), which is broadcast via synchronization unit 7 to the device, gates the address in the address register 3. Address: arrives.

0 to the inputs of the address of block 1 of memory, the inputs of the first decoder 5 device addresses, the inputs of the second decoder 6 device addresses, to the second group of inputs of the decoder 11. In this case

5, the address is decrypted by the first decoder 5 of the device address, with the major address being sent to the senior address input of the memory unit 1. Signal0

3

The decryption modules of the memory from the outputs of the first decoder 5 are fed to the first group of inputs of the decoder 11, as a result of which a signal is established to select only the required memory module. In addition, the read signal is transmitted through the control unit 8 to the input of the bus driver of the data 4, to the first inputs of the decoder 11 and the driver 9 of the response signal. The output of the decoder 11 sets a signal. Selecting the output of the memory block 1, as a result of which data is read from the memory cell of the selected memory module through the bus data 4, the output of the response signal generator 9 is set to the Response signal, as a result, the device stops reading data from the memory cell of memory 1, the bus driver 4 is switched, and thus the reading of their memory device 1 of the device ends.

Data is entered into the register of 12 modes in a write cycle, in the address part of the cycle the address translation into the device is similar to the Read cycle, but the address is decrypted by the first decoder 5 of the device address so that its output sets the enable signal of the second decoder 6 device address, the inputs of which in this case do not need to apply m high-order address bits necessary for selecting a bank of external devices. At the output of the second device address decoder 6, a device operation enable signal is set, on which data is written to. register 1 2 modes in the presence of a signal Recording device, which through the control unit 8 is fed to the input of the record of the mode register 12. As a result, an output signal is set at the output of the response signal generator 9, which informs the processor that the data recording in the mode register 12 has occurred. Cycle Recording is over.

Before programming the memory block 1 of the device, the processor starts in a cycle. Writing 12 modes to the register transforms the data so that the output of the register is 12 modes

25693

a permission signal was set for operation of the formers of the 10th cycle. There is no erase enable signal. Next, the processor starts the cycle Write to memory device 1 of the device.

The processor sets the address of the selected memory location, which

10 is transmitted through the data driver 4 to the inputs of the address register 3, then decrypted by the first address decoder 5 and the decoder 11, and the decoder 11 sets one of the signals to select the chip that selects the memory module of the corresponding memory cell to which the data will be recorded. According to the signal of the exchange rate, the address is built in the register 3 of the device address, and the recorded data through the bus driver 4 is fed to the inputs of the register 2 of the data. Next on the Record signal, which

25 is transmitted through the control unit 8 to the inputs of the cycle generator 10 and the response signal generator 9, a low active level cycle signal (SC) is generated, which is sent 30

blunt to the entry of register 2

40

data. In this case, the data at its inputs are stored in it for the duration of the operation (SC ;,), after that the device sets the TSS signal, indicating that the data is recorded in the device data register 2. Signal Record device removed. This causes the cycle signal generator 10 to set a cycle signal (SC; high active level, which is fed to the data enable input of the data bus 4 and the data register 2 read input. At the same time, the data bus 4 is turned off and its outputs go - water in the high-impedance state, besides this, reading of data from data register 2 is permitted.

 At the output level of the cycle former 10, the operation of the control unit 8 is inhibited, the signal OT7 is removed and thus the cycle of the Record ends. In this case, the programming voltage U55, E, is supplied to the input voltage of the programming unit 1 of the memory at the time of programming. From the time the voltage is applied

45

programming 1} to the input of memory block 1 in it starts writing data to the memory cell of the selected memory module. Upon completion of writing to the memory cell of the memory 1, the SC signal and the programming voltage are output from the programming voltage output of the device 1 memory.

Erasing information in the device is carried out simultaneously in all cells of the selected memory module of memory block 1. Before the start of erasing in the cycle. Record in the register 12 modes send data in such a way that the outputs of the register 12 modes set the enable signal of the shaper 10 and the erase enable signal, which is fed to the input of the decoder 11. At the same time, the output of the output of memory 1 is selected. the erase voltage is applied and the device is pushed to the erase mode in the memory block 1. Erasing one memory module is performed in a cycle Writing data to memory block 1. The state of the signals at the information I / Os and address inputs of memory 1 during the erasure is indifferent. To erase all the memory modules of the process unit, it executes R cycles Writing to memory block 1, where R is the total number of memory modules. After the erasing of information in block 1 of the device memory is completed, the processor in the cycle Writing in the register of 12 modes sends data that prohibits erase mode in the device and prohibits the operation of the generator 10 of the cycle.

When the Regeneration signal is given, the device shuts down and does not interfere with the regeneration of RAM if it is in the system.

Claims (1)

Invention Formula A memory device containing a memory block, a register, a data register, an address register, a bus data generator, a synchronization unit, a control unit, a first address decoder, a response signal conditioner, a cycle conditioner, and a decoder, the information inputs of the device connected to the information inputs-outputs first group 4256936 bus data generator, informational inputs-outputs of the second group of which are connected to informational inputs of the data register, address register and memory block, the address inputs of which are connected to the outputs of the lower bits of the address register address, the outputs of the older ones 10 bits of the address of which are connected to the information inputs of the first address decoder and information inputs of the first group of the decoder, information inputs of the second J5 groups which are connected to the output first address decoder, exit. the older bit of the address of which is connected to the input of the higher bit of the address of the memory block, the inputs of the The crystal chip 20 and the input selection of which are connected respectively to the chip selection and selection of the output of the decoder, the input resolution of which is connected, respectively, with the scoring input input on the bus data generator, the first input of the resolution comparing the response generator and the first output of the block management, 2Q first, second and third inputs of which are connected respectively to the inputs of the Regeneration, Reading and Writing signals., The output of the signal whose response is connected to the output of the signal generator from 35 40 45 50 55 A first recording input of which is connected to the recording input of the loop generator, and a second output of the control unit whose fourth input is connected to the output of the signal of the first low-level cycle loop generator and the first recording input of the address register, the second recording input of which is connected to the first output of the The synchronization and synchronizing input of the loop generator, the output of the signal of the first high level loop of which is connected to the enable input of the bus data generator and the input of the data register, the write input to orogo connected to the output low level shaper cycle the second cycle signal, output voltage programming coupled to an input voltage programming the memory unit, the input voltage programming tsikla- shaper connected to the input voltage programming device input signa 7 The exchange of which is connected to the first input of the synchronization unit, the second output of which is connected to the fifth input of the control unit, the sixth input of which is connected to the output of the corresponding bit of the first address decoder, the outputs of the data register are connected to the information inputs of the memory block, which differs so that, in order to expand the functionality by providing an erase information mode, the second address decoder and mode register are entered into it, the erase resolution output of which is connected to the enable input The erasure of the descrambler, whose recording input is connected to the sixth input of the control unit, the third output of which is connected respectively to the reset inputs of the mode register and the loop former, whose operation enable input is connected to of the modes whose recording input is connected to the fourth output of the control unit and the second input of the response signal generator, the second read enable input of which is connected to the fifth output of the control unit, the sixth output of which is connected to the second input of the synchronization unit, the information inputs of the mode register are connected respectively to information the inputs of the address register, the outputs of which are connected to the information inputs of the second address decoder, the output of which is connected to the seventh input of the control unit, are eight second input coupled to the input for setting the device input erase voltage coupled to an input voltage of the erase decoder, output resolution of the first address decoder coupled to the enable input of the second decoder al register resolution output 25 Ldr ACR WesUG Data ORP .J Thebes. 2 zhi h