JPS6230461B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to semiconductor memory circuits.

In the conventional memory circuit, as shown in FIG. 1, write information is held at a selected location in the memory circuit section M through write information input buffers WDI to WDN.
The read information is outputted from a selected portion of the memory circuit M through the read information output buffers OBI to OBN and from the read information output terminals OPI to OPN. In this case, in the write cycle, information is simply written to a certain location in the memory circuit section M specified based on the write control circuit, while in the read cycle, read information is only output from a certain location in the specified memory circuit section M. It ended in Therefore, the serial write and read information transfer speed is limited by the memory circuit section M of the memory circuit.

An object of the present invention is to provide a storage device that can transfer information at high speed.

The present invention includes first and second write hold circuits commonly connected to a write buffer, a write gate circuit that supplies each output of the first and second write hold circuits to an input of a memory, and a write gate circuit common to the memory. first and second read and hold circuits connected to;
It has a read gate circuit that outputs each output of the first and second read holding circuits to an output terminal, and a write and read control circuit, and the write control circuit transfers the output from the write buffer to the first write hold circuit. supplying the output of the second write hold circuit to the memory via the write gate while writing information to the memory, and the read control circuit supplying the output of the second write hold circuit to the memory while information is being read from the memory to the first read hold circuit;
The output of the second read and hold circuit is supplied to the output terminal via the read gate, and while information is being written to the memory from the first or second write and hold circuit, the first or second The present invention is characterized in that the output of the second read/hold circuit is supplied to the output terminal.

Next, an embodiment of the present invention will be described with reference to FIGS. 2 and 3.

As shown in Figure 2, multiple write information holding circuits are provided in the write information input buffers WDI to WDN.
Connect WRIA~WRNA and WRIB~WRNB in parallel. Write information holding circuit WRIA~WRNA and
A write information latch circuit WR and a write information selection circuit WX are provided to control WRIB to WRNB. Read information holding circuits RRIA to RRNA and RRIB to RRNB are connected in parallel to the output of the memory circuit section M. The write clock generator WCG is connected to the write information latch circuit WR, the write information selection circuit WX, and the write clock generation circuit WE, and is connected to the signal line 1.
~Control 4. Read clock generator
RCG is connected to read information latch circuit ME, read information selection circuit RX, and read clock generation circuit RR, and controls signal lines 5-8. Read information gate circuit RGI~RGN, read information output buffer OBI~
A read information output clock circuit RR is provided to control the OBN, and a read information holding circuit is provided.
A read information latch circuit ME and a read information selection circuit RX are provided to control RRIA to RRNA and RRIB to RRNB. In addition, the number of write information holding circuits connected in parallel can be increased by using a write information selection circuit.
This can be easily done by increasing WX, and the number of read information holding circuits connected in parallel can be easily increased by increasing read information selection circuits RX.

Next, the operation will be explained using FIG. In the write cycle, write information input buffer WDI
The write information in ~WDN is written to either write information holding circuits WRIA~WRNA or WRIB~WRNB. This selection is signal line 1 and signal line 2
This is done by setting either one to "0". Signal line 1 becomes "0" when write information selection circuit WX is "0" and write information latch circuit WR is "0", while signal line 2 becomes "0" when write information selection circuit WX is "1" and write information latch circuit WR is "0". becomes “0” when is “0”. Now, when the write information selection circuit WX is set to "0" and the write information latch circuit WR is set to "0", the signal line 1 becomes "0" and the write information holding circuits WRIB to WRNB are enabled to write the write information. , WRIA~WRNA side is signal line 2
Since this becomes "1", writing is disabled. At this time, the gates of write information gate circuits WGI to WGN are opened when signal line 3 or signal line 4 is "0", and in signal line 3, write information selection circuit WX is "0" and clock WE is "0". When , it becomes "0" and the information on the write information holding circuits WRIA to WRNA side is transferred to the storage circuit section M. The signal line 4 becomes "0" when the write information selection circuit WX is "1" and WE is "0", and transfers the information on the WRIB to WRNB side of the write information holding circuit to the memory circuit section M. In the above explanation, the write information selection circuit WX was "0", so when WE is set to "0", the signal line 3 becomes "0" and the write information holding circuit
The write information in WRIA to WRNA is transferred to the memory circuit M. At this time, the write information holding circuit WRIB~
The output of WRNB is forced to "0" and confined within the write information gate circuit.

On the other hand, in the read cycle, the read information RDI~RDN output from the memory circuit section M is output to the read information holding circuits RRIA~RRNA or RRIB~
Whether to output to RRNB is determined by signal line 5 and signal line 6.
One of them is determined to be "0".
The signal line 5 becomes “0” in the read information selection circuit.
RX is “0” and read information latch circuit ME
is "0", and the signal line 6 becomes "0" when the read information selection circuit RX is "1" and ME is "0". Now, set the read information selection circuit RX to “0”
When the read information latch circuit ME is set to "0", the signal line 5 becomes "0" and the read information holding circuit is set to "0".
Read information is introduced into RRIB~RRNB, and RRIA~
The signal line 6 becomes "1" and is not introduced to the RRNA side. At this time, the gates of the read information gate circuits RGI to RGN are opened when the signal line 7 or signal line 8 is "0". The signal line 7 becomes 0 when the read information selection circuit RX is 0 and the read information output clock is set to 0.
When RR is “0”, the read information holding circuit RRIA~
The read information on the RRNA side is the read information output buffer.
Output through OBI~OBN. The signal line 8 becomes “0” when the read information selection circuit RX is “1”
When the read information output clock RR is “0”,
Read information on the read information holding circuits RRIB to RRNB is outputted through read information output buffers OBI to OBN. Here, since the read information selection circuit RX is "0", when the read information output clock RR is set to "0", the signal line 7 becomes "0" and the read information from the read information holding circuits RRIA to RRNA is transferred to the read information output buffer. Output through OBI~OBN. At this time, the outputs of the read information holding circuits RRIB to RRNB are forced to "0" and confined within the read information gate circuits RGI to RGN.

According to the above embodiment, the write buffer WDI ~
WDN to one write hold circuit (e.g.
When writing information to WRIA~WRNA), the information already written to the other write holding circuit (for example, WRIB~WRNB) is transferred to the gate circuit WGI~
It is possible to write to memory M via WGN.
In addition, one read hold circuit (RRIA
~RRNA), the information already read to the other read holding circuit (RRIB~RRNB) can be output from the output terminals OPI~OPN via the read buffers DBI~DBN.
Therefore, reading and writing can be performed at an apparent double speed. Therefore, when writing and reading are performed alternately as in the past, both writing and reading can be performed during the same writing time as in the past, so from the user's perspective, it is as if reading and writing information is being done at the same time. Looks like it's running.

Further, according to the present invention, while information is written from the write buffer to one of the write and hold circuits WRIA to WRNA, one of the read and hold circuits RRIM is transferred from the memory M to one of the read and hold circuits RRIM.
~Read information to RRNA, then write another write information from the buffer to the other write holding circuit WRIB
While writing to ~WRNB, the information previously written to the write holding circuit WRIA ~ WRNA is written to memory M, and at the same time, the information written to the read holding circuit WRIA ~ WRNA is written to the memory M.
~The information already read out to RRNA can actually be read out from the output terminal via the gate. Such processing is effective in systems where memory access intervals are long, but reading and writing are required to be performed at high speed when accessing.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional storage device, FIG. 2 is a block diagram showing a storage device according to an embodiment of the present invention, and FIG. 3 is a waveform diagram showing the operation of the device shown in FIG. WDI~WDN...Writing information input buffer 1
Bit ~ N bit, WRIA ~ WRNA... 1 bit ~ N bit on write information holding circuit A side, WRIB ~
WRNB...1 bit to N bits on the write information holding circuit B side, WGI to WGN...1 bit to N bits on the write information gate circuit A side, WCG...write clock generator, M...memory circuit section, WR ……
Write information latch circuit, WX...Write information selection circuit, WE...Write and read clock of memory circuit section, RQ...True output of write/read information holding circuit, RO...False output of write/read information holding circuit , 1, 2, 5, 6... write clock,
3, 4, 7, 8...Read clock, RDI~RDN
...Read information 1 bit ~ N bits, RRIA ~
RRNA...1 bit on read information holding circuit A side ~
N bits, RRIB to RRNB...1 bit to N bits on the read information holding circuit B side, RGI to RGN...1 bit to N bits on the read information gate circuit A side,
RCG...Read clock generator, OBI~OBN...
...1 bit to N bits of the read information output buffer, OPI to OPN...1 bit to N bits of the read information output terminal, ME...read information latch circuit,
RX...Read information selection circuit, RR...Read information output clock.

Claims (1)

[Claims] 1 first and second write hold circuits commonly connected to a write buffer; a write gate circuit that provides each output of the first and second write hold circuits to an input of a memory; and a write gate circuit commonly connected to the memory. the first and second read and hold circuits;
and a read gate circuit that outputs each output of the second read hold circuit to an output terminal, and a write and read control circuit, the write control circuit transmitting information from the write buffer to the first write hold circuit. supplying the output of the second write hold circuit to the memory via the write gate during writing;
The read control circuit controls the second read holding circuit while information is being read from the memory to the first read holding circuit.
The output of the read hold circuit is supplied to the output terminal via the read gate, and while information is being written to the memory from the first or second write hold circuit, the first or second read A storage device characterized in that an output of a holding circuit is supplied to the output terminal.