JPH0425568B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer system, and more particularly to a power supply self-holding circuit that performs power supply/cutoff control by the microcomputer itself.

A conventional circuit of this type is shown in FIG. In FIG. 1, 1 is a microcomputer, the one marked Vcc indicates the power supply terminal (+ side), and the one marked Vcc indicates the reset signal input terminal to which a reset signal of level "L" is input.
The one marked PORT1 outputs a power hold signal at level "H" and becomes high impedance upon reset. The one marked PORT2 is a signal input terminal. The one marked PORT0 is used for the purpose of information processing. - Indicates signal input/output terminals for control. 2 indicates the power switch,
3a and 3b are resistors PORT1 and PORT, respectively.
Pull down the terminal 2 to ground potential. 4 is an OR gate, 5 is a power on/off circuit, the one marked V _+IN is the power input terminal, the one marked V _+OUT is the power output terminal, and the one marked CONTROL is the control signal input terminal. When the signal at the terminal is at level "H", the voltage at the V _+IN terminal is output to the V _+OUT terminal. 50 is the + side terminal of the power supply. 6 indicates a voltage drop detection circuit, 60 a comparator, 6
1 is the reference voltage of the comparator 60, and its value
Vref is set below the minimum operating power supply voltage of the microcomputer 1.

Figure 2 is a flowchart showing the background program of a conventional microcomputer.
8 is the start point at the time of reset, 9 is the execution of the initialization program, 10 is the judgment of on/off of power switch 2, 11 is the judgment of power hold/cut, 1
2 represents a step for outputting a power hold signal to the OR gate 4, 13 represents a step for stopping output of the power hold signal to the OR gate 4, and 14 represents execution of a main program for performing targeted information processing and control.

FIG. 3 is a waveform diagram showing the waveforms of various parts of the circuit shown in FIG. 1 during a power-off transition;
Figure A is the voltage at the PORT2 terminal of microcomputer 1, and Figure B is the voltage at the PORT2 terminal of microcomputer 1.
The signal at the PORT1 terminal, C in the figure shows the output signal of the OR gate 4, D in the figure shows the voltage at the power supply terminal Vcc of the microcomputer 1, and E in the figure shows the signal at the terminal of the microcomputer 1. In addition, d1 is the value of the minimum operating power supply voltage of the microcomputer 1,
d2 indicates the value of Vref. Note that the horizontal axis in FIG. 3 is time t.

Assume that the power switch 2 is now in the on position. This state corresponds to the time from t _a to t _b in FIG. 3, and the output of the OR gate 4 is at the "H" level, so the power on/off circuit 5 is in the power output state, and the microcomputer 1 power terminal
The voltage of Vcc is a predetermined operating voltage.

Since Vcc>Vref, the output signal of the comparator 60, that is, the output signal of the microcomputer 1
The input signal to the RESET terminal is at level "H". In the above state, the microcomputer 1 is in operation and is performing the intended information processing and control. (Figure 2 Step 14). At this time, in the flowchart of FIG. 2, steps 14→10→12→14 are repeated, and in step 12, a signal of level "H" is output from the PORT1 terminal to maintain the power supply.

Next, at time t _b in Fig. 3, power switch 2 is turned on.
When the microcomputer 1 is turned off, the flowchart shown in FIG. 2 goes from step 10 to step 11, where it is determined whether to maintain or cut off the power. 14
→10 is repeated, and in step 12 a power hold signal is output. Next, when it is no longer necessary to maintain the power supply at time t _c in FIG.
1 to output a level "L" signal. As a result, the power on/off circuit 5 enters the power off state, but the voltage at the power supply terminal Vcc gradually decreases as shown in FIG. 3D due to the time constant of the power supply circuit in the microcomputer 1. It becomes zero at the time t _f . During this period, Vcc<Vref at time t _e , and the level "L" is applied to the terminal of microcomputer 1.
The microcomputer 1 is reset by the input signal. As is clear from FIG. 3D, although normal operation of the microcomputer 1 is not guaranteed after time t _d , the operation of the microcomputer 1 continues for the period t _{d -te} .

Since the conventional circuit is configured as described above, there is a risk that the microcomputer may malfunction during the period t _d - t _e in Figure 3 when the power is cut off, and a system that stores data in standby RAM is not recommended. The disadvantage of this method was that there was a risk that the data in RAM could be destroyed. To prevent this, it is necessary to set d ₂ > d ₁ in Figure 3D, but normally, in the case of microcomputers using the NMOS process, the value of d ₁ above is equal to the rated value of Vcc.
This is about 95%, and since fluctuations in the power supply voltage are also considered, it has been difficult to set d ₂ > d ₁ .

This invention was made to eliminate the drawbacks of the conventional ones as described above, and instead of the conventional voltage drop detection circuit, a watchdog (watchdog) is used instead of the conventional voltage drop detection circuit.
By using the watchdog circuit to output a reset signal from the watchdog circuit when the power is cut off, and cutting off the power while maintaining the reset state of the microcomputer, malfunctions of the microcomputer will not occur during the transition of the power cut. The purpose of the present invention is to provide a microcomputer system that does the following.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 4 is a block diagram showing an embodiment of the present invention, in which the same reference numerals as in FIG. 1 indicate the same or corresponding parts, and the part marked PORT3 of the microcomputer 1 is used to detect an abnormality in the operation of the microcomputer 1. This is a signal output terminal that outputs an abnormality detection and determination signal (referred to as a determination signal in this specification) that can be used to detect an abnormality. 15 is a watchdog circuit,
The terminals marked with IN are signal input terminals for inputting a determination signal, and the terminals marked with IN are signal output terminals for outputting a negative direction pulse of a predetermined width at a predetermined period when an abnormality in the microcomputer 1 is detected. Note that the power source of the watchdog circuit 15 is configured such that the power source is maintained until the voltage of the power source terminal Vcc reaches OV when the power source of the microcomputer 1 is cut off.

FIG. 5 is a flowchart showing the background program of the microcomputer of the present invention, in which the same reference numerals as in FIG. is a step in which the output of the judgment signal to the watchdog circuit 15 is stopped.

Furthermore, FIG. 6 is a waveform diagram showing signal waveforms of each part of the circuit in FIG. 4, and FIG. 6 A, B, C, and D are signals corresponding to FIG. Diagram E
corresponds to Fig. 3E, and the microcomputer 1
This is an input signal to the RESET terminal, and FIG. 6F represents an output determination signal from the PORT3 terminal of the microcomputer 1. The horizontal axis in FIG. 6 is time t.

While the power switch 2 is in the on position (Fig.
t _a -t _b ), a predetermined voltage is applied to the power supply terminal Vcc of the microcomputer 1, similar to the conventional circuit. At this time, if the microcomputer is operating normally, the flowchart in Figure 5 shows that the microcomputer is operating normally.
Steps 10 → 16 → 14 → 12 → 10 are repeated, and in step 12, the power hold signal of level "H" is
It is output from the PORT1 terminal, and the watchdog circuit 1 is output from the PORT3 terminal in step 16.
A predetermined determination signal is output to the terminal 5. for example,
In the watchdog circuit 15, the period t _a − of FIG.
A signal shown at _tb is input, and the output signal of the terminal is maintained at level "H", assuming that the operation of the microcomputer 1 is normal. Further, if the microcomputer 1 is not in a normal operating state and a predetermined signal is not input to the watchdog circuit 15, a reset signal is output from the terminal and the microcomputer is reset.

Next, when the power switch 2 is turned off, the program enters step 10→11 in FIG.
→11→16→14→12→10 steps are repeated.
When the point _tg in Figure 6 is reached, it is determined in step 11 in Figure 5 that there is no need to maintain the power supply, and step 17 is reached.
The determination signal output to the watchdog circuit 15 is stopped. Therefore, at the time t _h , the output of the terminal of the watchdog circuit 15 is at the level "L".
As a result, the microcomputer 1 enters a reset state. At this time, the PORT1 terminal is in a high impedance state, and the voltage level of that terminal is set to the level "L" by the pull-down resistor 3a.
The power is cut off in the power on/off circuit 5,
The voltage at the power supply terminal Vcc decreases as shown at t _h -t _i in FIG. 6D.

In addition, although the above embodiment uses a microcomputer whose output terminal takes a high impedance state in the reset state, at the time of reset the terminal output is at the level "H" or "L".
It can also be constructed using a microcomputer that has been determined for either one. Further, even if the watchdog circuit 15 is configured to be supplied with power regardless of whether the power to the microcomputer 1 is maintained or cut off, the same effect as in the above embodiment can be obtained.

As described above, according to the present invention, a watchdog circuit is used instead of the conventional voltage drop detection circuit, and when the power is cut off, the watchdog circuit outputs a reset signal, and the power is turned on while the microcomputer remains in the reset state. Since the power is cut off, it is possible to reliably prevent the microcomputer from malfunctioning when the power is cut off.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional system, Fig. 2 is a flowchart showing a background program of the system shown in Fig. 1, Fig. 3 is a waveform diagram showing signal waveforms of each part of Fig. 1, and Fig. 4 5 is a flowchart showing a background program of the system of FIG. 4, and FIG. 6 is a waveform diagram showing signal waveforms of various parts of FIG. 4. 1... Microcomputer, 2... Power switch, 4... OR gate, 5... Power on/off circuit, 15... Watchdog circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] 1 A microcomputer, a power switch for inputting an on/off signal to the microcomputer, a power hold signal output terminal for outputting a power hold signal indicating whether or not to hold the power to the microcomputer, and this power hold signal. A power on/off circuit that controls the on/off of power to the power terminal of the microcomputer by means of an OR signal with the on/off signal from the power switch, and a power on/off circuit that controls whether or not the microcomputer is operating normally. A watchdog circuit receives a determination signal from the microcomputer, and when the watchdog circuit determines that the microcomputer is not operating normally or detects the absence of the determination signal. means for resetting the microcomputer, and determining whether or not it is necessary to maintain power in the microcomputer after the on/off signal from the power switch indicates the off state;
A means for stopping the sending of the determination signal after it is determined that the power supply is not required to be maintained, and a logic that indicates that the power supply retention signal is not required to be maintained in the reset state of the microcomputer is provided. a microcomputer system comprising means for configuring settings;