JP2008090592A - Electronic device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To solve a problem that a state of the power control means just before a reset operation by a control means cannot be maintained after the reset operation and that a user is required to turn on power again at every time of the reset operation. <P>SOLUTION: An electronic device comprises a retention means, driven by a second power supply different from a first power supply upon a reset operation by the control means, for retaining the state of the power control means just before the reset operation by the control means. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to an electronic device, and more particularly to an electronic device having a CPU that can be reset.

  The configuration of the digital camera according to the conventional example will be described with reference to FIG. Reference numeral 1 denotes a CPU that controls the entire digital camera. Reference numeral 2 denotes a ROM in which a program for operating the CPU 1 is recorded. Reference numeral 3 denotes a working memory RAM that temporarily stores captured image data or temporarily stores data necessary for the operation of the CPU 1. Reference numeral 4 denotes a power supply control unit, which generates necessary voltages for each part of the digital camera from the voltage of the power supply 5 and supplies power to each part.

  A power switch 6 is connected to the power supply control unit 4 and the CPU 1. A logic circuit unit 7 receives an output signal from the power switch 6 and an output signal from the CPU 1, outputs a logical sum of these two input signals to the power supply control unit 4, and controls activation and operation stop of the power supply control unit 4. is there. The power switch 6 is closed when pressed by the user. Then, an output signal of the power switch 6 is input to the CPU 1 and also input to the power supply control unit 4 via the logic circuit unit 7, and the power supply control unit 4 is activated.

  Further, the CPU 1 recognizes the first output signal from the power switch 6, outputs a control signal to the power supply control unit 4 via the logic circuit 7, and holds the operation state of the power supply control unit 4.

  When the power switch 6 is pressed again and an output signal is input to the CPU 1, the CPU 1 recognizes the second output signal from the power switch 6. When the second output signal is recognized, the control signal output to the power control unit 4 via the logic circuit 7 is stopped, the operation of the power control unit 4 is stopped, and the power of the digital camera is turned off.

  Reference numeral 8 denotes a reset IC for resetting the CPU 1. The CPU 1 includes a lens driving unit, an image stabilization control unit (IS), an imaging unit including an imaging device and a timing generator, an image display unit including an LCD, an audio control unit including a microphone and a speaker, and peripheral devices such as a recording medium. 9 is connected. The peripheral devices such as the lens driving unit to the recording medium are configured to be controlled by the CPU 1 and perform a target process, and are connected by communication means so that the CPU can detect each state.

It is also known to detect the occurrence of an error that cannot be processed continuously by the CPU, and individually reset necessary elements of the entire system or individual elements other than the CPU according to the type of detected error. ing. (See Patent Document 1)
Further, it is also known that when a reset operation is required during system operation, a reset signal is output from reset signal output means provided in the control means, and the system reset operation is performed. (See Patent Document 2)
JP-A-6-230993 JP-A-9-44201

  In the conventional example of FIG. 9, when communication is not returned from the peripheral device 9 to the CPU 1 or an abnormal value is returned, the CPU 1 detects an error in the peripheral device. When the CPU 1 detects an error in the peripheral device, the CPU 1 forcibly terminates the access, performs predetermined error processing, displays an error via the image display unit, and then performs an internal reset operation. In this case, in the configuration as in the conventional example, when the CPU 1 performs an internal reset operation, the operation state of the power supply control unit 4 cannot be maintained, and the power supply as the digital camera is turned off. Therefore, it is necessary to turn the digital camera on again by pressing the operation system 6 again. Therefore, for example, even when a simple error that can be repaired only by resetting the CPU, such as application of static electricity, has occurred, the user has to turn the digital camera on again.

  The present invention is intended to solve such a problem, and even when the CPU detects an error of a peripheral device, if the error is repaired by the reset operation of the CPU, the electronic device does not require the user to turn on the power again. The purpose is to provide.

  In order to achieve the above object, the present invention controls a first power source, a second power source different from the first power source, a power source control unit for controlling the first power source, and the power source control unit. And a holding unit that is driven by the second power source and holds the state of the power control unit immediately before the reset operation of the control unit when the control unit performs a reset operation. It is characterized by.

  Even if the control means performs a reset operation, the state of the power supply control means immediately before the reset operation can be maintained, so that it is possible to provide an electronic device that does not need to be turned on again at every reset operation. .

  Embodiments of the present invention will be described below with reference to the drawings.

  FIG. 1 shows the configuration of a digital camera according to the present invention.

  The CPU 1 is a central processing unit that controls the entire digital camera. The CPU 1 controls the control operation of the power supply to each unit, the detection operation of the input of the operation key in the operation unit 6, and the operation of each unit of the digital camera based on the input of the operation key.

  Reference numeral 2 denotes a ROM in which a program for operating the CPU 1 is recorded. Reference numeral 3 denotes a working memory RAM that temporarily stores captured image data or temporarily stores data necessary for the operation of the CPU 1.

  A power control unit 4 is connected to the power source 5 and includes a power detection circuit, a DC-DC converter, a switch circuit that switches blocks to be energized, and the like. Based on the control of the CPU 1, the power supply control unit 4 generates necessary voltages for each unit of the digital camera from the voltage of the power supply 5, and supplies power to each unit for a necessary period.

  Reference numeral 6 denotes an operation system including a power switch, which is connected to the power control unit 4 and the CPU 1. The power of the camera is turned on / off by turning on / off the power switch 6.

  Reference numeral 10 denotes an auxiliary power source, which is composed of a coin battery or the like, and supplies power to a reset auxiliary block that must be constantly supplied when no power is supplied from the main power source 5. When the auxiliary power source 10 is a secondary battery, the auxiliary power source 10 may be charged when the power from the main power source 5 is supplied.

  The main power source 5 includes a primary battery such as an alkaline battery or a lithium battery, a secondary battery such as a NiCd battery, a NiMH battery, or a Li battery, an AC adapter, or the like.

  Since the reset auxiliary block 8 is connected to the main power supply 5 and the auxiliary power supply 10, power is always supplied from the auxiliary power supply 10 even when the camera body is turned off.

  The reset auxiliary block 8 is communicatively connected to the CPU 1 through an SPI signal line. In addition, the reset auxiliary block 8 is connected to the output of the general-purpose port (ResetDET) to the CPU 1 and to the power supply control unit 4 via the logic circuit unit 7. With the above configuration, the activation and stop of the power supply control unit 4 are controlled by communication from the CPU 1. Since the reset auxiliary block 8 is supplied with power from the auxiliary power supply 10 even when the camera power is off, the output polarity of the general-purpose port for power control can be maintained.

  The logic circuit unit 7 is connected to the CPU 1 on the input side, the reset auxiliary block 8, and the output of the operation system 6, and the output side is connected to the power supply control unit 4. Controls start-up, operation stop, and operation holding of the unit 4.

  The CPU 1 includes a lens driving unit, an image stabilization control unit (IS), an imaging unit including an imaging device and a timing generator, an image display unit including an LCD, an audio control unit including a microphone and a speaker, and peripheral devices such as a recording medium. 9 is connected.

  The peripheral devices such as the lens driving unit to the recording medium are configured to be controlled by the CPU 1 and perform a target process, and are connected by communication means so that the CPU can detect each state.

  Note that SPI is a serial communication line, DET is a drive power supply detection line, CLK is a drive clock line, DATA is a data line, READY is a response signal line from a peripheral device, and / RESET is a reset line. Although the above signal group is an example, it is a signal group that controls a peripheral device control / drive system.

  Next, the configuration of the auxiliary reset block according to the present embodiment will be described with reference to FIG.

  In this embodiment, the function of the reset auxiliary block 8 described above is configured by RTC (Real Time Clock).

  The reset auxiliary block 8 is a time management means for managing the time inside the digital camera, but has a general-purpose port, and the CPU 1 can control the general-purpose port of the RTC via serial communication.

  FIG. 4 is a block diagram showing the configuration of the reset auxiliary block 8. In FIG. 4, the reset auxiliary block 8 includes a controller 13, a timer 14, a register 15, a bus interface 16, an internal bus 17, and a clock supply unit 18.

  The controller 13 controls the entire reset auxiliary block 8 and determines the control of the entire reset auxiliary block 8 based on the set value stored in the register 15.

  The register 15 is configured to be readable / writable from the CPU 1 via the bus interface 17. Thereby, the CPU 1 can control the reset auxiliary block 8. Since the reset auxiliary block 8 is also connected to the auxiliary power supply 10, it can be driven even when no power is supplied from the main power supply 5.

  Thus, when the control content from the CPU 1 is written to the register 15, even if the main power supply 5 is disconnected and the CPU stops, the reset auxiliary block 8 continues to be executed until the CPU is activated again to release the control content. .

  Next, the configuration of the logic circuit unit of this embodiment will be described with reference to FIG.

  In this embodiment, the function of the logic circuit unit described above may be realized by a diode. A pair of diodes is connected in parallel to the number of input signals, and the logical sum of the signals from the CPU 1, the reset auxiliary block 8, and the operation system 6 is input to the power supply control unit 4.

  If any one of the output signals from the CPU 1, the reset auxiliary block 8, and the operation system 6 is at a high level, the output as a logic circuit is also at a high level.

  Next, the operation of each block in the present embodiment will be described with reference to FIGS. 1, 3, and 5 to 7. FIG. FIG. 1 shows the configuration of an embodiment of a digital camera according to the present invention. FIG. 3 shows the operation timing of the embodiment of the digital camera according to the present invention. FIG. 5 shows the error detection operation of the peripheral device of the embodiment of the digital camera according to the present invention. FIG. 6 shows a communication operation between the CPU and the reset auxiliary block in the embodiment of the digital camera of the present invention. FIG. 7 shows the operation of signals input to the logic circuit of the embodiment of the digital camera according to the present invention.

  The peripheral device is connected to the CPU 1 through SPI, DET, CLK, DATA, READY, and / RESET, and is controlled by the CPU 1 to perform a target process and detect an error. An example of error detection will be described with reference to FIG.

  The peripheral device changes the Ready signal from High to Low at a period of Tx. The CPU detects that the Ready signal has changed from High to Low and sends 1 byte of Clk. The peripheral device detects that 1-byte CLK has been sent from the CPU, and changes the Ready signal from Low to High.

  Normally, such control is repeated. However, when the peripheral device freezes due to a problem such as static electricity and the Ready signal cannot be controlled, the CPU detects the Ready signal and returns an error.

  After detecting an error at T1, the CPU changes the / RESET signal from High to Low at T2 to reset the peripheral device. Then, the above-described communication is performed again at T3.

  The reset auxiliary block 8 is connected to the CPU 1 through the SPI, and controls a general-purpose port (RESET_DET signal) connected to the power supply control unit via the logic circuit unit. If the CPU detects an error again after communicating with the error target device at T3, it starts communication with the reset auxiliary block at T4. At T5, CS changes from Low to High level and the general-purpose port (RESET_DET signal) changes to High level. Determine.

  The output signals from the CPU 1, the reset auxiliary block 8, and the operation system 6, respectively, the E1LAT signal, the Reset_DET signal, and the Power_DET signal are input to the power supply control unit through the logic circuit unit, and are activated at the high level and stopped at the low level. Control.

  The Reset_DET signal is connected from the logic circuit unit to the CPU, and detects the Reset_DET state. The CPU detects that the Reset_DET signal has become high level at T6, confirms that the operating state of the power supply control unit is maintained, and then internally resets the entire system at T7. The CPU cannot maintain the polarity of E1_LAT due to the internal reset, and E1_LAT is changed from the High level to the Low level at T8.

  As shown in FIG. 7, due to the configuration of the logic circuit portion, even if C E1_DET becomes Low level, B Reset_DET is held at High level, so the output D of the logic circuit portion is held at High level, and the power supply The operation state of the control unit is maintained.

  The CPU sets E1LAT, which has become Low level due to system internal reset at T9, to High level, and maintains the operation state of the power supply control unit. At T10, it is detected that the Reset_DET signal is at a high level. At T11, communication with the reset auxiliary block is started. At T12, CS is changed from low to high level, and the RESET_DET signal is fixed at low level. At T13, the CPU communicates with the peripheral device to start an error check. If a communication error is not detected at T15, normal activation is started from T16.

  Next, an operation sequence will be described with reference to FIG. FIG. 2 shows an operation sequence of this embodiment.

  When the CPU 1 communicates with the peripheral device 9, or performs a reset operation (S101). At this time, DET did not reach a predetermined level and the power supply voltage of the peripheral device could not be detected, or a response signal such as READY did not return for a predetermined time, or an output value such as DATA returned an abnormal value Is confirmed (S102). In such a case, the CPU 1 recognizes an error in the peripheral device, sets / Reset to Low, and resets the error target device (S103).

  Communication with the error target device is performed again, and if the response signal is returned within a predetermined time and the output value is also a normal value, the error target device continues the normal operation sequence (S105).

  Conversely, if no response signal is returned within a predetermined time or if the output value returns an abnormal value, the CPU 1 communicates with the reset auxiliary block 8 via the SPI (S106). Then, in response to communication from the CPU, the reset auxiliary block 8 sets Reset_DET to High for the logic circuit 7 to hold the operation state of the power supply control unit 4, and also outputs High to the CPU 1 (S107).

  The CPU 1 receives the Reset_DET High output from the reset auxiliary block 8 and recognizes that the operation state of the power supply control unit 4 is held (S108). Then, the entire system is internally reset (S109).

  Since E1LAT becomes Low due to the reset operation and the power supply operation holding from the CPU is once released, after the CPU is activated, E1LAT is set to High again to hold the operation state of the power supply control unit 4 (S110). Thereafter, the output of ResetDET is detected to confirm that the activation factor of the camera is a reset auxiliary block factor (S111), and an error repair sequence is entered.

  Thereafter, the reset auxiliary block 8 communicates with the SPI (S112), and the reset auxiliary block 8 receives the communication from the CPU and switches the Reset_DET output for the logic circuit 7 from High to Low, and maintains the operation state of the power supply control unit 4. Release (S113).

  The CPU communicates after resetting the error target device by setting / Reset to Low (S114) (S115). At this time, if an error occurs, such as when the power supply voltage could not be detected or the response signal did not return for a specified time, or the output value returned an abnormal value, the error target block and error details The error check list is created (S117). The created error checklist ROM is recorded (S118), and the camera is shut down (S119). If no error has occurred, each device is normally activated (S116).

  In this embodiment, RTC (Real Time Clock) is adopted as the reset auxiliary block, but a simple DQ flip-flop may be used. A block diagram in that case is shown in FIG.

  In the figure, 80 is a DQ flip-flop configuration instead of the RTC example. When the CPU 1 inputs CLK and Low → High output to the DQ flip-flop 80 to the CLK terminal and the D terminal, respectively, the output of the Q terminal is switched from Low to High. Therefore, the operation state of the power supply control unit 4 is maintained, and the power supply of the digital camera is maintained in the ON state.

  Further, the output of the Q terminal is switched from High to Low, and the CPU 1 recognizes the activation factor. Therefore, the polarity is maintained even when the CPU is shut down. If the CPU 1 again inputs CLK and High → Low output to the DQ flip-flop 80 to the CLK terminal and D terminal, respectively, the output of the Q terminal is switched from High to Low, and the power supply from the DQ flip-flop 80 is released. . On the other hand, the output of the Q terminal is switched from Low to High, and the activation factor returns to normal.

  As described above, even when the CPU detects an error in the peripheral device, the user does not need to turn the camera on again if the error is corrected by the reset operation.

It is a figure which shows the structure of the digital camera which is embodiment in this invention. It is a figure which shows the operation | movement sequence of the digital camera which is embodiment in this invention. It is a figure which shows the operation timing of the digital camera which is embodiment in this invention. It is a figure which shows the structure of the reset auxiliary block of the digital camera which is embodiment in this invention. It is a figure which shows the error detection operation | movement of the peripheral device of the digital camera which is embodiment in this invention. It is a figure which shows communication operation | movement with CPU of a digital camera which is embodiment in this invention, and a reset auxiliary block. It is a figure which shows operation | movement of the signal input into the logic circuit of the digital camera which is embodiment in this invention. It is a figure which shows the structure at the time of DQ flip-flop use of the digital camera which is embodiment in this invention. It is a figure which shows the structure of the digital camera which is a prior art example.

Explanation of symbols

1 CPU
4 Power Control Unit 5 Main Power Supply 6 Power Switch 8 Reset Auxiliary Block 10 Auxiliary Power Supply

Claims (3)

A first power source;
A second power source different from the first power source;
Power control means for controlling the first power;
Control means for controlling the power supply control means;
And a holding unit that is driven by the second power source when the control unit performs a reset operation and holds the state of the power source control unit immediately before the reset operation of the control unit. machine.   The power supply control unit performs control to turn on / off the energization of the first power supply, and the holding unit is configured so that the power supply control unit is connected to the first power supply immediately before a reset operation of the control unit. The electronic apparatus according to claim 1, wherein whether or not energization is turned on is held.   The electronic device according to claim 1, wherein the holding unit is a DQ flip-flop circuit.

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