JP2747011B2 - Interrupt signal interface - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface of an interrupt signal, and more particularly to an interrupt signal interface for connecting an existing board which is a rising edge active interrupt to a low active interrupt line. Ace.

[Conventional technology]

In the conventional interrupt interface, an interrupt request signal is connected to a bus via an open collector buffer.

[Problems to be solved by the invention]

In the conventional interrupt interface described above, since the interrupt signal from each device is connected through an open collector buffer, if an attempt is made to connect an existing board of rising edge active interrupt to a low level active interrupt line, Some existing edge-active interrupt boards output a high level while others are not operating and output a low level.If a low-level output is connected, a low-level active interrupt is generated. When is working,
There was a problem that it malfunctioned as if an interrupt occurred even though there was no interrupt.

[Means for solving the problem]

An interrupt signal interface according to the present invention includes a pull-up resistor for pulling up an interrupt input, an edge detecting circuit for detecting a rising edge of the interrupt input, a delay circuit for delaying the interrupt input, and an output of the delay circuit as an input. It has a three-state buffer controlled by the output of the edge detection circuit.

[Action]

In the present invention, in the initial state, the interrupt output is disconnected from the bus, and the interrupt output is connected to the bus only by detecting the rising edge of the edge-active interrupt.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

 FIG. 1 is a block diagram showing one embodiment of the present invention.

In the figure, reference numeral 1 denotes an interrupt input which is an interrupt request input from an interrupt device, and 2 denotes an edge detection circuit for detecting a rising edge of the interrupt input 1.
Is constituted by a D-type flip-flop with reset. The D (data) input 21 of the edge detection circuit 2 is fixed at a high level, and the R (reset) input 23 is connected to the system reset input 5. And interrupt input 1
Is connected to the C (clock) input 22 of the edge detection circuit 2, whereby the edge detection circuit 2 detects the rising edge of the interrupt input 1.

3 is a delay circuit for delaying the interrupt input 1, 4 is a three-state buffer which receives the output of the delay circuit 3 as input, and is controlled by the output of the edge detection circuit 2, 6 is a pull-up resistor for pulling up the interrupt input, and 7 is an interrupt. Output.

The Q output 24 of the edge detection circuit 2 is connected to the control input of the three-state buffer 4, and the interrupt input 1 is also input to the three-state buffer 4 through the delay circuit 3. The output of the three-state buffer 4 becomes an interrupt output 7, which is connected to an interrupt line on the bus. The pull-up resistor 6 connected to the interrupt input 1 prevents the state of the interrupt input 1 from becoming unstable when nothing is connected to the interrupt input 1.

2 and 3 are time charts showing an operation example of the present invention. In FIG. 2, interrupt input 1 is normally at a high level.
FIG. 3 shows an operation example in the case of a type in which a low-level pulse is issued at the time of an interrupt request.
It shows an operation example in the case of a type in which a high level is held until an interrupt is accepted.

In FIG. 2, reference numeral 80 denotes a reset period, 81 denotes a non-operation period, 82 denotes an interrupt active period, 83 denotes an interrupt inactive period, and 84 denotes a delay time. In FIG. 3, reference numeral 90 denotes a reset period, 91 denotes a non-operating period, and 92 denotes an interrupt active period.

Next, the operation of the embodiment shown in FIG. 1 will be described with reference to FIGS.
(E) and FIGS. 3 (a) to (e).

First, during the reset periods 80 and 90, the system reset input 5 becomes active, the edge detection circuit 2 is reset, and as a result, the output of the three-state buffer 4 becomes a high impedance state, and the interrupt output 7 is disconnected from the bus. Therefore, when the low-level active interrupt is operating, the interrupt output of the rising edge active interrupt has no effect.

Next, the non-operation periods 81 and 91 do not operate because the rising edge active interrupt device is not programmed. The interrupt input 1 is activated by the system programming the edge active interrupt device. This is the interrupt active period 8
2,92.

In the case of FIG. 2, at the moment when the interrupt inactive period 83 is reached, the edge detection circuit 2 operates, the three-state buffer 4 is turned on, and the interrupt is connected to the bus. Since the interrupt output 7 is pulled up, it is at a high level when the three-state buffer 4 is off, so that when the three-state buffer 4 directly drives the interrupt input 1, a rising edge occurs in the interrupt output 7. The three-state buffer 4 is not
Drive the output of

In the case of FIG. 3, the edge detection circuit 2 operates at the moment when the interrupt active period 92 is reached, and the three-state buffer 4 is activated.
Turns on and connects the interrupt to the bus. Since the interrupt output 7 is pulled up, it is at a high level when the three-state buffer 4 is off, so that when the three-state buffer 4 directly drives the interrupt input 1, a rising edge occurs in the interrupt output 7. Therefore, the three-state buffer 4 drives the output of the delay circuit 3.

The delay time 84 may be longer than the minimum time of the low-level pulse time of the interrupt input of the interrupt controller such as Intel's 8259, for example.

In both cases of FIG. 2 and FIG.
Detects an edge, the interrupt output 7 remains connected to the bus until the system reset input 5 becomes active. This is because the integration of the interrupt board into the system is generally determined when the system is started up, and the state of installation is not frequently changed during operation.

However, if it is necessary to change the built-in state during operation, the R (reset) input 23 of the edge detection circuit 2
A signal obtained by performing a logical sum (OR) of the signal generated by the system reset input 5 and the command may be input.

〔The invention's effect〕

As described above, according to the present invention, in the initial state, the interrupt output is disconnected from the bus, and the interrupt output is connected to the bus only by detecting the edge active interrupt rising edge. -Normal operation can be performed even if an existing board with active interrupt is connected.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are time charts showing an operation example of the present invention. 1 ... interrupt input, 2 ... edge detection circuit, 3 ... delay circuit, 4 ... three-state buffer, 5 ... system reset input, 6 ... pull-up resistor, 7 ... interrupt output.

Claims (1)

(57) [Claims] A pull-up resistor for pulling up an interrupt input; an edge detecting circuit for detecting a rising edge of the interrupt input; a delay circuit for delaying the interrupt input; an output of the delay circuit as an input; An interrupt signal interface having a three-state buffer controlled by an output of the interrupt signal.