JP3630877B2 - Interface circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an interface circuit for connecting a plurality of systems, and more particularly to an interface circuit that is less likely to cause malfunctions such as malfunction even at low cost.
[0002]
[Prior art]
In recent years, attempts have been made to reduce power consumption of system devices from the viewpoint of energy saving. For example, in a multi-function device, when not in use, the copy unit (main system) is generally turned off and the facsimile unit (subsystem) is kept on.
[0003]
By the way, when there are an active part with the power turned on and an inactive part with the power turned off, it is necessary to devise an interface unit that connects the main system and the subsystem. For example, logic signal matching is performed between the main system and the subsystem, and malfunctions during an indefinite period between state transitions and a reset period are prevented. Conventionally, these have been performed using an open collector semiconductor or an optical element.
[0004]
[Problems to be solved by the invention]
However, an open collector semiconductor requires a power signal line and increases the number of interface signal lines. For this reason, there existed a problem that cost became high. Further, the optical element has a problem that the optical element itself and its connector are expensive, and the cost is increased as a whole. On the other hand, when an interface circuit is configured with inexpensive elements, there is a problem that malfunction such as malfunction may occur.
[0005]
The present invention has been made in view of the above, and an object of the present invention is to provide an interface circuit that is less likely to cause malfunctions such as malfunction even at low cost.
[0006]
[Means for Solving the Problems]
In order to achieve the above object, an interface circuit according to claim 1 is a level of detecting whether or not the level of a logic power supply in each system has risen to an effective level in an interface circuit connecting a plurality of systems. A detection means, a program abnormality detection means for detecting a program abnormality of one of the plurality of systems, a detection result of the level detection means and a detection result of the program abnormality detection means. Gate means for opening and closing the gate based on a soft reset , the gate means in a state where the level of the logic power supply has risen to an effective level in all systems based on the detection result of the level detection means , Program abnormality detection by means of program abnormality detection It is to close the gate when detecting the soft reset period is performed from fruit.
[0007]
For example, if the gate is opened when the level of the logic power supply of one system is not yet at an effective level, a malfunction such as not accepting a request for any operation to the system occurs. Therefore, the gate is opened only when the logic power supply level of each system is at an effective level. In this way, each system operates reliably, so that malfunctions such as malfunctions can be prevented.
[0013]
In addition , the system does not accept a request at the time of a software reset such as a program error. Therefore, problems such as malfunctions can be prevented.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, the present invention will be described in detail with reference to the drawings. In addition, this invention is not limited at all by this embodiment.
[0015]
(Embodiment 1)
First, a first embodiment according to the present invention will be described. FIG. 1 is a block diagram showing a configuration of a system apparatus using an interface circuit according to this embodiment. The system apparatus 1000 includes a main system 1 and a subsystem 2. The main system 1 and the subsystem 2 are respectively supplied with power from an AC power source 3.
[0016]
The AC power supply 3 is connected to a PSU (Power Supply Unit: power supply unit) 4 provided in the main system 1. The logic DC voltage and other voltages from the AC power supply 3 are supplied to each part of the main system 1 via the PSU 4. The AC power source 3 is also connected to the PSU 5 equipped in the subsystem 2. Similarly to the above, the logic DC voltage and other voltages from the AC power supply 3 are supplied to each part of the subsystem 2 via the PSU 5.
[0017]
Further, the subsystem 2 is equipped with an I / F gate circuit 100. Through this I / F gate circuit 100, the main system 1 and the subsystem 2 are connected to form gate means. Here, 6 represents an address bus, 7 represents a data bus, and 8 represents various system control signals.
[0018]
FIG. 2 is a circuit diagram showing the I / F gate circuit 100 of the subsystem. This I / F gate circuit 100 employs a configuration in which three-state buffers 101 to 103. For example, the address bus signal 6 from the main system 1 is input from the 3-state buffer 101, the data bus input signal is input from the 3-state buffer 102, and various system control signals are input from the 3-state buffer 103 to the subsystem 2. The I / F gate circuit 100 includes a gate circuit 10 (described later), and a gate control signal is input from the gate circuit 10.
[0019]
FIG. 3 is a circuit diagram showing the gate circuit 10 for generating the gate control signal. In the gate circuit 10, the AND gate 11 receives a power-on reset signal (−PmRES) from the main system side and a power-on reset signal (−PsRES) from the subsystem side. The power-on reset signal is output by a general-purpose voltage detection IC (not shown) provided in both the main system 1 and the subsystem 2. Further, the gate circuit 10 and a CPU (not shown) detect whether or not the levels of the logic power supply in the main system 1 and the subsystem 2 are both high levels (effective levels).
[0020]
FIG. 4 shows a timing chart of each signal. As shown in FIG. 4A, when the main system power supply is turned on, the voltage gradually rises and reaches a predetermined logic voltage (4.5 V). Then, as shown in FIG. 4B, a high-level power-on reset signal (-PmRES) is output. On the other hand, when the voltage does not reach the predetermined logic voltage (4.5 V), a low-level power-on reset signal (-PmRES) is output.
[0021]
Next, even when the power supply on the subsystem side is turned on, the voltage gradually rises and reaches a predetermined logic voltage (4.5 V) as shown in FIG. Then, as shown in FIG. 4D, a high-level power-on reset signal (-PsRES) is output. On the other hand, when the voltage does not reach the predetermined logic voltage (4.5 V), a low-level power-on reset signal (-PsRES) is output.
[0022]
Subsequently, the power-on reset signal (-PmRES) on the main system side and the power-on reset signal (-PsRES) on the subsystem side are input to the gate circuit 10 having the AND gate 11. When both signals are at a high level, the main system 1 and the subsystem 2 are at an effective level, so that a gate control signal GATCON1 is generated as shown in FIG. Subsequently, in response to the gate control signal GATCON1, the CPU opens the I / F gate circuit 100 ((f) in FIG. 4).
[0023]
As described above, since the gate is opened only during the effective period of the power supply voltage of the main system 1 and the subsystem 2, problems such as malfunction do not occur. In addition, since the gate circuit 10 is configured using the AND gate 11 or the like, the I / F gate circuit 100 is inexpensive. This is particularly effective when the AC power source 3 is an inexpensive power source having a large CR constant.
[0024]
Further, as shown in FIG. 5, even when there is a momentary interruption in the AC power supply 3, the logical product of the power-on reset signal (-PmRES) and the power-on reset signal (-PsRES) is taken, and the momentary interruption period is The I / F gate circuit 100 is closed. For this reason, malfunctions, such as malfunctioning in the momentary interruption period of AC power supply 3, can also be prevented.
[0025]
(Embodiment 2)
Next, a second embodiment will be described. The configuration of the second embodiment is characterized in that the gate circuit 20 for generating the gate control signal is composed of a three-state buffer 21 and a pull-up resistor 22 provided on the gate control signal side.
[0026]
FIG. 6 is a circuit diagram showing a configuration of the gate circuit 20. In the gate circuit 20, the power-on reset signal (−PmRES) on the main system side is input from the data input side of the three-state buffer 21. Further, the power-on reset signal (−PsRES) on the subsystem side is input from the control input side of the three-state buffer 21. Further, the gate circuit 20 and a CPU (not shown) detect whether or not the levels of the logic power supply in the main system 1 and the subsystem 2 are both high levels (effective levels).
[0027]
FIG. 7 shows a timing chart of each signal. As shown in FIG. 7A, when the power supply on the main system side is turned on, a high level power-on reset signal (-PmRES) is output as shown in FIG. 7B. Further, as shown in FIG. 7C, when the power supply on the subsystem side is turned on, as shown in FIG. 7D, a high-level power-on reset signal (-PsRES) is output. .
[0028]
Subsequently, the power-on reset signal (-PmRES) on the main system side and the power-on reset signal (-PsRES) on the subsystem side are input to the three-state buffer 21. In this case, the gate control signal GATCON2 output from the 3-state buffer 21 is in a high impedance state (61, 61) during the rise and fall periods of the subsystem, as shown in FIG. However, since the gate control signal GATCON2 is held at a high level even while the power supply voltage of the IC is raised by the pull-up resistor 22, as shown in FIG. 7 (f) even in the high impedance period (a1, a2). At the same time, the I / F gate circuit 100 is opened.
[0029]
As described above, even during a transition period of the power supply voltage, a logical interface can be established by performing voltage conversion with the main system 1. For this reason, the interface valid period can be extended (a1, a2). In addition, an inexpensive power supply unit with a large CR constant is particularly effective because it takes a long time until the power-on reset signal becomes High after the power supply starts.
[0030]
Alternatively, the subsystem side may be started first, and then the main system may be started. FIG. 8 shows a timing chart of each signal.
[0031]
First, as shown in FIGS. 8A to 8D, when the subsystem side is raised first, the gate control signal GATCON2 output from the gate circuit 20 becomes as shown in FIG. 8E. Therefore, the open period of the I / F gate circuit is as shown in FIG. However, in the circuit configuration of the first embodiment, when the subsystem side is started up first and then the main system side is started up, the gate control signal GATCON1 ′ output from the gate circuit 10 is shown in FIG. become that way. Therefore, the open period of the I / F gate circuit 100 is as shown in FIG.
[0032]
In this manner, when the main system side is started up after the subsystem side is set up first, in the configuration according to the first embodiment, the gate is opened when the gate should not be opened (x1). X2), inadvertent access from the subsystem occurs. However, in the configuration of the second embodiment, an appropriate interface valid period can be acquired ((f) in FIG. 8), so that inadvertent access from the subsystem is not allowed. Have further advantages.
[0033]
Further, as shown in FIG. 9, even when the AC power supply 3 has an instantaneous interruption, the I / F gate circuit 100 is closed. For this reason, malfunctions, such as a malfunctioning in the momentary interruption period of AC power supply 3, can be prevented.
[0034]
(Embodiment 3)
Next, a third embodiment will be described. FIG. 10 is a circuit diagram showing a gate circuit 30 for generating a gate control signal according to the third embodiment. In the third embodiment, the gate circuit 30 is configured using a 3-input AND gate 31. In order to avoid program abnormality, a watchdog circuit is provided on the main system side (not shown).
[0035]
The three-input AND gate 31 has a power-on reset signal (-PmRES) from the main system side, a soft reset signal (-SmRES) from the main system side, and a power-on reset signal (-PsRES from the subsystem side). ) And are input.
[0036]
FIGS. 11A to 11G show timing charts of the respective signals. Thus, the gate control signal GATCON3 is generated and the I / F gate circuit 100 is opened only when the soft reset signal (-SmRES) from the main system side is High ((c) in FIG. 11) (FIG. 11). 11 (g)).
[0037]
As described above, since the I / F gate circuit 100 is closed during the soft reset period due to a program abnormality or the like ((g) in FIG. 11), the subsystem 2 is not affected by the main system 1. For this reason, problems such as malfunctions do not occur.
[0038]
If the soft reset period is not taken into consideration, that is, if the gate circuit 10 of the first embodiment is left as it is, a gate control signal GATCON 3 ′ as shown in FIG. Since the circuit 10 is open ((i) in FIG. 11), problems are likely to occur.
[0039]
As a modification, a gate circuit 40 may be configured by an AND gate 41, a three-state buffer 42, and a pull-up resistor 43 as shown in FIG. Also by this gate circuit 40, the gate is closed during a soft reset period due to a program abnormality or the like ((j) and (k) in FIG. 11), so that the subsystem 2 is not affected by the main system 1. For this reason, malfunctions such as malfunctions do not occur.
[0040]
【The invention's effect】
As described above, in the interface circuit according to the first aspect, the gate is opened only when the level of the logic power supply of each system is at an effective level. Since it operates, it is possible to prevent malfunctions such as malfunctions.
[0043]
The gate means interface circuit, since the soft reset period such as programs abnormalities so as to close the gate, thereby preventing problems such as malfunction.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a system device using an interface circuit according to a first embodiment of the present invention.
2 is a circuit diagram showing a configuration of an I / F gate circuit provided in the subsystem shown in FIG. 1. FIG.
3 is a circuit diagram showing a configuration of a gate circuit for generating a gate control signal to be sent to the I / F gate circuit shown in FIG. 2;
4 is a timing chart showing the operation timing of each signal in the gate circuit shown in FIG. 3. FIG.
5 is a timing chart showing the operation timing of each signal in the I / F gate circuit when there is a momentary interruption in the AC power source shown in FIG. 1. FIG.
FIG. 6 is a circuit diagram showing a configuration of a gate circuit according to a second embodiment of the present invention.
7 is a timing chart showing the operation timing of each signal in the gate circuit shown in FIG. 6. FIG.
8 is a timing chart showing the operation timing of each signal when the power-on reset signal (−PmRES) and the power-on reset signal (−PsRES) are interchanged in the gate circuit shown in FIG. 6;
9 is a timing chart showing the operation timing of each signal in the gate circuit when there is a momentary interruption in the AC power source shown in FIG. 6;
FIG. 10 is a circuit diagram showing a configuration of a gate circuit according to a third embodiment of the present invention.
11 is a timing chart showing the operation timing of each signal in the gate circuit shown in FIG.
FIG. 12 is a circuit diagram showing a configuration of a gate circuit according to a modification of the third embodiment of the present invention.
[Explanation of symbols]
1000 System unit 1 Main system 2 Subsystem 3 AC power supply 4, 5 PSU
100 I / F gate circuits 101 to 103 3-state buffers 10, 20, 30, 40 Gate circuits 11, 41 AND gate 20 Gate circuits 21, 42 3-state buffers 22, 43 Pull-up resistor 31 3-input AND gate

Claims (1)

In an interface circuit that connects multiple systems,
Level detection means for detecting whether or not the level of the logic power supply in each system has risen to an effective level;
Of the plurality of systems, program abnormality detection means for detecting a program abnormality of one system,
Gate means for opening and closing the gate based on the soft reset of the one system performed based on the detection result of the level detection means and the detection result of the program abnormality detection means ,
The gate means is a soft reset performed based on the detection result of the program abnormality by the program abnormality detection means in a state where the level of the logic power supply rises to an effective level in all systems based on the detection result of the level detection means. Closing the gate when detecting the period
An interface circuit characterized by

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