JPH0364894B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an information processing device controlled by a microprogram, in which a logic device and a transfer device operate with a 1:n bus connection between activation and response. Related to interface control method.

[Conventional technology]

An information processing device that operates with a 1:i bus connection between one logical device and a plurality of transfer devices with an activation-response ratio generally has a system arrangement as shown in FIG. In the figure, 1 is a logical device (CPU), 2 is a startup request bus, and 30 to 3i are i data transfer devices (DCH or CHC). FIG. 3 is a configuration diagram of the interface section of one data transfer device 3.
4 is its own CHC machine number (DCH machine number) 0'~j' and DCH machine number 0 from CPU1 received through machine number bus 5.
-j is an exclusive OR (EOR) gate that detects a match, 6 is an OR gate that collects activation signals 0 to k from CPU 1, 7 is an AND gate that passes the output of OR gate 6 with the match output of EOR gate 4, and RV. is the DCH machine number and activation signal receiver,
DV is a driver that sends response signals 0 to i to the bus 8. In FIG. 1, the buses between the logical device and the plurality of transfer devices, which are indicated by one line as the activation request bus 2, are actually multiple data buses 8, machine number buses 5, and activation request buses, respectively. It consists of buses and is used on a time-sharing basis. 0 to i, 0 to j, and 0 to k represent each bit of data, machine number, and start signal. Since there are multiple types of activation signals, such as transfer requests, IPL, and interrupt reaping, there are multiple activation request buses. If the activation request is rising, one of the lines is at H (high) level, so by ORing the signals on each line of the activation request bus at the gate 6, it is possible to know whether there is an activation request.

In the above system configuration, conventionally, when the transfer device 3 receives the DCH device number and activation request signal sent from the logical device 1 and determines that the activation request corresponds to its own DCH device number, the activation request signal or
The period when the DCH machine number is valid is designated as bus-only time.
A response signal generated on the transfer device 3 side during this time is sent to the bus 8. In other words, the machine number on the machine number bus 5 and the
If the CHC machine numbers match, the output of EOR gate 4 is L.
(low) level, which is inverted to H (high) level and enters the AND gate 7. On the other hand, if there is an activation signal, the output of the OR gate 6 becomes H, so the AND gate 7 produces an H level output and drives the driver. Domestic violence
is activated and a response signal created by the microprogram is placed on bus 8.

When the logic device 1 receives this response signal, it lowers the activation request, and at the fall of this activation signal, the response signal 0~
i is cleared and becomes all 0s. If the activation signal is received again and it is addressed to itself, the AND gate 7 activates the driver DV, and the microprogram creates a response signal and activates the driver DV.
Transfer to logical device via DV.
By the way, if these timings are shifted, the driver DV becomes active even though the microprogram has not yet prepared a response signal, and if the clear at the falling edge of the previous startup request is uncertain and it is not all 0, 0, In this example, (i+
1) bits of meaningless data are sent to bus 8;
The logical device may take this as correct data sent from the transfer device. As mentioned above, the activation signal includes a transfer request (CHC
CALL), IPL, interrupt reaping, etc., and response signals to these transfer requests include call acceptance (CACEPT) and condition code (CC). 0 for condition code,
There are multiple types such as 1, 2, and 3, and these will notify you that startup has been successful, the channel is currently busy, etc.

[Problem that the invention seeks to solve]

According to the conventional method described above, when the hardware recognizes an activation request from the logic device, the bus is immediately occupied and the output from the transfer device is sent to the bus, which prevents unintentional errors by the microprogram. Since even a signal may be sent to the bus, this has the disadvantage of causing a malfunction regarding the start-up sequence. The present invention attempts to solve the above problems by adding turning on a flag provided in hardware to the conditions under which signals can be sent from the transfer device to the bus, and turning on the flag by a microprogram that has completed preparations for returning a response signal. That is.

[Means for solving problems]

The present invention provides an interface control method for a microprogram-controlled information processing device in which activation of a plurality of transfer devices from a logical device is achieved using a 1:n bus method. A flag is provided in hardware to be set when the transfer device recognizes activation from the logic device by a microprogram, and the signal is placed on the bus after the flag is set. It is something.

[Effect]

If a hardware flag is provided in the interface section of the transfer device, and if this flag is turned on as a condition for enabling signal transmission to the bus, and if the flag is turned on by a microprogram that recognizes a startup request, the microprogram This can prevent unintended signals from being sent to the bus by mistake. This will be explained in detail below with reference to illustrated embodiments.

〔Example〕

FIG. 1 is a configuration diagram of a transfer device side interface section showing an embodiment of the present invention, and the same parts as in FIG. 2 are given the same reference numerals. In this example, an AND gate 7 receives the outputs of the EOR gate 4 and the OR gate 6, which is a circuit that generates a signal indicating the activation request from the CPU 1 to the transfer device 3.
In addition to the transfer device 3 microprogram (μ
An AND gate 9 that issues an activation request to the system (abbreviated as ) and a flag 10 that is set when μ recognizes the request are added, and the output of the flag 10 exclusively controls the AND gates 7 and 9. The flag 10 consists of a flip-flop, and when it is not set, it gives an open signal to the AND gate and a close signal to the AND gate 7. Therefore, at the stage when the hardware recognizes the startup request, that is, when the outputs of gates 4 and 6 both become 1, gate 9 opens and issues a startup request to μ, but gate 7 does not open, so driver DV is not turned on and nothing is sent to bus 8. The driver DV is turned on after the flag 10 is set, and at this stage μ operates in response to the activation request and sets a response signal to be transmitted to the bus 8. Therefore, a correct response signal can be placed on the bus 8. When the logic device receives the data and lowers the activation signal, the output of the OR gate 6 becomes L level, gates 7 and 9 are closed, the driver DV is turned off, and the bus 8 is released. At this time, the response signal and flag 10 are reset.

〔Effect of the invention〕

As described above, according to the present invention, even if the hardware recognizes an activation request, the output from the transfer device side is not yet transmitted onto the bus, and the flag indicating that the microprogram has recognized the request from the logic device is sent to the hardware. Since the signal is sent from the time it is set in the software, the signal intended by the microprogram is always sent to the bus, which has the advantage of preventing the above-mentioned malfunction of sending an unintended signal.

[Brief explanation of drawings]

FIG. 1 is a schematic configuration diagram showing an embodiment of the present invention;
FIG. 2 is a schematic block diagram of the entire microprogram-controlled information processing device using bus connections, and FIG. 3 is a schematic diagram of the configuration of a conventional transfer device side interface section. In the figure, 1 is a logical device, 2 is a startup request bus, 3 is a transfer device, 4 is an EOR gate for comparing transfer device numbers,
5 is a machine number bus, 7 is a driver control gate, 8 is a response signal bus, 9 is a startup request output gate to the microprogram, 10 is a flag, DV is a driver, and RV is a receiver.

Claims (1)

[Claims] 1. In an interface control method for a microprogram-controlled information processing device that realizes activation of multiple transfer devices from a logical device using a 1:n bus method, the transfer device that received the activation sends a response signal to the logical device via the bus. A flag is provided in hardware to be set when the transfer device recognizes activation from the logical device by a microprogram, and the timing of the transfer is set after the flag is set. method.