JPS6159562A - Method for controlling interface - Google Patents

Method for controlling interface

Info

Publication number
JPS6159562A
JPS6159562A JP59181155A JP18115584A JPS6159562A JP S6159562 A JPS6159562 A JP S6159562A JP 59181155 A JP59181155 A JP 59181155A JP 18115584 A JP18115584 A JP 18115584A JP S6159562 A JPS6159562 A JP S6159562A
Authority
JP
Japan
Prior art keywords
bus
flag
signal
gate
activation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP59181155A
Other languages
Japanese (ja)
Other versions
JPH0364894B2 (en
Inventor
Haruhiko Tsunoda
治彦 角田
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59181155A priority Critical patent/JPS6159562A/en
Publication of JPS6159562A publication Critical patent/JPS6159562A/en
Publication of JPH0364894B2 publication Critical patent/JPH0364894B2/ja
Granted legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4063Device-to-bus coupling
    • G06F13/4068Electrical coupling
    • G06F13/4072Drivers or receivers

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Debugging And Monitoring (AREA)
  • Information Transfer Systems (AREA)

Abstract

PURPOSE:To prevent a signal not intended by a program from being transmitted to a bus by adding ON of a flag of an interface part to the signal transmissible condition to a bus and turning, further a flag into ON by micro program recog nizing the drive demand. CONSTITUTION:At the time when a hardware recognizes a drive demand, i.e. the output of gates 4, 6 is 1, a gate 9 is opened to give a drive demand to a micro program mu. At this time, a driver DV does not turn ON because a gate 7 does not open, and nothing is transmitted to a bus 8. A driver DV turns ON after a flag 10 is set. At this state, mu acts receiving the drive demand, and a response signal to be transmitted to the bus 8 is set. Consequently, the correct response signal can be transmitted to the bus 8. When a logic device receives data and falls down the drive signal, the output of an OR gate 6 becomes at an L level, the drive DV turns OFF after gates 7, 9 are closed, the response signal and flag 10 are reset after the bus 8 is opened.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、マー−クロプログラムで制御される情報処理
装置において、81:i理装置と転送装置の起動一応答
力I : nのバス結合で動作する場合のインタフェー
ス制御力式に関する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an information processing device controlled by a Markcro program, in which a bus connection between an 81:i physical device and a transfer device and a response force I:n is provided. Concerning the interface control force expression when operating with.

〔従シにの技術〕[Advanced technology]

1台の論理装置と複数台の転送装置との間の起動一応答
が1:iのバス結合で動作する情報処理装置は、概略第
2図のようなシステム配置をとる。
An information processing device that operates with a 1:i bus connection between one logical device and a plurality of transfer devices with an activation/response ratio generally has a system arrangement as shown in FIG.

図中、工は論理装置(CPU) 、2は起動要求ハス、
30〜31はi台のデータ転送装置(DCHまたはCH
C)である。第3図は1台のデータ転送装置3のインタ
フェース部の構成図で、4は自己のCHC機番(DCH
CH2O′〜j′と聞番パス5を通して受信したCPU
IからのD CH121番0−jの一致検出をする排他
的論理和(EOR)ゲート、6はCPUIからの起動信
号0−kをまとめるオアゲート、7はEORゲー1−4
の一致出力でオアゲート6の出力を通過させるアントゲ
−1・、RVはDCHCH2Oび起動信号のレシーバ、
DVは応答信号0− iをバス8へ送出するドライバで
ある。なお第1図では起動要求ハス2として1本の線で
示した論理装置と複数個の転送装置との間のバスは実際
には各々複数本のデータバス8、機番ハス5、及び起動
要求ハスからなり、時分割で使用される。0〜i、0〜
j、0〜l(ばデータ、(フ番、起動信号の各ヒソ(−
を示す。起動信号には転送要求、IPL、割込み刈り取
など複数種あるので起動要求ハスは複数本とする。起動
要求が上っておればいずれかの線がH(ハイ)レベルな
ので、ゲート6で起動要求ハスの各線の信号のオアをと
ることにより起すノ要求の有無を知ることができる。
In the figure, engineering is the logic device (CPU), 2 is the activation request lot,
30 to 31 are i data transfer devices (DCH or CH
C). FIG. 3 is a configuration diagram of the interface section of one data transfer device 3, where 4 indicates its own CHC machine number (DCH
CPU received through CH2O'~j' and serial number path 5
Exclusive OR (EOR) gate that detects coincidence of D CH121 No. 0-j from I, 6 is an OR gate that collects activation signals 0-k from CPUI, 7 is EOR gate 1-4
Ant game 1, which passes the output of the OR gate 6 with a coincidence output, RV is a receiver of DCHCH2O and a start signal;
DV is a driver that sends response signals 0-i to bus 8. In FIG. 1, the buses between the logical device and the plurality of transfer devices, which are indicated by a single line as the activation request bus 2, are actually a plurality of data buses 8, the machine number bus 5, and the activation request. It consists of a lotus and is used on a time-sharing basis. 0~i, 0~
j, 0 to l (data, (f number, start signal) (-
shows. Since there are multiple types of activation signals, such as transfer requests, IPL, and interrupt reaping, there are multiple activation requests. If the activation request is rising, one of the lines is at the H (high) level, so by ORing the signals on each line of the activation request lot at the gate 6, it is possible to know whether there is a request for activation.

上記のシステム(が成において、従来は論理装置1より
送出されるD CH機番と起動要求信号を受けて転送装
置3か自DCH機番に対応する起動要求であると判定し
た場合、該起動要求信号又はDCHI;、u Tiνか
白′効である間をバス専有時間とし、その間に発生する
転送装置3側の応答信号をハス8に送出している。即ら
機悉ハス5上の1幾番と自CHC機番が一致すればEO
Rゲー1−4の出力はL(ロー)レベル、それ力<H(
ハイ)レベルに反市云されてアンドゲート7に入り、一
方、起動信号があればオアゲート6の出力ば■(となり
、従ってアンドゲート7ばHレベル出力を生じてドライ
バDVをアクティブにし、マイクロプログラムが作成し
た応答信号をハス8へのせる。
In the above system, conventionally, upon receiving the DCH device number and activation request signal sent from the logical device 1, if the transfer device 3 determines that the activation request corresponds to its own DCH device number, the activation The period during which the request signal or DCHI is active is defined as the bus exclusive time, and the response signal generated on the transfer device 3 side during that time is sent to the lotus 8. That is, the 1 on the free lotus 5 If the number and own CHC machine number match, it is EO.
The output of R game 1-4 is L (low) level, which is less than H (
On the other hand, if there is an activation signal, the output of the OR gate 6 becomes (), and therefore, the AND gate 7 generates an H level output, activates the driver DV, and executes the microprogram. The response signal created by is placed on the lotus 8.

論理装置1はこの応答信号を取り込むと起動要求を下げ
、この起動信号の立下りで応答信号O〜iはクリアされ
てオールOとなる。再び起動信号が入り、それが自己宛
のものであればアンドゲート7はドライバDVをアクテ
ィブにし、またマイクロプログラムは応答信号を作成し
、ドライノXD■を通して論理装置へ転送されるように
する。ところでこれらのタイミングがずれると、まだマ
イクロプログラムが応答信号を用息しないのにドライバ
DVがアクティブになりそして前回の起動要求の立下り
時のクリヤが不確実でオールOになっていないと、0,
1からなる本例では(i+1)ビットの無意味データが
ハス8へ送出され、論理装置はこれを転送装置から送ら
れた正しいデータとして取り込んでしまう恐れがある。
When the logic device 1 receives this response signal, it lowers the activation request, and at the fall of this activation signal, the response signals O to i are cleared and become all O's. If the activation signal is received again and it is addressed to itself, the AND gate 7 activates the driver DV, and the microprogram creates a response signal to be transferred to the logic device through the Drino XD■. By the way, if these timings are shifted, the driver DV becomes active even though the microprogram has not yet received a response signal, and if the clear at the falling edge of the previous startup request is uncertain and all O's are not set, the 0 ,
In this example, meaningless data of (i+1) bits is sent to the lotus 8, and there is a risk that the logic device may take this as correct data sent from the transfer device.

尚、前述のように起動信号には転送要求(CHCCAL
L)、IPL、割込み刈り取り等があり、この転送要求
に対する応答信号としてはコールアクセ、プ1−(CA
CEPT)とコンディションコード(CC)がある。コ
ンディションコードには0,1,2.3などの傾数種が
あり、これらで起動成功、チャネルは現在ビジーなどを
知らせる。
As mentioned above, the activation signal includes a transfer request (CHCCAL).
L), IPL, interrupt reaping, etc., and response signals to this transfer request include call access, P1-(CA
CEPT) and condition code (CC). Condition codes include slope types such as 0, 1, and 2.3, and these indicate success in startup, the channel is currently busy, etc.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の方式によると、ハードウェアが論理装置
からの起動要求を認識すると、すぐにバスが専有されて
転送装置側の出力がバスに送出される事になり、マ・C
クロプログラムの意図しない誤った信号でもバスに送出
される可能性があるので、起動シーう一ンスに関する誤
動作の要因となる欠点がある。本発明は転送装置からバ
スに信号を送出できる条件にハードウェアに設けたフラ
グのオンを追加し、該フラグを応答信号返送/$備を完
了したマイクロプログラムでオンすることにより上記の
問題点を解決しようとするものである。
According to the conventional method described above, when the hardware recognizes a startup request from a logical device, the bus is immediately occupied and the output from the transfer device is sent to the bus, and the
Since there is a possibility that an erroneous signal that is not intended by the computer program is sent to the bus, there is a drawback that it may cause malfunctions related to the startup sequence. The present invention solves the above problem by adding turning on a flag provided in hardware to the conditions under which signals can be sent from the transfer device to the bus, and turning on the flag by a microprogram that completes response signal return/$ preparation. This is what we are trying to solve.

〔問題点を解決するだめの手段〕[Failure to solve the problem]

本発明は、論理装置より複数の転送装置に対する起動を
1:11のハス方式で実現するマイクロプログラム制御
の情報処理装置のインタフェース制御方式において、起
動を受けた転送装置が該論理装置へ返す応答信号をハス
へのせるタイミングを、該転送装置が該論理装置よりの
起動をマイクロプログラムで認識したときセントするフ
ラグをハードウェアに設けて、該フラグがセ・ノドされ
た以降にすることを特徴とするものである。
The present invention provides an interface control method for a microprogram-controlled information processing device that realizes activation of multiple transfer devices from a logic device in a 1:11 ratio, in which a response signal that a transfer device that has received activation returns to the logic device is used. A flag is provided in the hardware to be sent when the transfer device recognizes activation from the logic device by the microprogram, and the timing for placing the transfer device on the lotus is set after the flag is set. It is something to do.

〔作用〕[Effect]

転送装置のインタフェース部にノ\−ドウエアによるフ
ラグを設け、且つこのフラグのオンをバスへの信号送出
可条件に加え、さらに該フラグを起動要求を認識したマ
イクロプログラムでオンするようにすると、マイクロプ
ログラムが意図しない信号が誤ってバスへ送出されるこ
とを防止できる。
If a flag is provided in the interface section of the transfer device by the node/ware, and if this flag is turned on as a condition for allowing signal transmission to the bus, and if the flag is turned on by a microprogram that recognizes an activation request, the microprogram It is possible to prevent signals that are not intended by the program from being erroneously sent to the bus.

以下、図示の実施例を参照しながらこれを詳細に説明す
る。
This will be explained in detail below with reference to illustrated embodiments.

〔実施例〕〔Example〕

第1図は本発明の一実施例を示す転送装置側インタフェ
ース部の構成図で、第2図と同一部分には同一符号が付
しである。本例では、本転送装置3に対するCPUIか
らの起動要求があったときそれを示す信号を生じる回路
つまりEORゲート+1とオアゲー1−〇の出力を受け
るアン(−ゲー(・7に加えて、転送装置3のマイクロ
プログラム(μと略記する)に対し起動要求を与えるア
ンドゲート9と、μが該要求を認識したときセラ1−す
るフラグ10とを追加し、フラグ10の出力でアンドゲ
ート7.9を排他的に制fllする。フラグ10はフリ
ップフロップからなり、セットされない状態ではアンド
ゲートに開信号を、アントゲ−1・7には閉信号を与え
る。従って、起動要求をハードウェアが認識した段階、
つまりゲート4,6の出力が共に1になった段階ではゲ
ー(・9が開いてμへの起動要求を出すが、ゲート7は
開かないのでドライl” D Vはオンとならず、ハス
8へは何も送信されない。ドライバDVがオンとなるの
はフラグ10かセットされた後であり、この段階ではμ
が起動要求を受けて動作し、ハス8に送信すべき応答信
号をセラとしておく。従ってバス8へは正しい応答信号
をのせることができる。論理装置がデータを受取って起
動信号を立下げればオアゲー1−6の出力はLレベルに
なり、ゲート7.9が閉じてトライバDVはオフとなり
、ハス8は13.rj放される。またこのとき応答1j
号及びフラグ10のリセラI−が行なわれる。
FIG. 1 is a configuration diagram of a transfer device side interface section showing an embodiment of the present invention, and the same parts as in FIG. 2 are given the same reference numerals. In this example, in addition to the circuit that generates the signal indicating when there is a startup request from the CPU for the transfer device 3, that is, the output of the EOR gate +1 and the OR gate 1-0, An AND gate 9 that issues a startup request to the microprogram (abbreviated as .mu.) of the device 3, and a flag 10 that activates when .mu. recognizes the request are added, and the output of the flag 10 causes an AND gate 7. 9 is exclusively controlled.Flag 10 consists of a flip-flop, and when it is not set, it gives an open signal to the AND gate, and gives a close signal to AND gates 1 and 7.Therefore, when the hardware recognizes the activation request, step,
In other words, when the outputs of gates 4 and 6 both become 1, gate 9 opens and issues an activation request to μ, but gate 7 does not open, so dry l"D V does not turn on, and gate 8 Nothing is sent to the driver DV.The driver DV is turned on after flag 10 is set, and at this stage μ
operates in response to the activation request, and sends a response signal to be sent to the lotus 8 as a cell. Therefore, a correct response signal can be placed on the bus 8. When the logic device receives the data and lowers the activation signal, the output of OR game 1-6 becomes L level, the gate 7.9 closes, the driver DV turns off, and the lotus 8 becomes 13. rj released. At this time, response 1j
The reseller I- with the number and flag 10 is performed.

〔発明の〃)果〕[Results of invention]

以上述べたように本発明によれは、ハードウェアが起動
要求を認1識してもまだハス上Qこ転送装置側の出力が
送信されず、マイクロプログラムが論理装置の要求を認
識した旨のフラグをハードウェアに設定した時点より送
出されるので、常にマイクロプログラムの窓口した信号
がハスに送出され、g′、図しない信号送出という前記
誤動作を防止することができる利点がある。
As described above, according to the present invention, even if the hardware recognizes the startup request, the output from the transfer device side is not yet sent, and the microprogram does not receive a message indicating that it has recognized the request from the logical device. Since the flag is sent from the moment the flag is set in the hardware, the signal communicated by the microprogram is always sent out, and the advantage is that g', the above-mentioned malfunction of unintended signal sending, can be prevented.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の一実施例を示す1Rm6.47!成図
、第2図はバス結合によるマーCクロプログラム制御の
情報処理装置全体の概略ブロック図、第3図は従来の転
送装置側インタフェース部の概略構成図である。 図中、■は論理装置、2は起すJ要求ハス、3は転送装
置、4は転送Pi置番号比較用EORゲーI・、5は機
番バス、7ばドライバ制御用ゲート、8は応答侶号用ハ
ス、9はマイクロプログラムへの起動要求出力ゲート、
10はフラグ、DVはドライバ、RJレシーバである。
FIG. 1 shows an embodiment of the present invention with 1Rm6.47! FIG. 2 is a schematic block diagram of the entire information processing device for Mark C program control using bus connections, and FIG. 3 is a schematic block diagram of a conventional transfer device side interface section. In the figure, ■ is a logic device, 2 is a J request lot that originates, 3 is a transfer device, 4 is an EOR game I for comparing transfer Pi location numbers, 5 is a machine number bus, 7 is a driver control gate, 8 is a responder Lotus number 9 is the start request output gate to the microprogram,
10 is a flag, DV is a driver, and RJ receiver.

Claims (1)

【特許請求の範囲】[Claims] 論理装置より複数の転送装置に対する起動を1:nのバ
ス方式で実現するマイクロプログラム制御の情報処理装
置のインタフェース制御方式において、起動を受けた転
送装置が該論理装置へ返す応答信号をバスへのせるタイ
ミングを、該転送装置が該論理装置よりの起動をマイク
ロプログラムで認識したときセットするフラグをハード
ウエアに設けて、該フラグがセットされた以降にするこ
とを特徴とするインタフェース制御方式。
In an interface control method for a microprogram-controlled information processing device that realizes activation of multiple transfer devices from a logical device using a 1:n bus method, the transfer device that received the activation sends a response signal to the logical device to the bus. An interface control method characterized in that a flag is provided in hardware to be set when the transfer device recognizes activation from the logical device by a microprogram, and the timing is set after the flag is set.
JP59181155A 1984-08-30 1984-08-30 Method for controlling interface Granted JPS6159562A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59181155A JPS6159562A (en) 1984-08-30 1984-08-30 Method for controlling interface

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59181155A JPS6159562A (en) 1984-08-30 1984-08-30 Method for controlling interface

Publications (2)

Publication Number Publication Date
JPS6159562A true JPS6159562A (en) 1986-03-27
JPH0364894B2 JPH0364894B2 (en) 1991-10-08

Family

ID=16095848

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59181155A Granted JPS6159562A (en) 1984-08-30 1984-08-30 Method for controlling interface

Country Status (1)

Country Link
JP (1) JPS6159562A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0337595A2 (en) * 1988-03-14 1989-10-18 Advanced Micro Devices, Inc. Integrated circuit having a configurable terminal pin
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0337595A2 (en) * 1988-03-14 1989-10-18 Advanced Micro Devices, Inc. Integrated circuit having a configurable terminal pin
US6531784B1 (en) 2000-06-02 2003-03-11 Amkor Technology, Inc. Semiconductor package with spacer strips

Also Published As

Publication number Publication date
JPH0364894B2 (en) 1991-10-08

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