JPS6159562A - Method for controlling interface - Google Patents

Abstract

PURPOSE:To prevent a signal not intended by a program from being transmitted to a bus by adding ON of a flag of an interface part to the signal transmissible condition to a bus and turning, further a flag into ON by micro program recog nizing the drive demand. CONSTITUTION:At the time when a hardware recognizes a drive demand, i.e. the output of gates 4, 6 is 1, a gate 9 is opened to give a drive demand to a micro program mu. At this time, a driver DV does not turn ON because a gate 7 does not open, and nothing is transmitted to a bus 8. A driver DV turns ON after a flag 10 is set. At this state, mu acts receiving the drive demand, and a response signal to be transmitted to the bus 8 is set. Consequently, the correct response signal can be transmitted to the bus 8. When a logic device receives data and falls down the drive signal, the output of an OR gate 6 becomes at an L level, the drive DV turns OFF after gates 7, 9 are closed, the response signal and flag 10 are reset after the bus 8 is opened.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention provides an information processing device controlled by a Markcro program, in which a bus connection between an 81:i physical device and a transfer device and a response force I:n is provided. Concerning the interface control force expression when operating with.

[Advanced technology]

An information processing device that operates with a 1:i bus connection between one logical device and a plurality of transfer devices with an activation/response ratio generally has a system arrangement as shown in FIG.

In the figure, engineering is the logic device (CPU), 2 is the activation request lot,
30 to 31 are i data transfer devices (DCH or CH
C). FIG. 3 is a configuration diagram of the interface section of one data transfer device 3, where 4 indicates its own CHC machine number (DCH
CPU received through CH2O'~j' and serial number path 5
Exclusive OR (EOR) gate that detects coincidence of D CH121 No. 0-j from I, 6 is an OR gate that collects activation signals 0-k from CPUI, 7 is EOR gate 1-4
Ant game 1, which passes the output of the OR gate 6 with a coincidence output, RV is a receiver of DCHCH2O and a start signal;
DV is a driver that sends response signals 0-i to bus 8. In FIG. 1, the buses between the logical device and the plurality of transfer devices, which are indicated by a single line as the activation request bus 2, are actually a plurality of data buses 8, the machine number bus 5, and the activation request. It consists of a lotus and is used on a time-sharing basis. 0~i, 0~
j, 0 to l (data, (f number, start signal) (-
shows. Since there are multiple types of activation signals, such as transfer requests, IPL, and interrupt reaping, there are multiple activation requests. If the activation request is rising, one of the lines is at the H (high) level, so by ORing the signals on each line of the activation request lot at the gate 6, it is possible to know whether there is a request for activation.

In the above system, conventionally, upon receiving the DCH device number and activation request signal sent from the logical device 1, if the transfer device 3 determines that the activation request corresponds to its own DCH device number, the activation The period during which the request signal or DCHI is active is defined as the bus exclusive time, and the response signal generated on the transfer device 3 side during that time is sent to the lotus 8. That is, the 1 on the free lotus 5 If the number and own CHC machine number match, it is EO.
The output of R game 1-4 is L (low) level, which is less than H (
On the other hand, if there is an activation signal, the output of the OR gate 6 becomes (), and therefore, the AND gate 7 generates an H level output, activates the driver DV, and executes the microprogram. The response signal created by is placed on the lotus 8.

When the logic device 1 receives this response signal, it lowers the activation request, and at the fall of this activation signal, the response signals O to i are cleared and become all O's. If the activation signal is received again and it is addressed to itself, the AND gate 7 activates the driver DV, and the microprogram creates a response signal to be transferred to the logic device through the Drino XD■. By the way, if these timings are shifted, the driver DV becomes active even though the microprogram has not yet received a response signal, and if the clear at the falling edge of the previous startup request is uncertain and all O's are not set, the 0 ，
In this example, meaningless data of (i+1) bits is sent to the lotus 8, and there is a risk that the logic device may take this as correct data sent from the transfer device.

As mentioned above, the activation signal includes a transfer request (CHCCAL).
L), IPL, interrupt reaping, etc., and response signals to this transfer request include call access, P1-(CA
CEPT) and condition code (CC). Condition codes include slope types such as 0, 1, and 2.3, and these indicate success in startup, the channel is currently busy, etc.

[Problem that the invention seeks to solve]

According to the conventional method described above, when the hardware recognizes a startup request from a logical device, the bus is immediately occupied and the output from the transfer device is sent to the bus, and the
Since there is a possibility that an erroneous signal that is not intended by the computer program is sent to the bus, there is a drawback that it may cause malfunctions related to the startup sequence. The present invention solves the above problem by adding turning on a flag provided in hardware to the conditions under which signals can be sent from the transfer device to the bus, and turning on the flag by a microprogram that completes response signal return/$ preparation. This is what we are trying to solve.

[Failure to solve the problem]

The present invention provides an interface control method for a microprogram-controlled information processing device that realizes activation of multiple transfer devices from a logic device in a 1:11 ratio, in which a response signal that a transfer device that has received activation returns to the logic device is used. A flag is provided in the hardware to be sent when the transfer device recognizes activation from the logic device by the microprogram, and the timing for placing the transfer device on the lotus is set after the flag is set. It is something to do.

[Effect]

If a flag is provided in the interface section of the transfer device by the node/ware, and if this flag is turned on as a condition for allowing signal transmission to the bus, and if the flag is turned on by a microprogram that recognizes an activation request, the microprogram It is possible to prevent signals that are not intended by the program from being erroneously sent to the bus.

This will be explained in detail below with reference to illustrated embodiments.

〔Example〕

FIG. 1 is a configuration diagram of a transfer device side interface section showing an embodiment of the present invention, and the same parts as in FIG. 2 are given the same reference numerals. In this example, in addition to the circuit that generates the signal indicating when there is a startup request from the CPU for the transfer device 3, that is, the output of the EOR gate +1 and the OR gate 1-0, An AND gate 9 that issues a startup request to the microprogram (abbreviated as .mu.) of the device 3, and a flag 10 that activates when .mu. recognizes the request are added, and the output of the flag 10 causes an AND gate 7. 9 is exclusively controlled.Flag 10 consists of a flip-flop, and when it is not set, it gives an open signal to the AND gate, and gives a close signal to AND gates 1 and 7.Therefore, when the hardware recognizes the activation request, step,
In other words, when the outputs of gates 4 and 6 both become 1, gate 9 opens and issues an activation request to μ, but gate 7 does not open, so dry l"D V does not turn on, and gate 8 Nothing is sent to the driver DV.The driver DV is turned on after flag 10 is set, and at this stage μ
operates in response to the activation request, and sends a response signal to be sent to the lotus 8 as a cell. Therefore, a correct response signal can be placed on the bus 8. When the logic device receives the data and lowers the activation signal, the output of OR game 1-6 becomes L level, the gate 7.9 closes, the driver DV turns off, and the lotus 8 becomes 13. rj released. At this time, response 1j
The reseller I- with the number and flag 10 is performed.

[Results of invention]

As described above, according to the present invention, even if the hardware recognizes the startup request, the output from the transfer device side is not yet sent, and the microprogram does not receive a message indicating that it has recognized the request from the logical device. Since the flag is sent from the moment the flag is set in the hardware, the signal communicated by the microprogram is always sent out, and the advantage is that g', the above-mentioned malfunction of unintended signal sending, can be prevented.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention with 1Rm6.47! FIG. 2 is a schematic block diagram of the entire information processing device for Mark C program control using bus connections, and FIG. 3 is a schematic block diagram of a conventional transfer device side interface section. In the figure, ■ is a logic device, 2 is a J request lot that originates, 3 is a transfer device, 4 is an EOR game I for comparing transfer Pi location numbers, 5 is a machine number bus, 7 is a driver control gate, 8 is a responder Lotus number 9 is the start request output gate to the microprogram,
10 is a flag, DV is a driver, and RJ receiver.

Claims (1)

[Claims] In an interface control method for a microprogram-controlled information processing device that realizes activation of multiple transfer devices from a logical device using a 1:n bus method, the transfer device that received the activation sends a response signal to the logical device to the bus. An interface control method characterized in that a flag is provided in hardware to be set when the transfer device recognizes activation from the logical device by a microprogram, and the timing is set after the flag is set.