JPS63186341A - Program testing circuit - Google Patents

Abstract

PURPOSE:To facilitate a program test even in an interruption inhibiting state by transmitting a mask unable interruption signal at the time of transmission/ reception of data and inhibiting the interruption until the transmission/reception of data carried out by the interruption caused in response to said interruption signal is through. CONSTITUTION:The output of an AND gate 8 is turned on by the input of a reception data signal 21 while an FF 3 is previously is kept turned on and a mask unable interruption signal NMI22 is sent to a processor 1. Then the processor 1 applies an interruption to a program which is read out of a memory 2 and processed. Thus the processor 1 performs a mask unable interruption processing job to immediately turn off the FF 3. The interruptions are inhibited until the FF 3 is turned on again. As a result, an interruption is applied to the program of the processor 1 only at the time of the first rise of the signal 21. Thus a programming job is facilitated. Furthermore the program can be tested despite an inhibition state of the processor 1 owing to the interruption processing carried out by the signal NMI22. Then the processing state can be tested even in its busy mode.

Description

DETAILED DESCRIPTION OF THE INVENTION 1. Field of the Invention The present invention relates to a program test circuit, and more particularly to a program test circuit that tests a program for a microprocessor or the like.

Conventionally, this type of program test circuit uses a general-purpose communication control circuit that is an input/output control section of a processor. When connecting a general terminal to another M device, if the speed is low, E
tA-R8232C standard interface is used, and for high speed, IEEε-488 standard interface (G
PIB) or 5AS1.5C8I.

Since this general-purpose communication control circuit requires low speed, R8232
A C interface is used, and this interface is a serial interface.

Generally, serial-to-parallel conversion is not performed by a microprocessor program, but by an external circuit.

This general-purpose communication control circuit each has a buffer that stores one or more characters of received data and transmitted data, and generates an interrupt when data enters or runs out of this buffer. The data is controlled by the program. Moreover, a maskable interrupt signal is used for this interrupt signal.

That is, EIA-R32 is used as this general-purpose communication control circuit.
Since it is designed for a 32C interface and is slow, an interrupt occurs every time one character's worth of data is sent or received without using DMA (direct memory access).

Such conventional program test circuits have a buffer that stores received data and transmitted data, and use a maskable interrupt signal to generate an interrupt when data enters the buffer and when there is no more data in the buffer. Since the data was controlled by the program using this interrupt, there is a drawback that the program cannot be tested in the interrupt disabled state.

In addition, this general-purpose communication control circuit generates an interrupt every time one character's worth of data is transmitted or received, so another interrupt process must be performed during the program interrupt process.
Handle this large number of interrupts correctly! l! This has the disadvantage that it is difficult to perform interrupt processing, and it is not easy to test a program for processing interrupts.

Furthermore, a general-purpose communication II control circuit is used as a test circuit, and since this general-purpose communication control circuit converts serial data and parallel data, the circuit becomes complicated.

The present invention has been made in order to eliminate the drawbacks of the conventional system B as described above, and it is possible to test a program even when interrupts are disabled, and it is possible to The purpose is to provide a program test circuit that can be easily tested.

The program test circuit according to the present invention sends a non-maskable interrupt signal to the central processing unit when transmitting or receiving data,
The present invention is characterized by comprising means for prohibiting an interrupt to the central processing unit until the data transmission/reception process due to an interrupt generated in response to the non-maskable interrupt signal is completed.

Maruse 1 Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. In the figure, one embodiment of the present invention includes fritsubbufs [1] that can be set and reset by a program, a command decoder 6, an AND gate 7.8, and a receiver.
It is composed of a driver 10.

FIG. 2 is a time chart showing a data receiving operation in an embodiment of the present invention, and FIG. 3 is a time chart 1- showing a data transmitting operation in an embodiment of the present invention.

The operation of an embodiment of the present invention will be explained using FIGS. 1 to 3.

A received data signal 21 from the simple terminal 11 having a serial interface is received by the receiver 9. The serial interface of this simple terminal 11 is E.
[Assumed to be compliant with A-R3232C.]

If the character rAJ is expressed in the 8-digit code according to JISC6220, it is r010000012 (=4116)J, and in E IA-R8232C, a start bit (ST) and a stop bit (SP) are added before and after this code, so rsTloooooloSPJ (See received data signal 21 in Figure 2, ST has the same polarity as 0, SP
is the same polarity as 1) (sent sequentially from the lower bit).

rA [return] as a command from the simple terminal 11
(The input of the [Return] key means the end of the instruction from the simple terminal 11), the received data signal 21
rsTloooooloSP 5TIO on the signal line of
It is output as I100OO3PJ (see received data signal 21 in FIG. 2).

With the flip-flop 3 set to ON in advance, the AND gate 8 is turned on by inputting the received data signal 21.
output is turned on, a non-maskable interrupt signal (hereinafter referred to as NMI) 22 is sent to the processor 1, which interrupts the program being read from the memory 2 and is being processed. Possible interrupt processing is executed.

The flip-flop 3 is immediately turned off by this non-maskable interrupt processing, and after the input of this NMI 22,
Interrupts are prohibited until flip-flop 3 is turned on.

After the flip-flop 3 is turned off, when a fetch command from the processor 1 is detected by the command decoder 6, one bit is read through the AND gate 7 at a time interval commensurate with the transmission speed of the received data signal 21. The received data signal 21 that is sent to the processor 1 is taken in by the processor 1.
1, while monitoring the state of the received data signal 21, it assembles and processes the received data signal 21 into a character (A in this case), and detects [return] to detect the end of the instruction.

When [Return] is detected, the data will not be sent until a certain amount of time has elapsed, or the next data that will be sent will have a different meaning, so flip 70 knob 3. Set it to 1 again and prepare for the next data reception process.

A transmission data signal 20 is sent out from the processor 1 and inputted to the flip 70 block 5 via the flip 70 block 4. The transmission data signal 20 is shaped into regular intervals by the clock 23 in the flip 70 block 5, and is transmitted bit by bit via the driver 10 (see FIG. 3; the transmission data signal 20, like the reception data signal 21, Start bit (ST) and stop bit (SP) before and after
).

When all the transmission processing is completed, the processor 1 turns on the flip-flop 3 to prepare for the next data transmission/reception processing.

In this way, NMI is sent to processor 1 when transmitting and receiving data.
22 and disables interrupts to the processor 1 by turning off the flip-flop 3 until the data transmission/reception process due to the interrupt generated in response to the NMI 22 is completed. 1
Since the program can be interrupted only at the first rise of the received data signal @21, programming becomes easy.

Furthermore, since the interrupt processing is performed by the NMI 22, the program can be tested even when the processor 1 is in an interrupt-disabled state, and even if the program of the processor 1 is executing interrupt processing, the processing can be easily tested. Can be done.

Furthermore, since the conversion between serial data and parallel data is performed by the processor 1 according to a program, a serial-to-parallel conversion circuit is not required.

As explained above, according to the present invention, a non-maskable interrupt signal is sent during data transmission and reception, and the data is processed by an interrupt generated in response to the non-maskable interrupt signal. By disabling interrupts until the sending/receiving process is completed, the program being processed can receive an interrupt only at the first rise of data, which simplifies programming and prevents non-maskable data. Interrupt signal.

Since interrupt processing is performed by a signal, the program can be tested even when interrupts are disabled, and even if the program is executing interrupt processing, the processing can be easily tested.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a time chart showing a data reception operation in an embodiment of the invention, and FIG. 3 is a data transmission operation in an embodiment of the invention. FIG. Explanation of the symbols of the four main parts 3 to 5...Flip-flop 6...Command decoder 7.8...And gate 9...Receiver 10... ····driver

Claims (1)

[Claims] Sends a non-maskable interrupt signal to the central processing unit when transmitting/receiving data, and prevents interrupts to the central processing unit until the data transmitting/receiving process due to the interrupt generated in response to the non-maskable interrupt signal is completed. A program test circuit characterized by having means for inhibiting the program.