JPS6226740B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure detection circuit that detects failures in a plurality of input/output devices installed in parallel in an electronic computer.

Conventionally, there has been a failure detection circuit of this type as shown in FIG. In the figure, a computer 1 has input/output devices 2a, 2b, 2c, and 2d installed in parallel, and these computer 1 and input/output devices 2a
2d, an address signal line 3 for specifying a predetermined input/output device, a data line 4 for transmitting input/output data, a control signal line 5 for specifying an operation for the input/output device, and an operation signal line 5 for specifying an operation for the input/output device. a starting signal line 6 for commanding;
and an operation completion signal line 7 indicating the completion of the operation of the input/output device.

Therefore, 8 is a failure detection circuit provided in the computer 1, and this failure detection circuit 8 is constituted by a delay circuit 9, and the operation completion signal is not returned but is sent to the start signal line 6. When the activation signal 6a becomes significant for a certain period of time or more, the delay signal 10 of the delay circuit 9 is outputted to the computer 1 as a failure signal.

In the configuration shown in FIG. 1, the electronic computer 1 transmits an address signal specifying one of the input/output devices 2a to 2d, a control signal indicating an input operation, and a start signal to an address signal line 3, a control signal line 5, and a start signal line. 6
For example, the input/output device 2a specified by the address signal starts operating in response to the control signal and start signal, and sends an operation completion signal along with the input data to the data line 4. and is sent back to the computer 1 via the operation completion signal line 7. Therefore, the electronic computer 1
After confirming that the operation completion signal has been returned, the input data is taken in, and then the activation signal is made inactive and the data reading operation is completed.

However, at that time, if the operation completion signal is not returned due to a failure of the input/output device, etc., the computer 1 will not be able to import the input data.
The system waits until the operation completion signal is returned. However, this computer 1 has a built-in failure detection circuit 8, and if an operation completion signal is not returned within a certain period of time after outputting the start signal, a failure signal is sent to the computer 1. By outputting this information, failures in input/output devices are detected.

However, since the conventional fault detection circuit is configured as described above, it is possible to detect a fault in an input/output device such that an operation completion signal is not returned. A failure in which an operation completion signal is sent from the input/output device to the computer even though the start signal is not sent to the input/output device due to a short circuit in the signal line or a defective output IC. It had the disadvantage that it could not be detected. That is,
If the failure cannot be detected and the operation completion signal continues to be returned, the computer 1 cannot recognize the failure and may erroneously import data.

The present invention has been made in order to eliminate the drawbacks of the conventional devices as described above, and is capable of detecting not only failures in which the operation completion signal is not returned, but also failures in which the operation completion signal is returned. The present invention provides a new failure detection device that can perform the following tasks.

Hereinafter, one embodiment of the present invention will be described with reference to FIG. 2, in which the same parts as in FIG. 1 are denoted by the same reference numerals.
In FIG. 2, a failure detection circuit 11 of the present invention built into an electronic computer 1 includes AND circuits 12, 13, 15, and a memory element 14 in addition to a conventional delay circuit 9. That is, in the failure detection circuit 11 of the present invention, the activation signal 6a output from the computer 1 is ANDed with the inverted signal of the operation completion signal 7 by the AND circuit 12, and the AND output is It is stored in the memory element 14 set by the activation signal 6a, and the output of the storage element 14 is outputted as the activation signal 6 to the input/output devices 2a to 2d. The activation signal 6a is ANDed with the inverted signal of the operation completion signal 7 by the AND circuit 12 and stored in the storage element 14, and the output thereof is the activation signal 6.
It is output to the input/output devices 2a to 2d as follows. On the other hand, the operation completion signal 7 is ANDed with the output of the storage element 14 by an AND circuit 13 which is an AND circuit for sending out an operation completion signal, and this AND output is used as the operation completion signal 7a in the electronic computer 1.
The failure signal 15a of the input/output device is electronically sent back to the input/output device by an AND circuit 15 which obtains an AND between the inverted signal of the operation completion signal 7a and the delay signal 10 of the delay circuit 9. The configuration is such that it is given to computer 1.

Next, the operation of the above configuration will be explained. First of all,
During normal operation, the computer 1 is connected to the input/output device 2.
an address signal specifying any one of a to 2d;
A control signal indicating an input operation and a start signal are connected to an address signal line 3, a control signal line 5 and a start signal line 6a.
At this point, the operation completion signal line 7 is output to the input/output device via the operation completion signal line 7, and the output of the storage element 14, which has not been returned, is output as a start signal to the start signal line 6.
Output via . Then, for example, the input/output device 2a specified by the address signal starts operating in response to the control signal and activation signal,
The operation completion signal along with the input data is sent back to the computer 1 via the data line 4 and the operation completion signal line 7. At this point, the above operation completion signal is
An AND circuit 13 performs an AND operation with the output of the memory element 14, and the output of the AND circuit 13 is sent back to the computer 1 as an operation completion signal via the operation completion signal line 7a. Therefore,
The computer 1 receives the input data after confirming that the operation completion signal has been returned;
Next, the activation signal is made inactive and the data reading operation is completed. At this time, the AND circuit 15 which obtains the AND of the output inverted signal of the AND circuit 13a and the delayed signal of the delay circuit 9 does not output a failure signal of the input/output device, and when the activation signal becomes invalid, the memory element 14 and delay circuit 9 are reset.

Next, in the event of an abnormality, that is, if the operation completion signal has already been returned due to a failure of the input/output device at the time when the computer 1 outputs the start signal, the operation completion signal is still being returned from the input/output device. Even if the computer 1 outputs the start signal 6a in this state, the AND circuit 12 performs an AND with the inverted signal of the operation completion signal, so the memory element 14 is not set, and therefore the input/output device is not No start signal is output. Further, since the operation completion signal from the input/output device is ANDed with the output of the storage element 14 by the AND circuit 13, the operation completion signal is not returned to the computer 1. On the other hand, since the delay circuit 9 is activated by the activation signal 6a, the AND circuit 15 that obtains the logical product of the delayed signal output after a certain period of time and the inverted output signal of the AND circuit 13 is sent to the electronic computer 1. This causes the computer 1 to output a failure signal 15a.
can handle failures without erroneously importing data. Furthermore, in the case of an abnormality in which an operation completion signal is not returned due to a failure of the input/output device, the failure can of course be detected by performing the same operation as the conventional device.

In the above embodiment, a case has been described in which the electronic computer 1 performs an input operation, but it goes without saying that the present invention can be implemented in the same manner when the computer 1 performs an output operation.
Furthermore, since the present invention uses the delay circuit 9,
Even if the operation completion signal is delayed due to the propagation delay time of the signal in the signal line, it will operate normally within the set time of the delay circuit, so it is effective not only as a failure detection function but also as a failsafe function.

As described above, according to the present invention, an AND circuit and a memory element are added to the failure detection circuit to monitor the state of the operation completion signal. In addition to detection, it is also possible to detect failures in cases where the items are still being returned, allowing for more complete failure detection.

[Brief explanation of the drawing]

FIG. 1 is a connection diagram showing a conventional failure detection circuit for an input/output device, and FIG. 2 is a connection diagram showing a failure detection circuit for an input/output device according to an embodiment of the present invention. 1...Electronic computer, 2a-2d...I/O device, 3...Address signal line, 4...Data line, 5
...Control signal line, 6...Start signal line, 7...Operation completion signal line, 8, 11...Failure detection circuit, 9...
Delay circuit, 12, 13, 15...AND circuit, 1
4...Memory element, the same reference numerals in the figures are the same,
or a corresponding portion.

Claims (1)

[Claims] 1. Equipped with a delay circuit that delays a start signal sent from the computer to the input/output device side for a predetermined period of time, and based on the delay signal of this delay circuit and the operation completion signal given from the input/output device side to the computer side. The failure detection circuit for detecting a failure in the input/output device includes an AND circuit that obtains an AND of the inverted signal of the operation completion signal and the start signal, and an output of the AND circuit that is set by the start signal. a memory element that stores the memory output and sends the memory output as a start signal to the input/output device, and an operation completion signal that obtains a logical product of the operation completion signal and the output of the storage element and supplies it to the computer. an AND circuit for sending out an operation completion signal; and an AND circuit for detecting a failure, which obtains an AND of an inverted output signal of the AND circuit and a delayed signal of the delay circuit, and generates a failure detection signal for the input/output device. A failure detection circuit for an input/output device, characterized in that it is provided with: