JP2638257B2 - Error handling circuit for control power supply - Google Patents
Error handling circuit for control power supplyInfo
- Publication number
- JP2638257B2 JP2638257B2 JP2127963A JP12796390A JP2638257B2 JP 2638257 B2 JP2638257 B2 JP 2638257B2 JP 2127963 A JP2127963 A JP 2127963A JP 12796390 A JP12796390 A JP 12796390A JP 2638257 B2 JP2638257 B2 JP 2638257B2
- Authority
- JP
- Japan
- Prior art keywords
- abnormality
- power supply
- microcomputer
- control power
- detection signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Description
【発明の詳細な説明】 産業上の利用分野 本発明は制御電源の異常処理回路に関するもので、さ
らに詳しく言えば制御電源の異常を検出し、その異常情
報を格納して処理できるようにした回路に関するもので
ある。Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an abnormality processing circuit of a control power supply, and more specifically, a circuit capable of detecting an abnormality of a control power supply and storing and processing the abnormality information. It is about.
従来の技術 近年、マイクロコンピュータを内蔵した機器が普及
し、種々の制御がこのマイクロコンピュータによって行
われるようになってきている。このような機器では、マ
イクロコンピュータを安定に動作させるため、またマイ
クロコンピュータの制御電源の異常を監視するため、制
御電源に監視回路を設け、停電等によって制御電源に異
常が発生した場合には、異常検出信号によってマイクロ
コンピュータをリセットするとともに、その異常情報を
マイクロコンピュータに接続したバックアップが可能な
RAMに格納し、正常な状態に復帰した後で前記異常情報
を処理して信頼性の向上等に寄与させている。2. Description of the Related Art In recent years, devices incorporating a microcomputer have become widespread, and various controls have been performed by the microcomputer. In such a device, in order to operate the microcomputer stably, and to monitor the abnormality of the control power supply of the microcomputer, a monitoring circuit is provided in the control power supply, and when an abnormality occurs in the control power supply due to a power failure or the like, The microcomputer can be reset by the abnormality detection signal and the abnormality information can be backed up by connecting to the microcomputer
The information is stored in a RAM, and after returning to a normal state, the abnormal information is processed to contribute to improvement of reliability.
上記の如き制御電源の異常処理回路の従来例を第３図
により説明する。第３図において、１はマイクロコンピ
ュータで、制御電源２から駆動用電力の供給を受けてい
る。３は前記制御電源２の監視回路で、停電等による電
圧の低下のような異常を検出し、異常検出信号によって
前記マイクロコンピュータ１をリセットさせる。４は上
記の如き異常情報を格納するためのRAM、５は前記RAMに
格納された情報を保持するためのバックアップ電源であ
る。このような異常処理回路では、監視回路３から送出
される異常検出信号によってマイクロコンピュータ１を
リセットするとともに、前記異常情報をRAM4に格納する
ようにしている。すなわち、第４図のように時刻t0で制
御電源電圧がV0になった時に送出される異常検出信号に
よってマイクロコンピュータ１のリセットとRAM4への異
常情報の格納とが行われる。また、制御電源電圧は、そ
の後時刻t1でマイクロコンピュータが動作可能な下限電
圧V1まで低下していることが示されている。A conventional example of the control power supply abnormality processing circuit as described above will be described with reference to FIG. In FIG. 3, reference numeral 1 denotes a microcomputer which is supplied with driving power from a control power supply 2. A monitoring circuit 3 for the control power supply 2 detects an abnormality such as a voltage drop due to a power failure or the like, and resets the microcomputer 1 by an abnormality detection signal. Reference numeral 4 denotes a RAM for storing the abnormal information as described above, and reference numeral 5 denotes a backup power supply for holding the information stored in the RAM. In such an abnormality processing circuit, the microcomputer 1 is reset by an abnormality detection signal sent from the monitoring circuit 3, and the abnormality information is stored in the RAM 4. In other words, storage and abnormality information to reset and RAM4 microcomputer 1 is performed by the abnormality detection signal sent when the control power supply voltage at time t 0 as in the fourth diagram becomes V 0. Also, the control power supply voltage, it has been shown that the microcomputer thereafter time t 1 is reduced lower limit to the voltages V 1 operable.
発明が解決しようとする課題 上記した制御電源の異常処理回路は、異常検出信号に
よってマイクロコンピュータ１のリセットとRAM4への異
常情報の格納とが同時に行われるため、RAM4に格納され
る異常情報が不完全になり、正常な状態に復帰した後で
前記異常情報を処理することができないという欠点があ
った。In the above-described abnormality processing circuit of the control power supply, the reset of the microcomputer 1 and the storage of the abnormality information in the RAM 4 are simultaneously performed by the abnormality detection signal. There is a drawback that the abnormal information cannot be processed after it has become complete and has returned to a normal state.
課題を解決するための手段 本発明の制御電源の異常処理回路は、マイクロコンピ
ュータに駆動用電力を供給する制御電源と、この制御電
源の異常を監視し、異常が発生した場合に異常検出信号
を前記マイクロコンピュータに送出する監視回路とを有
し、前記異常検出信号によって該マイクロコンピュータ
をリセットするとともに、その異常情報を前記マイクロ
コンピュータに接続したRAMに格納させて制御電源の異
常処理を行うものにおいて、前記監視回路とマイクロコ
ンピュータとの間に、前記異常検出信号を、この異常検
出信号が送出されてから制御電源電圧がマイクロコンピ
ュータが動作可能な下限電圧に低下するまでの時間より
短く、RAMへの異常情報の格納に要する時間より長い時
間だけ遅延させる、遅延回路を介挿してマイクロコンピ
ュータのリセットを遅延させるとともに、この異常検出
信号によって前記マイクロコンピュータに割込み処理を
実行させ、この割込み処理によって前記異常情報をRAM
に格納させて制御電源の異常処理を行うことを特徴とす
るものである。Means for Solving the Problems An abnormality processing circuit of a control power supply of the present invention monitors a control power supply for supplying drive power to a microcomputer and an abnormality of the control power supply, and outputs an abnormality detection signal when an abnormality occurs. A monitoring circuit for sending to the microcomputer, wherein the microcomputer is reset by the abnormality detection signal, and the abnormality information is stored in a RAM connected to the microcomputer to perform abnormality processing of a control power supply. The abnormality detection signal is sent to the RAM between the monitoring circuit and the microcomputer in a time shorter than the time from when the abnormality detection signal is transmitted until the control power supply voltage falls to the lower limit voltage at which the microcomputer can operate. The delay time is longer than the time required to store the abnormal information of the microcontroller. In addition to delaying the reset of the computer, the abnormality detection signal causes the microcomputer to execute interrupt processing.
In which abnormal processing of the control power supply is performed.
作用 上記の如き構成とすることにより、本発明の制御電源
の異常処理回路は、遅延回路によってマイクロコンピュ
ータのリセットを遅延させているので、マイクロコンピ
ュータがリセットされる前に異常情報をRAMに格納させ
ることができる。Operation With the above-described configuration, the abnormality processing circuit of the control power supply of the present invention delays the reset of the microcomputer by the delay circuit, and stores the abnormality information in the RAM before the microcomputer is reset. be able to.
実施例 以下、実施例により説明する。第１図は本発明の制御
電源の異常処理回路のブロック図で、第３図と同じ機能
を有する部分には同じ符号を付して以下の説明は省略す
る。Example Hereinafter, an example will be described. FIG. 1 is a block diagram of an abnormality processing circuit of a control power supply according to the present invention. Parts having the same functions as those in FIG.
第１図のように、本発明は監視回路３とマイクロコン
ピュータ１との間に遅延回路６を介挿して異常検出信号
によるマイクロコンピュータ１のリセットを遅延させる
とともに、前記異常検出信号によってマイクロコンピュ
ータ１に割込み処理を実行させ、この割込み処理によっ
て異常情報をRAM4に格納するものである。従って、第２
図のように、時刻t0で制御電源電圧がV0になった時に送
出される異常検出信号によってRAM4への異常情報の格納
が開始され、その後時刻t2においてマイクロコンピュー
タ１がリセットされる。この場合、時刻t0から時刻t2ま
での時間T2は、時刻t0から時刻t1までの時間T1より短か
く、RAM4への異常情報の格納に要する時間より長くなる
ように遅延回路６の遅延時間を設定し、割り込み処理に
よって確実に異常情報がRAM4に格納されるようにしなけ
ればならない。As shown in FIG. 1, according to the present invention, a delay circuit 6 is interposed between a monitoring circuit 3 and a microcomputer 1 to delay resetting of the microcomputer 1 by an abnormality detection signal. 1 executes an interrupt process, and stores the abnormal information in the RAM 4 by the interrupt process. Therefore, the second
As shown, storage of the abnormality information to the RAM4 by abnormality detection signal sent when the control power supply voltage becomes V 0 at time t 0 is started, the microcomputer 1 is reset in a subsequent time t 2. In this case, the time T 2 from time t 0 to time t 2 is shorter than the time T 1 from time t 0 to time t 1 and longer than the time required for storing the abnormality information in the RAM 4. 6, the delay time must be set so that the abnormality information is stored in the RAM 4 by the interrupt processing.
上記したとおりであるから、本発明は異常情報のRAM4
への格納を確実に行うことができる。As described above, the present invention provides a RAM 4 for abnormal information.
Can be reliably stored.
発明の効果 実施例において詳述した如く、本発明は異常情報の格
納を確実に行うことができるので、正常な状態に復帰し
た後で前記異常情報の処理を容易に行うことができ、信
頼性の向上等に寄与することができる。Effect of the Invention As described in detail in the embodiment, the present invention can reliably store the abnormality information, so that the abnormality information can be easily processed after returning to the normal state, and the reliability can be improved. Can be improved.
第１図は本発明の制御電源の異常処理回路のブロック
図、第２図はそのタイムチャート図、第３図は従来の制
御電源の異常処理回路のブロック図、第４図はそのタイ
ムチャート図である。 １……マイクロコンピュータ、２……制御電源 ３……監視回路、４……RAM ５……バックアップ電源、６……遅延回路1 is a block diagram of a control power supply abnormality processing circuit of the present invention, FIG. 2 is a time chart thereof, FIG. 3 is a block diagram of a conventional control power supply abnormality processing circuit, and FIG. 4 is a time chart thereof. It is. DESCRIPTION OF SYMBOLS 1 ... microcomputer, 2 ... control power supply 3 ... monitoring circuit, 4 ... RAM 5 ... backup power supply, 6 ... delay circuit
Claims (1)
する制御電源と、この制御電源の異常を監視し、異常が
発生した場合に異常検出信号を前記マイクロコンピュー
タに送出する監視回路とを有し、前記異常検出信号によ
って該マイクロコンピュータをリセットするとともに、
その異常情報を前記マイクロコンピュータに接続したRA
Mに格納させて制御電源の異常処理を行う制御電源の異
常処理回路において、前記監視回路とマイクロコンピュ
ータとの間に、前記異常検出信号を、この異常検出信号
が送出されてから制御電源電圧がマイクロコンピュータ
が動作可能な下限電圧に低下するまでの時間より短く、
RAMへの異常情報の格納に要する時間より長い時間だけ
遅延させる、遅延回路を介挿してマイクロコンピュータ
のリセットを遅延させるとともに、この異常検出信号に
よって前記マイクロコンピュータに割込み処理を実行さ
せ、この割込み処理によって前記異常情報をRAMに格納
させて制御電源の異常処理を行うことを特徴とする制御
電源の異常処理回路。1. A control power supply for supplying drive power to a microcomputer, and a monitoring circuit for monitoring an abnormality of the control power supply and transmitting an abnormality detection signal to the microcomputer when an abnormality occurs, Resetting the microcomputer according to the abnormality detection signal,
RA that connected the abnormality information to the microcomputer
In the abnormality processing circuit of the control power supply which stores the data in M and performs the abnormality processing of the control power supply, the abnormality detection signal is transmitted between the monitoring circuit and the microcomputer, and the control power supply voltage is changed after the abnormality detection signal is transmitted. It is shorter than the time until the microcomputer drops to the lower limit voltage at which it can operate,
This microcomputer delays the reset of the microcomputer by interposing a delay circuit that delays by a time longer than the time required for storing the abnormality information in the RAM, and causes the microcomputer to execute an interrupt process by the abnormality detection signal. An abnormality processing circuit for a control power supply, wherein the abnormality information is stored in a RAM to perform an abnormality process for the control power supply.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2127963A JP2638257B2 (en) | 1990-05-16 | 1990-05-16 | Error handling circuit for control power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2127963A JP2638257B2 (en) | 1990-05-16 | 1990-05-16 | Error handling circuit for control power supply |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0423018A JPH0423018A (en) | 1992-01-27 |
| JP2638257B2 true JP2638257B2 (en) | 1997-08-06 |
Family
ID=14973005
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2127963A Expired - Fee Related JP2638257B2 (en) | 1990-05-16 | 1990-05-16 | Error handling circuit for control power supply |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2638257B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005029675A1 (en) * | 2003-09-18 | 2005-03-31 | Hitachi, Ltd. | Backup circuit |
Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59148531A (en) * | 1983-02-08 | 1984-08-25 | 日本電気株式会社 | Power source controller |
| JPS60104944A (en) * | 1983-11-14 | 1985-06-10 | Konishiroku Photo Ind Co Ltd | Automatic developing machine |
| JPS62143153A (en) * | 1985-12-17 | 1987-06-26 | Casio Comput Co Ltd | Controller for central processing unit |
| JPS6315346A (en) * | 1986-07-07 | 1988-01-22 | Nec Corp | Memory protection circuit |
| JPS6354616A (en) * | 1986-08-25 | 1988-03-09 | Mitsubishi Electric Corp | Microcomputer system |
| JP2659067B2 (en) * | 1988-06-08 | 1997-09-30 | 住友電気工業株式会社 | Microcomputer reset circuit |
-
1990
- 1990-05-16 JP JP2127963A patent/JP2638257B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2005029675A1 (en) * | 2003-09-18 | 2005-03-31 | Hitachi, Ltd. | Backup circuit |
| US7376040B2 (en) | 2003-09-18 | 2008-05-20 | Hitachi, Ltd. | Backup circuit for holding information in a storage circuit when power cut-off occurs |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0423018A (en) | 1992-01-27 |
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