JP2860817B2 - PWM controller - Google Patents

Description

The present invention relates to a PWM control device used in a drive circuit of a power supply device such as a copying machine and an LBP (laser beam printer), and particularly relates to the same chip as a CPU. The present invention relates to a PWM control device suitable for being configured as an LSI above.

[Conventional technology]

FIG. 4 is a block diagram showing the configuration of a conventional PWM (pulse width modulation) control device of this kind. In the figure, reference numeral 1 denotes an up / down counter control block, and an up / down counter (hereinafter referred to as U /
The counter output value of the “D counter” is input to the data input terminal of the down counter 3 through the signal line 2.
The counter output value of the down counter 3 is input to a down count value determination circuit 5 through a signal line 4.
The down-count value determination circuit 5 outputs a duty control signal on the signal line 6 in accordance with the count value of the down counter 3 and the data value on the signal line 25, and ends the output of the pulse signal for one cycle. Then, a load signal indicating the start of the next pulse signal formation is output on the signal line 10.

The signal line 6 is connected to a waveform control signal input terminal of a PWM signal generation circuit 7 that outputs a PWM signal.
The signal line 10 is connected to a load signal input terminal of the control block 1 and each of the circuits 3 and 7, respectively. A signal output terminal of the PWM signal generation circuit 7 is connected to a signal output terminal 9 through a signal line 8. The block 3 and the circuits 5 and 7 have the same clock (CLO).
CK), and a clock is input to the clock signal input terminals of the block 3 and the circuits 5 and 7 through the signal line 23.

Reference numeral 22 denotes a CPU signal bus line. Control data for the block 1 and the determination circuit 5 output from the CPU on this bus line is controlled by controlling signals on an address signal line 14 and a strobe signal line 15. CPU registers 13
It is possible to set to. This register 13
Output side of the block 1 through the signal lines 24 and 25 respectively
And a control data input terminal of the determination circuit 5. Further, the reset signal line 16 is connected to the reset signal input terminal of the register 13, and the feedback signal line 41 for transmitting the result of comparing and judging the voltage of the power supply to a reference voltage for comparison and judgment is compared with the input terminal. The block 1 is connected to the U / D control input terminal of the block 1.

 Next, the operation will be described.

At the same time as outputting the first control data on the signal bus line 22, the CPU sends a control signal to the signal lines 14 and 15 and sets the data on the signal bus line 22 to the register 13. This data is captured by the up-down counter control block 1 through the signal line 24 and is also captured by the down-count value determination circuit 5 through the signal line 25. When the load signal is output to the load signal line 10, the output value of the U / D counter of the block 1 is set to the data input terminal of the down counter 3 at the falling edge of the signal. Thereafter, the up / down counter control block 1 determines the data value on the signal line 24 and the state of the feedback signal on the signal line 41, and sets the output value of the U / D counter in the up / down counter control block 1 to "1". One operation is selected and executed from among three operations in which “increase” or “1” decreases or does not increase or decrease. The down counter 3 uses the output value of the U / D counter in the up / down counter control block 1 as its maximum value, and counts the count output value each time the clock on the signal line 23 rises from “0” to “1”. Decrease by "1". Then, the down-count value judging circuit 5 takes in the count output value of the down-counter 3 through the signal line 4 for each clock on the signal line 23, and
The data is compared with the data from 25 to determine the match, and a signal for the required duty is created from the result of the determination and output on the signal line 6. The PWM signal generating circuit 7 generates a rectangular wave having a required duty by using the signals on the signal line 6 and the signal lines 10 and 23, and outputs the rectangular wave to the output terminal 9 through the signal line 8.
Output to Then, the down count value determination circuit 5
When the down counter 3 further counts down and its count output value falls within a certain value range near zero, it outputs a load signal on the signal line 10.

In the device as described above, the reset signal applied to the all clear terminal to initialize the system is connected to the reset signal line to the register 13 as shown in the figure.
Entered directly on 16.

(Problems to be Solved by the Invention) Incidentally, in the conventional PWM control device as described above, the register 13
Are all cleared and the control information up to that point disappears, or abnormal data is set in the register 13. There is a problem that the control of the PWM signal becomes impossible, an abnormal signal is output, and an external circuit element may be destroyed.

The present invention has been made in view of such a problem. Even if abnormal data outside the control range is set in a register, an abnormal signal is not output, and external circuit elements are destroyed. The purpose is to obtain a PWM control device that can prevent the problem.

(Means for Solving the Problems) The PWM control device of the present invention is configured as follows.

I. A PWM signal generating circuit that outputs a PWM signal, a register in which control data of the PWM signal is set, and an output of the PWM signal when the control data set in this register is abnormal data outside the control range. An abnormal signal detection circuit for stopping is provided.

II.PWM signal generating circuit for outputting a PWM signal, a register in which control data of the PWM signal is set, and when the control data set in this register is abnormal data outside the control range, the PWM signal generating circuit An abnormal signal detection circuit for outputting a PWM signal of a predetermined pulse is provided.

[Action]

In the PWM control device of the present invention, when abnormal data outside the control range of the PWM signal is set in the register, the output of the PWM signal is stopped by the abnormal signal detection circuit. In another PWM control device of the present invention, a PWM signal of a predetermined pulse is output when abnormal data is set.

〔Example〕

FIG. 1 is a block diagram showing the configuration of a PWM control device according to an embodiment of the present invention. The same components as those in FIG. 4 are denoted by the same reference numerals, and redundant description is omitted. In the figure, reference numeral 26 denotes an abnormal signal detecting circuit for stopping the output of the PWM signal generating circuit 7 when the control data of the PWM signal set in the register 13 is abnormal data outside the control range. It has a function to detect signals. The abnormal signal detection circuit 26 has an input terminal 28 connected to the signal line 25, and an output terminal 29 connected to a reset signal input terminal 33 of the PWM signal generation circuit 7 through the signal line 27.

In this embodiment, the CPU (not shown) and the PWM control device are configured on the same IC.

FIG. 2 is a circuit diagram showing an example of the internal configuration of the abnormal signal detection circuit 26. This circuit comprises an n-input NOR circuit 30,
an n-input AND circuit 31 and a two-input OR circuit 32;
The input NOR circuit 30 and the n-input AND circuit 31 are connected to a signal line 25 composed of n data bus lines. The output terminals of the n-input NOR circuit 30 and the n-input AND circuit 31 are connected to the input terminals of a two-input OR circuit 32, respectively.
It is connected to the reset signal input terminal 33 of the M signal shaping circuit 7.

Next, the operation will be described. Since the operation of the entire system is the same as that of the circuit of FIG. 4, the case where an abnormal signal is input to the register 13 will be described here. In this case, the abnormal signal is the reset signal to register 13.
When the data in the register 13 becomes all “0” by adding to the register 16, the system runs out of control by the CPU, and the CPU stores all “1” in the register 13 through the signal bus line 22.
Is considered to be set. In the former case, the n-input NOR circuit 30 is used. In the latter case, the n-input AND circuit is used.
31 detects an abnormality in the operation of the system through the signal lines 25 of the n bus lines, and outputs "1" to its output terminal. Then, the result passes through the OR circuit 32 and the signal line
Reset signal input terminal 3 of PWM signal generation circuit 7 through 27
In addition to 3, the output value of the output terminal 9 is fixed at the H (high) level, and output of a pulse signal for PWM control to the output terminal 9 is prohibited.

As described above, even if the abnormal data outside the control range of the PWM signal is set in the register 13, the abnormal signal is not output from the output terminal 9 by the operation of the abnormal signal detecting circuit 26, and the external circuit of the output destination is not output. The device is prevented from being destroyed.

FIG. 3 is a block diagram showing another embodiment of the present invention. Also in this embodiment, the CPU and the PWM control device are configured on the same IC. In this embodiment, a PWM signal of a predetermined pulse is output from the PWM signal generating circuit 7 when the above-mentioned abnormal data is set in the register 13, and a two-input AND circuit 34 is added to the circuit of FIG. EX-OR circuit 3
5 is added. Further, a low-pass filter 37 connected to a power supply circuit, a high-pass filter 38, a control circuit 39, and a CPU 40 are connected to the output side of the EX-OR circuit 35.

One input terminal of the two-input AND circuit 34 is a signal line 27.
And the other input terminal is a signal line 23 for a clock signal.
It is connected to the. One input terminal of the EX-OR circuit 35 is connected to an output terminal of the AND circuit 34 through a signal line 36, and the other input terminal is connected to a signal line 8 from which a signal of the PWM signal generation circuit 7 is output. The output terminal is connected to the output terminal 9.

In the circuit configured as described above, when "1" is output to the signal line 27 by the abnormal signal detection circuit 26, the PWM signal generation circuit 7 is reset, and the output signal is fixed to "1". At the same time that “1” is output to the signal line 8, the clock signal of the signal line 23 is output to the signal line 36 through the AND circuit 34, and as a result, the inverted signal is output from the output terminal 9.

Here, as shown in FIG. 2, the abnormal signal detection circuit 26 can be appropriately changed to a circuit corresponding to a signal on an arbitrary signal line 25 in which the output signal of the output terminal 9 becomes abnormal. Further, as described above, it also has a function of detecting an external control signal. In FIG. 3, the abnormal signal detecting circuit is used.
26 is used as an external control signal detection circuit, and the output terminal 9 of the PWM signal is connected to the input sides of a low-pass filter 37 and a high-pass filter 38. The output terminal of the low-pass filter 37 is connected to the control terminal of the power supply circuit, and the output terminal of the high-pass filter 38 is connected to the input terminal of the control circuit 39. The control circuit 39 is connected to an interrupt detection terminal of the CPU 40.

Normally, the switching power supply receives the PWM signal generated by the PWM signal generation circuit 7 of FIG. 3 through the signal line 8, the EX-OR circuit 35, and the low-pass filter 37, and inputs the power supply circuit. Then, a control feedback signal corresponding to the output voltage of the power supply is output to the signal line 36, and the power supply is controlled by PWM control.

Although the control operation of the power supply is well known, the description thereof will be omitted.However, when the CPU 40 stops the power supply operation under the above-described conditions and switches the control from the power supply control to another control after a certain time, the CPU 40 uses Data detectable by the external control signal is set in the register 13 through the line 22. Then, when the abnormal signal detection circuit 26 detects this, the signal line
By setting the output to 27 to "1", the clock on the signal line 23 is output to the output terminal 9 through the two-input AND circuit 34, the signal line 36, and the EX-OR circuit 35. This clock signal is
The signal passes through the high-pass filter 38 as it is and is input to the clock signal input terminal of the control circuit 39. At this time, the control circuit 39
If a timer means or the like is provided in the control circuit 39, the control circuit 39 can interrupt the CPU 40 after a certain period of time, thereby triggering another control operation. Further, the clock signal is supplied to a low-pass filter 37.
, The output thereof becomes L (low level), and the operation of the power supply circuit stops.

As described above, when the control data of the register 13 is data outside the control range, the abnormality detection circuit 26 outputs a high-frequency pulse signal capable of driving an external power supply circuit or a PWM signal of a predetermined pulse such as a clock signal of the CPU 40. Therefore, even if the data on the register 13 changes due to runaway of the CPU 40 or external noise, the pulse signal input to the driven circuit of the PWM control device stops or the driven circuit cannot respond. By applying the high-frequency pulse, it is possible to prevent the driven circuit from outputting an abnormally high voltage and destroying circuit elements. In addition, by connecting the above-described circuit for detecting a high-frequency pulse (high-pass filter 38) to the output terminal 9, a recovery function for externally diagnosing an abnormal state, interrupting the CPU 40, and restarting the CPU 40 is added. Is possible.
Furthermore, by performing the control by using a counter circuit or the like using the clock signal output from the output terminal 9 as a clock, control synchronized with the CPU 40 can be easily executed.

[Effects of the Invention] As described above, according to the present invention, when data outside the control range of the PWM signal is set, the output of the PWM signal is stopped, and the PWM signal of a predetermined pulse is output. Thus, there is an effect that an abnormal signal is not output and the external circuit element can be prevented from being destroyed.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of an internal configuration of the abnormality detection circuit of FIG. 1,
FIG. 3 is a block diagram showing another embodiment of the present invention, and FIG. 4 is a block diagram showing a circuit configuration of a conventional device. 7 PWM signal generation circuit 9 Output terminal 13 Register 26 Abnormal signal detection circuit

Claims (2)

(57) [Claims] 1. A PWM signal generating circuit for outputting a PWM signal, a register in which control data of the PWM signal is set, and the PWM signal when control data set in the register is abnormal data outside a control range. A PWM control device comprising an abnormal signal detection circuit for stopping output of the PWM signal. 2. A PWM signal generating circuit for outputting a PWM signal, a register in which control data of the PWM signal is set, and the PWM signal when the control data set in the register is abnormal data outside the control range. A PWM signal control device comprising an abnormal signal detection circuit for outputting a PWM signal of a predetermined pulse from a generation circuit.