JP2000032770A - Inverter device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reliably prevent switching elements connected in series from being turned on simultaneously when restarted after the stop of operation. SOLUTION: A series circuit of a pair of switching elements Q1, Q2 is connected to a DC power source Vdc, and both switching elements Q1, Q2 are turned on and off alternately. The drive signal of the switching elements Q1, Q2 are generated by passing the control signal of square-wave signals outputted from a control signal generating circuit 1 through drive circuits 2, 3. If an abnormality detecting circuit 9 detects an abnormality when the switching element Q1 is turned on, a stop controlling circuit 10 turns off the switching element Q1 when the control signal falls next.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an inverter for converting a DC voltage into a high-frequency voltage.

[0002]

2. Description of the Related Art As shown in FIG. 8, a conventionally provided inverter device includes a pair of switching elements Q1 and Q2.
Many include a series circuit of Q2. In this inverter device, a series circuit of switching elements Q1 and Q2 is connected between both ends of a DC power supply Vdc, and both switching elements Q1 and Q2 are connected.
2 are alternately turned on and off, so that the potential at the connection point (output terminal OUT) between the two switching elements Q1 and Q2 is alternately changed to the positive potential and the negative potential of the DC power supply Vdc. Therefore, the potential at one end of the load circuit connected to the output terminal OUT alternates between the positive potential and the negative potential of the DC power supply Vdc, and when the potential at one end of the load circuit is the positive potential, the potential at the other end of the load circuit changes. If the potential is set to a relatively low potential and the potential at the other end of the load circuit is set to a relatively high potential when the potential at one end of the load circuit is the negative potential, an alternating current can flow through the load circuit. As a circuit configuration in which the potential at the other end of the load circuit has the above-described relationship, the switching element Q1,
A circuit that forms a bridge circuit with Q2 (full bridge type), a circuit that forms a bridge circuit with switching elements Q1 and Q2 using a series circuit of a pair of capacitors (half bridge type), a series circuit of a load circuit and a capacitor A device connected in parallel to one of the switching elements Q1 and Q2 (half-bridge type) is known.

By the way, drive signals S9 and S11 for turning on and off the switching elements Q1 and Q2 include a square wave control signal S1 as shown in FIG.
, And is generated by giving a control signal to the drive circuits 2 and 3. Since the source potential of the switching element Q2 on the low potential side of the DC power supply Vdc is the negative potential of the DC power supply Vdc, the reference potential of the drive circuit 3 is also the negative potential of the DC power supply Vdc. And the same potential as. In other words, the drive signal S11 (FIG. 9 (k)) of the switching element Q2 changes the control signal S1 to NO.
After being inverted through the T circuit 4, it is generated by passing through the drive circuit 3 composed of a buffer.

On the other hand, since the source potential of the switching element Q1 on the high potential side of the DC power supply Vdc changes depending on the on / off state of the switching element Q2, the reference potential of the drive signal S9 (FIG. 9 (i)) output from the drive circuit 2 Must be matched to the source potential of the switching element Q1. Therefore, a level shift circuit 5 is provided in the drive circuit 2. That is, the rising edge and the falling edge of the control signal S1 output from the control signal generation circuit 1 are detected by the edge detection circuits 6a and 6b, respectively, and FIG.
The edge signals S4 and S5 as shown in FIG. 9E are generated, and the edge signals S4 and S5 are passed through the level shift circuit 5, whereby the set signal S6 and the reset signal s7 as shown in FIGS. And generate Level shift circuit 5
Is a pair of switching elements SH composed of MOSFETs.
1 and SH2, and resistors R1 and R2 connected to the drains of the switching elements SH1 and SH2, respectively. Each switching element SH1, SH2 and each resistor R1,
The series circuit with R2 is connected to a control power supply HVcc which is a separate power supply from the DC power supply Vdc.

The set signal S6 and the reset signal S7 output from the level shift circuit 5 are input to an RS flip-flop 7. That is, by inputting the set signal S6 and the reset signal S7, which are respectively generated in response to the rising edge and the falling edge of the control signal, to the RS flip-flop 7, the RS flip-flop 7 outputs the signal shown in FIG. As described above, the rectangular wave signal S8 having substantially the same shape as the control signal S1 can be generated. This square wave signal S8
Is passed through the buffer 8 to obtain a drive signal S9 as shown in FIG. 9 (i). However, RS
The flip-flop 7 and the buffer 8 have a control power supply H
Since the power is supplied by Vcc and the reference potential of the RS flip-flop 7 and the buffer 8 is matched with the source potential of the switching element Q1, the driving signal S9 is a signal using the source potential of the switching element Q1 as the reference potential. become.

By the way, when any abnormality occurs in the inverter device or the load circuit, it is necessary to stop the operation of the inverter device to prevent the inverter device from being destroyed. Therefore, an abnormality detection circuit 9 is provided to detect this kind of abnormality. When the abnormality detection circuit 9 is normal, the output S2 is set to the H level as shown in FIG. 9B, and when the abnormality is abnormal, the output S2 is set to the L level. It is configured so that Also,
In order to stop the operation of the inverter device in the event of an abnormality, AND circuits 11 and 12 as gate circuits that are opened and closed by the output S2 of the abnormality detection circuit 9 are provided at the input terminals of the driving circuits 2 and 3. That is, the output of the control signal generation circuit 1 is input to the drive circuit 2 through the AND circuit 11, and
The output of the OT circuit 4 is supplied to the drive circuit 3 through the AND circuit 12.
Is input to As a result, as shown in FIG.
In the case where an abnormality occurs, the inputs S3 and S10 to the drive circuits 2 and 3 thereafter become L level as shown in FIGS. 9C and 9J, and both the switching elements Q1 and Q2 are turned off.

The edge detection circuits 6a and 6b in the circuit shown in FIG. 8 detect the rising or falling of the input signal and generate a set signal or a reset signal having a short pulse width. As shown,
The configuration includes a delay circuit for defining the pulse width. FIG. 10 shows an edge detection circuit 6b for detecting a falling edge. The delay circuit includes a resistor R3 and a capacitor C3.
3 and a NOT circuit 13. The NOR circuit 14 is configured to input a signal obtained by passing an input signal through a delay circuit and an input signal to a NOR circuit 14 and to output a NOT of a logical sum. Therefore, when the rectangular wave signal S3 as shown in FIG. 11A is input, the potential S12 at the connection point between the resistor R3 and the capacitor C3 is changed to the input rectangular wave signal S3 as shown in FIG. The rise and fall are inclined. By inputting this signal to the NOT circuit 13, FIG.
As shown in (c), a rectangular wave signal S13 obtained by delaying and inverting the input signal is obtained.
Numeral 5 is a pulse signal which is generated at the falling point of the input signal as shown in FIG. 11D and has a pulse width corresponding to the delay time of the delay circuit.

To generate such a pulse signal,
It is necessary that the level of the input signal be kept unchanged for a certain period of time (a time sufficiently longer than the time constant of the delay circuit) before the point in time when the level of the input signal changes.

For example, when the input signal S3 is as shown in FIG. 12A, the capacitor C3 is not sufficiently charged, and therefore the potential S at the connection point between the resistor R3 and the capacitor C3 is obtained.
12 changes as shown in FIG.
Cannot be reached. As a result, as shown in FIG. 12C, the output S13 of the NOT circuit 13 is kept at the H level, and the edge detection circuit 6b cannot output a pulse signal corresponding to the falling edge.

The state as shown in FIG. 12 occurs when the period of the H level of the input signal to the edge detection circuit 6b is short, and more specifically, the control signal output from the control signal generation circuit 1 Corresponds to the case where the output of the abnormality detection circuit 9 falls immediately after the rise of the signal. That is, since the edge detection circuit 6a detects the rising edge of the control signal, the switching element Q1 is turned on, and thereafter, the control is stopped without detecting the falling edge.
1 will be kept on.

If the switching element Q1 is kept on after the abnormality is detected, the switching element Q2 is turned on when the abnormality is released and the output of the abnormality detecting circuit 9 returns to the H level. And both switching elements Q1 and Q2 are turned on at the same time. That is, when both switching elements Q1 and Q2 are turned on at the same time, both ends of DC power supply Vdc are short-circuited, and an excessive current may flow through both switching elements Q1 and Q2.

As described above, when the abnormality is detected by the abnormality detection circuit 9 immediately after the switching element Q1 is turned on, the switching element Q1 cannot be turned off in addition to the time delay generated in the edge detection circuit 6b. There may be a case where a time delay generated in the level shift circuit 5 is a cause.

To solve the above problem, FIG.
As shown in FIG. 3, a configuration in which the power of the drive circuit 2 is supplied by a capacitor Cb has been considered. That is, the power supply LVcc having a relatively low voltage is smoothed by the smoothing capacitor Ca, and a series circuit of the diode Db and the capacitor Cb is inserted between the positive terminal of the smoothing capacitor Ca and the connection point between the two switching elements Q1 and Q2. Thus, a configuration is considered in which the capacitor Cb is charged according to the on / off state of the switching element Q2.

In this configuration, if the inverter device stops and the switching element Q2 turns off, the capacitor Cb
Is stopped, the capacitor Cb is discharged through the drive circuit 2, and the voltage of the control power supply HVcc also decreases. Therefore, it is necessary to add a circuit for monitoring the voltage drop of the control power supply HVcc and for forcibly changing the drive signal from the drive circuit 2 to the switching element Q1 to L level to turn off the switching element Q1 when the voltage drops below a predetermined voltage. Thus, it is possible to prevent the switching element Q1 from being kept on after the inverter device is stopped.

[0015]

However, even if the above configuration is adopted, it takes time for the voltage across the capacitor Cb to decrease, so that the switching element Q1 is kept on when the inverter device stops operating. afterwards,
When the abnormality is removed by the time the switching element Q1 is turned off due to a decrease in the voltage across the capacitor Cb and the inverter device is restarted, the switching elements Q1, Q2
May be turned on at the same time.

The present invention has been made in view of the above circumstances, and an object of the present invention is to provide an inverter device that reliably prevents switching elements connected in series from being simultaneously turned on when restarting after an operation is stopped. Is to provide.

[0017]

The invention according to claim 1 includes a series circuit of a pair of switching elements connected between both ends of a DC power supply, and the two switching elements are connected alternately by turning on and off. An inverter device that alternately switches a potential of a point between a positive potential and a negative potential of a DC power supply, and a control signal generation circuit that generates a control signal that is a rectangular wave signal that is a reference for turning on and off both switching elements. A first drive circuit for generating a drive signal for the switching element on the high potential side from the control signal, a second drive circuit for generating a drive signal for the switching element on the low potential side from the control signal, An abnormality detection circuit that instructs the first and second drive circuits to turn off both switching elements, and an abnormality detected by the abnormality detection circuit. Both switching elements after the instruction of OFF is applied to the switching element having a high potential side is intended and a stop control circuit for controlling the timing to turn off during detection.

According to a second aspect of the present invention, in the first aspect of the present invention, the first drive circuit includes a pair of edge detection circuits for detecting a rising edge and a falling edge of the control signal, respectively, It comprises a level shift circuit for converting the output into a signal potential for the switching element on the high potential side, and an RS flip-flop using each output of the level shift circuit as a set signal and a reset signal.

According to a third aspect of the present invention, in the first or second aspect of the present invention, the stop control circuit waits until the control signal is inverted next when the high-potential side switching element is turned on. The switching element on the potential side is turned off.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The basic configuration of the embodiment described below is the same as that of the circuit described as the prior art shown in FIG. 8, and the components having the same functions are denoted by the same reference numerals. Is omitted.

(Embodiment 1) As shown in FIG. 1, the point different from the conventional configuration shown in FIG. 8 is that the output from the abnormality detection circuit 9 is not directly input to the AND circuit 11 but the OR circuit 15 is used. Stop control circuit 1 including a filter circuit 16
0 is input to the AND circuit 11. O
The other input of the R circuit 15 is the control signal output from the control signal generation circuit 1. The filter circuit 16 includes a resistor R4
And a diode D4 connected in parallel with the resistor R4. When the output of the OR circuit 15 is at the H level, the capacitor C4 is charged via the resistor R4. When the level becomes L level, the charge of the capacitor C4 is discharged through the diode D4. Also, this filter circuit 16
Is the connection point between the resistor R4 and the capacitor C4 and is connected to the AND circuit 11.

The OR shown in the circuit shown in FIG.
The circuit 15 and the filter circuit 16 are shown in FIGS.
The function of delaying the fall of the output (FIG. 2B) from the abnormality detection circuit 9 until the fall of the control signal S1 is provided. That is, since the control signal S1 is input to the OR circuit 15 in addition to the output of the abnormality detection circuit 9,
Immediately after the control signal S1 rises to the H level as shown in FIG. 2A, the output S of the abnormality detecting circuit 9 is outputted as shown in FIG.
2 falls, as shown in FIG.
5 is maintained at H level until the fall of the control signal S1. Thereafter, when the output of the OR circuit 15 falls to the L level, the electric charge of the capacitor C4 is immediately released via the diode D4, and the resistance R as shown in FIG.
That is, the potential at the connection point between the capacitor 4 and the capacitor C4 becomes L level. Here, when the control signal S1 goes high, the potential S15 at the connection point between the resistor R4 and the capacitor C4 slightly increases, but the filter circuit 16 connects the resistor R4 and the capacitor C4 during the period when the control signal S1 is at the high level. The potential S15 at the connection point is set so as not to exceed the threshold value of the AND circuit 11.

As a result, even if the abnormality is detected by the abnormality detection circuit 9 at the time t1, the output S3 of the AND circuit 11 remains low until the control signal S1 falls as shown in FIG.
Since the timing is controlled by the stop control circuit 10 so as not to reach the level, even if a delay occurs in the edge detection circuit 6b or the level shift circuit 5, the switching element Q1 can be reliably turned off. In FIG. 2, (f) to (k) indicate the output S4 of the edge circuit 6a, the output S5 of the edge circuit 6b, and the set signal S6, respectively.
Reset signal S7, drive signal S for switching element Q1
9, a drive signal S11 for the switching element Q2. Other configurations and operations are the same as those of the tenth embodiment.

(Embodiment 2) In this embodiment, as shown in FIG. 3, a control signal generation circuit 1
Between the NOT circuit 17a, 1 and the AND circuit 11
7B is inserted, and a D flip-flop 18 is used instead of the OR circuit 15 and the filter circuit 16. That is, the stop control circuit 10 includes the NOT circuits 17a and 17b and the D flip-flop 18.
The D flip-flop 18 is such that the output of the abnormality detection circuit 9 is input to the data terminal D, and the control signal is input to the clock terminal C. The output of the NOT circuit 17b and the output of the D flip-flop 18 are input to the AND circuit 11.

One input to the AND circuit 11 is two N
Since the signal passes through the OT circuits 17a and 17b, it is delayed, and the control signal S1 shown in FIG.
A signal S16 as shown in (b) is input to the AND circuit 11. 4C, when the output of the abnormality detection circuit 9 becomes L level at the time t1, the input to the data terminal D of the D flip-flop 18 becomes L level, but the output of the data terminal D becomes D level. Since the output of the flip-flop 18 is reflected at the time of the rise of the control signal S1, the output signal of the abnormality detection circuit 9 until the next rise of the control signal S1 after the fall of the output S2 of FIG. , The output S17 of the D flip-flop 18 is kept at the H level. As a result, the output of the abnormality detection circuit 9 changes with the AND circuit 11.
The timing at which one of the input terminals becomes L level is determined by AND
This is a period during which the input to the other input terminal of the circuit 11 (the output of the NOT circuit 17b) is at the L level. That is, since the output change of the abnormality detection circuit 9 is reflected on the output of the AND circuit 11 during the off period of the switching element Q1, it is possible to prevent the switching element Q1 from being kept on when the inverter device is stopped. In addition, FIG.
(H) shows the output S3 of the AND circuit 11, the output S4 of the edge detection circuit 6a, and the output S4 of the edge detection circuit 6b, respectively.
5, a drive signal S9 to the switching element Q1. Other configurations and operations are the same as those of the first embodiment.

(Embodiment 3) In the present embodiment, as shown in FIG. 5, not only the non-inverted output but also the inverted output of the D flip-flop 18 is used in the configuration of the second embodiment. That is, the NOR circuit 19 is used instead of the AND circuit 12 in the second embodiment,
, The inverted output of the D flip-flop 18 and the output of the NOT circuit 17b are input. Therefore, the NOT circuit 4 becomes unnecessary. The operation according to this configuration is almost the same as that of the second embodiment.
A control signal S1 as shown in FIG.
The control signal is delayed by the circuits 17a and 17b, as shown in FIG.
A signal S16 as shown in FIG. On the other hand, when the output S2 of the abnormality detection circuit 9 falls at the time t1 as shown in FIG. 6C, when the control signal S1 rises next, FIG.
The non-inverted output S of the D flip-flop 18 as shown in FIG.
18 falls, and at the same time, the inverted output S19 of the D flip-flop 18 rises as shown in FIG. NOR circuit 1
9 outputs a rectangular wave signal S10 as shown in FIG. 6 (i) because the output of the NOT circuit 17b is inverted during the period when the inverted output of the D flip-flop 18 is at the L level. The signal S10 is used as a drive signal S11 through the drive circuit 3 to drive the switching element Q2. FIGS. 6F to 6H respectively show the AND circuit 1
1 shows an output S3, an output S5 of the edge detection circuit 6b, and a drive signal S9 of the switching element Q1. In this embodiment,
After the abnormality detection circuit 9 detects an abnormality, the switching element Q
2 is different from the other embodiments in that it is turned on once, then turned off, and then stopped.

In each of the embodiments described above, no pause period is provided between the on and off of the switching elements Q1 and Q2, but as shown in FIG.
1, Q2 when switching on and off
Period during which 1 and Q2 are simultaneously turned off (dead time DT)
May be provided. When the dead time DT is provided as described above, the dead time D is added to the configuration of each embodiment described above.
It is only necessary to add a configuration for generating T.

[0028]

The invention of claim 1 includes a series circuit of a pair of switching elements connected between both ends of a DC power supply,
An inverter device in which both switching elements are alternately turned on and off to alternately switch a potential at a connection point between the two switching elements to a positive potential and a negative potential of a DC power supply, and serve as a reference for turning on and off the two switching elements. A control signal generation circuit for generating a control signal that is a rectangular wave signal, a first drive circuit for generating a drive signal for a high-potential side switching element from the control signal, and a drive signal for a low-potential side switching element from the control signal Second to generate
Drive circuit, an abnormality detection circuit that instructs the first and second drive circuits to turn off both switching elements when an abnormality occurs, and a high potential side switching element when the abnormality detection circuit detects an abnormality. And a stop control circuit that controls the timing so that both switching elements are turned off after the instruction is given. Since the element is turned off, the operation of both switching elements does not stop while the switching element on the high potential side remains on as in the conventional configuration,
There is an advantage that a short circuit of the DC power supply due to simultaneous conduction of both switching elements at the time of recovery from the abnormality can be reliably prevented.

According to a third aspect of the present invention, in the first or second aspect of the present invention, the stop control circuit waits until the control signal is inverted next when the high-potential side switching element is turned on. This ensures that the drive signal for turning off the high-potential side switching element is ensured even if the abnormality detection circuit detects an abnormality immediately after the high-potential side switching element is turned on. The switching element on the high potential side can be turned off in a relatively short time within a half cycle of the control signal from the occurrence of the abnormality.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a first embodiment of the present invention.

FIG. 2 is an operation explanatory view of the above.

FIG. 3 is a circuit diagram showing a second embodiment of the present invention.

FIG. 4 is an operation explanatory view of the above.

FIG. 5 is a circuit diagram showing a third embodiment of the present invention.

FIG. 6 is an operation explanatory view of the above.

FIG. 7 is an explanatory diagram showing another operation example of the present invention.

FIG. 8 is a circuit diagram showing a conventional example.

FIG. 9 is an operation explanatory view of the above.

FIG. 10 is a main part circuit diagram of the same.

FIG. 11 is an operation explanatory diagram of the above.

FIG. 12 is an operation explanatory view of the above.

FIG. 13 is a main part circuit diagram showing another conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Control signal generation circuit 2 Drive circuit 3 Drive circuit 5 Level shift circuit 6a, 6b Edge detection circuit 7 RS flip-flop 9 Abnormality detection circuit 10 Stop control circuit Q1, Q2 Switching element Vdc DC power supply

Claims (3)

[Claims] A DC power supply includes a series circuit of a pair of switching elements connected between both ends of the DC power supply, and by alternately turning on and off the switching elements, a potential at a connection point of the switching elements is set to a positive potential and a negative potential of the DC power supply. An inverter device that alternately switches between a potential and a potential, a control signal generation circuit that generates a control signal that is a rectangular wave signal that is a reference for turning on and off both switching elements, and a switching element on a high potential side from the control signal. And a second drive circuit for generating a drive signal for a low-potential side switching element from the control signal, and a second drive circuit for turning off both switching elements when an abnormality occurs. An abnormality detection circuit for instructing the first and second drive circuits, and a high-potential side switching element when an abnormality is detected by the abnormality detection circuit. A stop control circuit that controls timing so that both switching elements are turned off after an instruction to turn off is given to the child. 2. A first drive circuit comprising: a pair of edge detection circuits for detecting a rising edge and a falling edge of a control signal, respectively; and a signal to a high-potential side switching element for outputting an output of each edge detection circuit. 2. The inverter device according to claim 1, further comprising: a level shift circuit that converts the potential into a potential; and an RS flip-flop that uses each output of the level shift circuit as a set signal and a reset signal. 3. The stop control circuit according to claim 1, wherein when the high-potential side switching element is on, the stop control circuit turns off the high-potential side switching element until the control signal is inverted next time. The inverter device according to claim 1 or 2.