JPH07312897A - Fault detector - Google Patents

Abstract

PURPOSE:To prevent the operational instability of a motor due to an erroneous operation by continuously outputting a drive signal from an oscillator to the motor if the rise of next pulse is not detected without a predetermined time from the rise of the pulse after a PWM signal is stopped. CONSTITUTION:When noise is generated at B of an IC 6, the IC 6 is reset, and a high level signal is not output from Q<-> of the IC 6 at least only for a first predetermined time. In this case, the delay time of a second time constant circuit 8 is set to longer time than the first predetermined time. That is, if next pulse is not input to the B without the first predetermined time from the generation of the noise, the circuit 8 is discharged, and the noise is generated before it becomes a threshold voltage or less, and hence the first predetermined time is elapsed, and the high level signal is again output from the Q<-> of the IC 6. The noise is also input to the B of an IC 9, but since an input signal of A<-> of the IC 9 is high at that time point, it does not affect influence from the Q<-> to the output signal.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention detects PW by detecting a failure of an ECU or the like which outputs a PWM signal for driving a motor.
The present invention relates to a failure detection device for outputting a predetermined pulse signal to the motor side to guarantee a minimum operation when the M signal stops, and particularly when a PWM signal is output again after it is determined to be a failure, The present invention relates to a failure detection device of the type that returns to control.

[0002]

2. Description of the Related Art Conventionally, for example, a PWM signal has been used to drive a motor, but when the ECU or the like which generates this PWM signal fails for some reason and the output of the signal stops, the motor stops. Not to do
There has been proposed a failure detection circuit that outputs a drive signal with a predetermined duty ratio to a motor side from a separate oscillation circuit when it is detected that the PWM signal has stopped, thereby ensuring a minimum operation. This is to always detect the rising edge of the pulse of the PWM signal, prohibit the output of the drive signal from the oscillation circuit if the next rising edge is detected within a predetermined time from the previous rising edge, and If is not detected, the oscillator circuit outputs the drive signal pulse signal.

[0003]

However, in the failure detection circuit as described above, when the PWM signal is stopped and the pulse signal is output from the oscillation circuit, the rising edge of the pulse is detected again. It is determined that the PWM signal is output again, and the output of the drive signal from the oscillation circuit is stopped for at least the predetermined time. Therefore, for example, when a pulse rises due to noise, the pulse signal is intermittently output from the oscillation circuit, which causes a problem that the operation of the motor becomes unstable.

Further, it is conceivable that once the control by the oscillation circuit is performed, the PWM signal and the pulse signal from the oscillation circuit are continuously output even if the PWM signal is output again. It is not realistic because a device for completely switching is required separately and there is a problem that it is troublesome to restore the PWM signal when it is restored to a normal state.

The present invention has been made in view of the above problems of the prior art, and its main purpose is to output a drive signal having a predetermined duty ratio from an oscillation circuit when the output of a PWM signal is stopped, and Provided is a failure detection circuit that can stop the drive signal from the oscillation circuit when the PWM signal is output again, and does not stop the drive signal from the oscillation circuit even if noise occurs when the PWM signal output is stopped. To do.

[0006]

SUMMARY OF THE INVENTION According to the present invention, the above-mentioned object is achieved by providing P from PWM signal output means for driving a motor.
When the WM signal is stopped, it is determined that there is a failure, a drive signal having a predetermined duty ratio is output to the motor side, and when the PWM signal from the PWM signal output means is output, the predetermined pulse is output. A failure detection circuit for stopping the output of a signal, which outputs the first detection signal when it is detected that the pulse of the PWM signal has stopped for a first predetermined time or more, and the first signal when the PWM signal is detected again. First detection means for stopping the output of the detection signal, and while the first detection signal is being output from the first detection means and after the first detection signal has stopped Second detection means for outputting a second detection signal until a second predetermined time, which is longer than the predetermined time, and the predetermined detection time while the second detection signal is being output from the second detection means. The du It is achieved by providing a fault detection circuit further comprising a driving signal outputting means for outputting a driving signal of the duty ratio to the motor side.

[0007]

With this configuration, after the PWM signal is stopped, if the rising edge of the next pulse is not detected within the first predetermined time from the rising edge of the previous pulse, that is, if the pulse is not continuously detected, oscillation occurs. Since the drive signal from the circuit is continuously output to the motor side, there is no concern that the drive signal from the oscillation circuit will be inadvertently stopped by noise and the operation of the motor will become unstable.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings.

FIG. 1 shows a main part of a drive / control circuit of a motor to which the present invention is applied. The motor 1 is driven / controlled via the pre-driver circuit 3 and the driving transistor TR1 based on a PWM signal determined by the ECU 2 from input information (not shown).

On the other hand, the PWM signal output from the ECU 2 is input to the B input terminal of the flip-flop IC6 as the first detecting means in the failure detecting circuit 5 via the inverter. In addition to the B input terminal, this IC6 has a reset input terminal (RST) and a grounded A terminal.
￣ input terminal, RX / CX terminal, CX terminal and Q￣ output terminal are provided, and RX / CX terminal and CX terminal are resistors R1
And a first time constant circuit 7 including a capacitor C1
Is connected to the reset input terminal (RST) via. This IC 6 outputs a Q output until the next pulse input to the B input terminal after the first predetermined time set by the time constant circuit 7 after the pulse input of the PWM signal is not input to the B input terminal. First from the terminal
The detection signal of is output. When the pulse rising edge is input to the B input terminal, the output of the first detection signal is stopped.

The Q output terminal of IC6 is connected to the A input terminal of IC9 as the second detecting means via a second time constant circuit 8 composed of a resistor R2 and a capacitor C2. That is, the first detection signal output from the Q-output terminal of IC6 is delayed by the second predetermined time determined by the resistor R2 and the capacitor C2, and the first detection signal is delayed by A-of IC9.
It is input to the input terminal.

The IC 9 has an input terminal and an output terminal similar to those of the IC 6, and a PWM signal from the ECU 2 is input to the B input terminal of the IC 9 similarly to the B input terminal of the IC 6. In addition, the RX / CX terminal and the CX terminal are resistors R
The third time constant circuit 10 is composed of the capacitor 3 and the capacitor C3. If the A input terminal of this IC 9 is low, and the pulse rising of the PWM signal is not input to the B input terminal for the third predetermined time set by the time constant circuit 10, the next A input will be input. The second detection signal is output from the Q output terminal until the terminal is low and the rising pulse is input to the B input terminal.

The Q output terminal of the IC 9 is connected to the oscillator circuit 11. The oscillator circuit 11 is a circuit for outputting a pulse signal for driving a motor so that the duty ratio is 50%, for example, while the second detection signal from the Q output terminal of the IC 9 is input.

The operating procedure of this embodiment will be described below with reference to the time chart of FIG.

First, while the PWM signal is continuously output from the ECU 2, the timer of the IC 6 is always cleared, and the high level signal from the Q output terminal of the IC 6 as the first detection signal is not output. Then, as shown in the position A, the PWM signal from the ECU 2 is stopped and the resistance R1
After a lapse of a first predetermined time set by the first time constant circuit 7 including the capacitor C1 and the capacitor C1, a high level signal is output from the Q-output terminal of the IC 6 as shown in the position B. As a result, the second time constant circuit 8 is charged and the input signal of the A input terminal of the IC 9 becomes high.
Then, after the PWM signal from the ECU 2 is stopped, the third
When the third predetermined time set by the time constant circuit 11 has elapsed, a high level signal is output from the Q-output terminal of the IC 9 and the motor 1 is driven by the drive signal of the oscillator circuit 11. Here, in IC6 and IC9, when the input signal of the A input terminal is low and the input signal of the B input terminal has no rising edge of the input signal, the output signal of the Q output terminal is output after a predetermined time by the above time constant circuits. It is a flip-flop that changes the signal level.

In this state, as shown in position D, B of IC6
When noise occurs at the input terminal, the IC6 is reset and the high level signal is not output from the Q-output terminal of the IC6 for at least the first predetermined time. here,
The delay time (second predetermined time) of the second time constant circuit 8 is set to be slightly longer than the first predetermined time. That is, the next pulse is B from the position D within the first predetermined time.
If not input to the input terminal, the second time constant circuit 8 is discharged from the position D to the first voltage before reaching the threshold voltage (SH) or less.
After a predetermined time has passed, a high level signal is output again from the Q-output terminal of IC6 (position E). Also, the above noise is simultaneously input to the B input terminal of IC9,
At that time, since the input signal of the A input terminal of the IC 9 is high, it does not affect the output signal from the Q output terminal.

Therefore, when the PWM signal from the ECU 2 is stopped and the first predetermined time elapses, the motor 1 is driven by the pulse signal of the oscillation circuit 11, and thereafter within the first predetermined time. Unless a plurality of pulses are input to the B input terminal of the IC 6, that is, unless a continuous (pulse) signal is output from the ECU 2, the motor 1
Is driven by the drive signal of the oscillation circuit 11.

[0018]

As is apparent from the above description, according to the failure detection circuit of the present invention, the first detection signal is output when it is detected that the pulse of the PWM signal has stopped for the first predetermined time or longer. And the second detection signal while the first detection signal is being output and after the first detection signal is stopped until a second predetermined time longer than the first predetermined time elapses. And a drive signal output means for outputting a drive signal having a predetermined duty ratio to the motor side while the second detection signal is being output from the second detection means. Therefore, after the PWM signal is stopped, if the rising edge of the next pulse is not detected within the first predetermined time from the rising edge of the previous pulse, that is, if the pulse is not continuously detected, the drive signal with the predetermined duty ratio is set. Motor side From continuing to output, it can prevent unstable operation of the motor due to noise.

[Brief description of drawings]

FIG. 1 is a main part of a drive / control circuit of an electric power steering motor for an automobile to which the present invention is applied.

FIG. 2 is a time chart explaining the operation of the circuit of FIG.

[Explanation of symbols]

 1 Motor 2 ECU 3 Pre-driver Circuit 5 Failure Detection Circuit 6 IC 7 First Time Constant Circuit 8 Second Time Constant Circuit 9 IC 10 Third Time Constant Circuit 11 Oscillation Circuit

Claims (1)

[Claims] 1. When the PWM signal from the PWM signal output means for driving the motor is stopped, it is determined that there is a failure, a drive signal having a predetermined duty ratio is output to the motor side, and the PWM signal output means is provided. Is a failure detection circuit that stops the output of the predetermined pulse signal when the PWM signal is output, and the first detection is performed when the pulse of the PWM signal is stopped for a first predetermined time or more. A first detection unit that outputs a signal and stops the output of the first detection signal when the PWM signal is detected again; and while the first detection signal is output from the first detection unit, and Second detection means for outputting a second detection signal until a second predetermined time longer than the first predetermined time has elapsed after the first detection signal is stopped; and the second detection means. And a drive signal output means for outputting a drive signal having the predetermined duty ratio to the motor side while the second detection signal is being output from the failure detection circuit.