JPH0698574A - Motor driving circuit - Google Patents

Abstract

PURPOSE:To provide a motor driving circuit which facilitates a regenerative braking, reduction of heat generation, dealing with a reverse connection of a power supply and reduction of the size. CONSTITUTION:An FET 1 is connected to a motor 2 in series. A thyristor 4 is connected to the motor 2 in parallel. A first delay circuit 5 generates a first delay time which is longer than a time required to turn off the thyristor 4 completely. When an operation switch 3 is closed and a switching signal is turned on, ON/OFF of the FET 1 is controlled through the first delay circuit 5. On the other hand, when the operation switch 3 is opened and the switching signal is turned off, ON/OFF of the FET 1 is controlled through the second delay circuit 6 which generates a second delay time. With this constitution, at the time of start, the FET 1 is turned on after the thyristor 4 is completely turned off by the first delay time and, at the time of stop, the thyristor 4 is turned on after the FET 1 is turned off, so that a power supply short-circuit state between the FET 1 and the thyristor 4 can be avoided.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a motor drive circuit, and more particularly to a motor drive circuit in which an FET connected in series to the motor drives the motor and a thyristor connected in parallel to the motor can perform regenerative braking. Regarding the circuit.

[0002]

2. Description of the Related Art Conventionally, in a DC motor drive circuit used in an automobile wiper device or the like, when a relay is used, when one FET is used, when an H bridge drive is performed by four FETs, a power transistor is used. It may be used.

In the case of a relay, regenerative braking can be applied when the motor is stopped by selectively switching between the power supply terminal and the ground terminal, but the operation noise of the relay is large, the parts are large, and the relay is used. There were problems such as the environment being restricted. In the case of one FET, an N-channel type FET will be connected between the motor and the ground terminal,
There is an inconvenience that regenerative braking cannot be applied. FET4
In the case of an H-bridge circuit consisting of a single piece, there is the inconvenience that it cannot withstand the accident of reverse connection of the power supply.
Further, in the case of the power transistor, there is a problem that not only the power loss including the pre-driver is large and the heat generation amount is large, but also the controller tends to be large.

[0004]

In view of the above problems of the prior art, the main object of the present invention is that regenerative braking is possible, the amount of heat generation is small, and it is possible to deal with reverse connection of a power source.
Another object is to provide a motor drive circuit that can be miniaturized.

[0005]

According to the present invention, such an object is achieved by a motor driving F connected in series to a motor.
ET, a regenerative braking thyristor connected in parallel to the motor, and a first delay time that is longer than the time from when the thyristor is turned on to when it is completely turned off from when the start signal is generated. 1 delay time generation circuit, and turns on the FET after the elapse of the first delay time,
FET that turns off the FET when a stop signal is generated
A control circuit, a second delay time generation circuit for generating a second delay time from the generation of the stop signal, and a state in which the thyristor is turned off from the generation of the start signal and after the second delay time has elapsed. A motor drive circuit having a thyristor control circuit for turning on the thyristor, or a motor drive FET connected in series to the motor, and a regenerative braking thyristor connected in parallel to the motor. An FET control circuit for selectively outputting an ON signal of the FET, a thyristor control circuit for outputting an ON signal to the thyristor, and a thyristor state detecting means for detecting an incomplete OFF state of the thyristor. If a signal for starting the motor is generated while the incomplete off state of the thyristor is detected, the FET control circuit is turned on. A motor drive circuit having a reset circuit for setting, or a motor drive FET serially connected to the motor, a regenerative braking thyristor connected in parallel to the motor, and an incomplete thyristor. Thyristor state detection means for detecting the off state, and when the start signal of the motor is generated while the incomplete off state of the thyristor is detected, the thyristor is completely turned off and then the FET
It is achieved by providing a motor drive circuit characterized by having a FET drive control auxiliary circuit capable of turning on the.

[0006]

With this configuration, the F connected in series with the motor
The ET can be turned on / off to selectively drive the motor, and when a stop signal is generated, the thyristor connected in parallel to the motor is turned on, so that a current flows through the motor and the thyristor, and Regenerative braking can be applied. Note that the thyristor is on when the motor is stopped and must be turned off by the start signal.
Further, the thyristor has a characteristic that its gate current becomes equal to or less than the trigger current, and after the thyristor current becomes equal to or less than the holding current, it is completely turned off after a lapse of turn-off time. Therefore, before the thyristor is completely turned off, the FET is turned on after the first delay time, which is longer than the time from when the activation signal is generated until the thyristor is completely turned off. It is possible to prevent a power supply short-circuit state due to the FET being turned on.

If noise corresponding to a stop signal occurs when the thyristor is incompletely off, the FET is forcibly turned off to prevent the power supply short circuit. In addition, after the stop signal is generated, if the start signal is generated again when the thyristor is in the incomplete off state, the power supply short circuit state can be prevented by enabling the thyristor to be restarted after the thyristor is completely turned off. .

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A preferred embodiment of the present invention will now be described in detail with reference to the accompanying drawings. FIG. 1 is a diagram showing a main part of a motor drive circuit to which the present invention is applied. To the battery terminal BT as a power source, one end of the motor 2 is connected in series via the P-channel type FET 1, and the other end of the motor 2 is grounded. An operation switch 3 for operating the motor 2 is connected between the power supply terminal V and the ground on the power supply terminal V side via a resistor R1.

The node between the resistor R1 and the operation switch 3 is
It is connected to the input terminal of the Schmitt trigger ST1 via the resistor R2. A diode D1 is connected in parallel between both ends of the resistor R2 and in the forward direction toward the Schmitt trigger ST1.
Are connected, and the node of the resistor R2 and the Schmitt trigger ST1 is grounded via the capacitor C1. The capacitor C1 and the resistor R2 form a first delay circuit 5. The inverting output terminal of the Schmitt trigger ST1 is connected to the base of the transistor Q1 whose emitter is grounded.

The collector of the transistor Q1 is connected to the gate of the FET1. The collector of the transistor Q1 is connected to the power supply terminal V via the resistor R3, and the node of the power supply terminal V and the resistor R3 and the node of the battery terminal BT and the FET1 are forward diodes toward the resistor R3 side. They are connected to each other via D2. In this way, the FE is transmitted through the transistor Q1.
An FET control circuit for controlling ON / OFF of T1 is configured.

The node between the resistor R1 and the operation switch 3 is connected to the input terminal of the Schmitt trigger ST2 via the resistor R4. A diode D3 is connected between both ends of the resistor R4 in parallel and in the opposite direction to the Schmitt trigger ST2, and the resistor R4 and the Schmitt trigger ST2 are connected.
The nodes of and are grounded via the capacitor C2.
The capacitor C2 and the resistor R4 form a second delay circuit 6. The inverting output terminal of the Schmitt trigger ST2 is connected to the base of the transistor Q2 whose emitter is grounded. The collector of transistor Q2
It is connected to the power supply terminal V via the resistor R5. In this way, a thyristor control circuit for controlling ON / OFF of the thyristor 4 via the transistor Q2 is constructed.

The node between the FET 1 and the motor 2 is grounded via the thyristor 4. The gate of the thyristor SCR is connected to the node of the resistor R5 and the transistor Q2, and is also grounded via the resistor R6. A parasitic diode D4 is formed between the source and drain of the FET1. Therefore, the motor 2 rotates in the reverse direction when the power source is reversely connected, but by making the thyristor 4 capable of withstanding the reverse connection, there is no bearing on the circuit.

The operation procedure of the motor drive circuit thus constructed will be described below with reference to the timing chart of FIG. The output signal from the operation switch 3 is A in FIG. 1, the input signal to the Schmitt trigger ST1 is B in FIG. 1, the output signal of the Schmitt trigger ST1 is the drive signal of the transistor Q1, C in FIG. Input signal to ST2 is D in FIG. 1, Schmitt trigger S
The drive signal of the thyristor 4 via the transistor Q2 which is the output signal of T2 is shown by the level of each signal line indicated by E in FIG.

When the operation switch 3 is turned on, the operation switch signal A changes from the high level (H) to the low level (L), and at the same time, the input signal D of the Schmitt trigger ST2 changes from the H level to the L level. The drive signal is turned off (H). The drive signal of the FET1 is gradually decreased by C1 and R2 after the operation switch 3 is turned on, and the Schmitt trigger ST1 input signal is at a turn-off level (Vth in FIG. 2).
It is turned on after a delay time T1 until it goes below 1). That is, at the same time when the operation switch 3 is turned on, the gate signal of the thyristor 4 is turned off, and after the delay time T1, the FET 1 is turned on and the motor 2 is driven.

Next, when the operation switch 3 is turned off, in this case, at the same time, the input signal B of the Schmitt trigger ST1.
Changes from the L level to the H level, the FET1 is turned off. At this time, the delay time T until the input signal of the Schmitt trigger ST2, which gradually increases by C2 and R4 after the operation switch 3 is turned off, exceeds the turn-on level (Vth2 in FIG. 2).
After 2 lapses, the thyristor 4 drive signal E is turned on (L). Therefore, the delay time T from the turning off of the operation switch 3
After 2 lapses, the thyristor 4 is turned on, and a current may flow between the motor 2 and the thyristor 4, so that the motor 2
Regenerative braking is applied to the.

It should be noted that the thyristor has a characteristic that, when the thyristor current changes from the on state to the off state, the thyristor completely turns off after the turn-off time elapses after the thyristor current becomes less than the holding current. Therefore, when the operation switch 3 is turned on again immediately after it is turned off, a current due to the motor reverse voltage may flow through the thyristor 4. Therefore, the time in which the thyristor current becomes equal to or less than the holding current and the thyristor turn-off time can sufficiently pass may be set as the delay time T1.

FIG. 3 shows a second embodiment of the present invention. In FIG. 3, the same parts as those in the above-mentioned embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

In the second embodiment, the operation switch 3 and the resistor R1 are connected in the opposite manner to the above embodiment, and both nodes are connected to one of a pair of input terminals of the NAND circuit ND1. It is connected. The output terminal of the NAND circuit ND1 is connected to the input terminal of the Schmitt trigger ST1 via the resistor R2. The Schmitt trigger S
T2, each transistor Q1 and Q2, FET1, thyristor 4, motor 2, etc. are constructed in the same manner as in the above embodiment.

The node between the FET1 and the motor 2 is connected to the input positive terminal of the first comparator OP1 of the short-circuit prevention circuit 7 shown by the imaginary line in the figure through the resistor R7. The node between the positive input terminal of the first comparator OP1 and the resistor R7 is the Zener diode ZD.
Although it is grounded via the resistor R7 and the Zener diode ZD,
This is to protect the comparator OP1.

The inverting input negative terminal of the first comparator OP1 is grounded via the resistor R8, and between the output terminal of the first comparator OP1 and the inverting input negative terminal,
The capacitor C3 and the resistor R9 are connected in parallel with each other. The output terminal of the first comparator OP1 is connected to the inverting input negative terminal of the second comparator OP2. A node between both resistors R10 and R11 connected in series between the power supply V and the ground is connected to the input positive terminal of the second comparator OP2.

The output terminal of the second comparator OP2 is connected to one of the pair of input terminals of the NOR circuit NR1. The output terminal of the NOR circuit NR1 is connected to one of the pair of input terminals of the AND circuit AD1 via the resistor R12, and the node between the resistor R12 and the AND circuit AD1 is grounded via the capacitor C4. The Schmitt trigger ST is connected to the other input terminal of the NOR circuit NR1 and the other input terminal of the AND circuit AD1.
1 output terminal is connected.

The output terminal of the AND circuit AD1 is connected to the reset terminal R of the flip-flop FF1, and the output terminal Q of the flip-flop FF1 is connected to the other input terminal of the NAND circuit ND1. The operation switch 3 signal is input to the clock terminal CLK of the flip-flop FF1, the D terminal of the flip-flop FF1 is connected to the power supply V, and S
The terminal is grounded.

The operation procedure of the motor drive circuit of the second embodiment thus constructed will be described below with reference to the timing chart of FIG. In addition, as shown in FIG.
Output signal from operation switch 3, Schmitt trigger ST
1, the input signal to FET1, the drive signal to the FET1, the input signal to the Schmitt trigger ST2, and the drive signal to the thyristor 4 are indicated by A to E as in the above-mentioned embodiment, and are based on the Q terminal output signal of the flip-flop FF1. The input signal of the NAND circuit ND1 is F, the output signal of the NAND circuit ND1 is G, the applied voltage state to the thyristor 4 is H, one input signal of the second comparator OP2 is I, and the second comparator OP2 has an input signal of the second comparator OP2. The output signal is indicated by J, the output signal of the NOR circuit NR1 is indicated by K, the input signal of the AND circuit AD1 based on the signal K is indicated by L, and the reset signal of the flip-flop FF1 is indicated by the level of each signal line indicated by M.

The states of the signals AE until the motor 2 is driven after the operation switch 3 is turned on are the same as in the above embodiment. When the drive signal of the FET1 becomes H level, the voltage applied to the thyristor 4 is generated by the energization of the motor 2, and the output of the first comparator OP1 accordingly becomes H level. The H level signal becomes the input signal I to the second comparator OP2, and the second comparator O2
A threshold value Vth3 resulting from voltage division of the resistors R10 and R11 is input to one input terminal of P2, and the output signal J of the second comparator OP2, which is the result of comparison with the threshold value Vth3, changes from H level to L level.

Noise such that the operation switch signal A momentarily changes to the L level and is immediately returned to the H level for some reason at the time t1 shown in the figure while the drive signal of the FET 1 is at the H level, that is, while the motor 2 is being driven. The following is a description of the case of occurrence. When the switch signal A changes from H level to L level, at the same time, the input signal D of the Schmitt trigger ST2
Goes to the L level for a moment, and the thyristor 4 drive signal also turns on for a moment and then turns off.

The input signal B of the Schmitt trigger ST1 is changed to the capacitor C1 by the momentary interruption of the switch signal A.
Is incompletely charged to exceed the threshold value Vth1, and the switch signal A returns to start discharging. When the signal B falls below the threshold value Vth1 again, the FET1 is turned off once.
The drive signal is turned on again (t2 in FIG. 4).

When the drive signal of the FET1 is turned on again, the applied voltage H of the thyristor 4 is generated to some extent by the back electromotive force of the motor 2, and therefore the second comparator OP2 which is the output signal of the first comparator OP1. Input signal I is at a level higher than the threshold value Vth3. Therefore,
The thyristor 4 is in an incomplete off state that can be turned on when an anode voltage is applied, and the incomplete off state is detected by the second comparator OP2. When the thyristor 4 is in the incomplete off state, The output signal J of the second comparator OP2 is in the L level state, and the L level signal is input to one input terminal of the NOR circuit NR1.

When the noise occurs, the drive signal C of the FET1 becomes L level, so the L level signal is input to the other input terminal of the NOR circuit NR1 and the NOR circuit NR1.
Output signal K becomes H level. Along with it C4
When the input signal L of the AND circuit AD1 which changes according to the time constant of R12 falls below the threshold value Vth1, the AND circuit A
The reset signal M of the flip-flop FF1, which is the output signal of D1, changes from L level to H level. Since the flip-flop FF1 is reset by the generation of the reset signal M, the input signal F of the NAND circuit ND1 switches from the H level to the L level, and therefore the NAND circuit ND1.
The output signal G of the above becomes H level, and the drive signal C of the FET1 which is turned on again can be forcibly turned off. This is because the delay circuit of C4 and R12 is necessary in order to hold that the output signal K of the NOR circuit NR1 has become L level as the input signal L of the AND circuit AD1.

If the process of forcibly turning off the drive signal C of the FET1 is not performed, the drive signal of the FET1 is turned on when the thyristor 4 is in the incomplete off state, so that both are turned on. Then, there arises a problem that the power is short-circuited. However, according to the present invention, as described above, while the noise is generated and the incomplete off state of the thyristor 4 is detected, the FET
When the ON signal of 1 is generated, the drive signal C can be forcibly set to the OFF state, and the above problem can be prevented from occurring.

It should be noted that the time Td from the time t2 when the drive signal C of the FET1 is generated again to the forced off state is Td.
However, this is because the element operating time (for example, several microseconds) from the time when the drive signal C of the FET 1 is generated again to the time when the short-circuit prevention circuit 7 works to forcibly turn it off. Further, the incomplete off-state detection time of the thyristor 4 (Ton in FIG. 4) is completely reduced from the holding current or less to the anode current of the thyristor 4 (Ta in FIG. 4) or less. The commutation turn-off time (Tr in FIG. 4) before turning off is set by C3 / R9.

FIG. 5 shows a third embodiment of the present invention. In FIG. 5, the same parts as those in the first embodiment are designated by the same reference numerals, and detailed description thereof will be omitted.

In the third embodiment, the operation switch 3 and the resistor R1 are connected in the same manner as in the second embodiment, and the nodes of both are one of the pair of input terminals of the AND circuit AD2. And the output signal of the AND circuit AD2 is input to the base of the transistor Q1 via the resistor R2.
The node between 1 and 1 is grounded via the capacitor C1. Further, the switch signal of the operation switch 3 is the resistance R
4 and the node between the resistor R4 and the transistor Q2 is grounded via the capacitor C2. In addition,
Each transistor Q1, Q2, FET1, thyristor 4,
The motor 2 and the like are configured in the same manner as in the above embodiment.

Further, the node between the FET1 and the motor 2 is connected to one input positive terminal of the first comparator OP1 via the resistor R7 as in the second embodiment. The configuration of each element from the first comparator OP1 to the output signal of the second comparator OP2 is the same as that of the second embodiment.

In the third embodiment, the output terminal of the second comparator OP2 is connected to one of the pair of input terminals of the NOR circuit NR1 and the reset terminal R of the flip-flop FF1. There is. NOR circuit N
A node of the operation switch 3 and the resistor R1 is connected to the other input terminal of R1. The inverting output terminal of the flip-flop FF1 is connected to the other input terminal of the AND circuit AD2.

The operation procedure of the motor drive circuit of the third embodiment thus constituted will be described below with reference to the timing chart of FIG. In addition, as shown in FIG.
An output signal from the operation switch 3, a drive signal for the FET 1,
Each of the drive signal of the thyristor 4, the applied voltage state to the thyristor 4, one input signal of the second comparator OP2, the output signal of the second comparator OP2, and the output signal of the NOR circuit NR1 is the same as in the above embodiment.・ C ・ E ・ H ～ K
, The inverted output signal of the flip-flop FF1 is shown in FIG.
It is indicated by the level of each signal line indicated by N.

When the operation switch 3 is turned on, the operation switch signal A becomes H level and the AND circuit AD
Since the inverted output signal N of the flip-flop FF1 which is the other input signal to 2 is in the H level state, the output signal of the AND circuit AD2 becomes the H level. After the lapse of the delay time T1 due to C1 and R2, the FET1 drive signal C becomes H level, the FET1 is turned on, and the motor 2 is driven as in the above-described embodiment.

Then, at a certain time t3, when the operation switch 3 is turned off, the FE is reached after the delay time T1 has elapsed.
T1 is turned off and C2, which is longer than the delay time T1,
After the lapse of the delay time T2 due to R4, the thyristor 4 is turned on and the motor 2 is regeneratively braked. Time Ta until the anode current of the thyristor 4 falls below the holding current Ta
Is the time during which the regenerative braking is possible, and further before the lapse of the time, which is the addition of the time Tr from when the anode current becomes the holding current or less to when the thyristor 4 is completely turned off,
When the operation switch 3 is turned on, the thyristor 4 may be on and the FET 1 may be turned on. In that case, a power short-circuit state will occur.

In the case of the third embodiment, the incomplete off-state detection time Ton of the thyristor 4 similar to that of the second embodiment is set, and the signal A of the operation switch 3 is set to L before that time. When the level changes from the H level to the H level, the thyristor drive signal E is turned off. Further, when the operation switch 3 signal A is turned off, the output signal K of the NOR circuit NR1 changes from the L level to the H level.
When the operation switch 3 signal A is switched to the H level again, it becomes the L level. Then, similarly to the second embodiment, the input signal I of the second comparator OP2 falls below the threshold value Vth3 after the lapse of time Ta due to the decrease of the voltage H applied to the thyristor 4, and at that timing, the output signal J of the second comparator OP2 is reached. Switches from the L level to the H level, and the flip-flop FF1 is reset.

Since the inverted output N is switched to the H level state at the reset timing of the flip-flop FF1, the AND circuit AD2 starts to output the H level signal. Then, after a lapse of time T1 from that time, that is, after a lapse of time Ton after the thyristor drive signal E is turned off, the FET1 drive signal C is turned on and the motor 2
Is restarted. In this way, after the time Ton has passed,
That is, the drive of the motor 2 is restarted after the thyristor 4 is completely turned off and the power supply short-circuit state is prevented from occurring.

The delay time due to C1 and R2 is set longer than the time Tr from when the anode current of the thyristor 4 becomes equal to or less than the holding current to when the thyristor 4 is completely turned off. It is set shorter than the time.

[0041]

As described above, according to the present invention, one FE is used.
By selectively driving the motor with T, installing a thyristor in parallel with the motor, and controlling the FET and thyristor by generating a delay time so that both are not turned on simultaneously, regenerative braking is achieved with a simple circuit configuration. A possible motor drive circuit can be achieved. If noise corresponding to the start signal for driving the motor occurs before the thyristor is completely turned off, the FET is forcibly turned off to prevent the power supply short-circuit state. obtain. In addition, by setting the time for the thyristor to be completely turned off and restarting the motor after that time has elapsed, the power supply short-circuit condition when a start signal is generated before the thyristor is completely turned off can be prevented. You can

[Brief description of drawings]

FIG. 1 is a diagram showing a main part of a motor drive circuit according to the present invention.

FIG. 2 is a timing chart showing an operating procedure based on the circuit of FIG.

FIG. 3 is a diagram showing a main part of a motor drive circuit according to a second embodiment of the present invention.

FIG. 4 is a timing chart showing an operating procedure based on the circuit of FIG.

FIG. 5 is a diagram showing a main part of a motor drive circuit according to a third embodiment of the present invention.

FIG. 6 is a timing chart showing an operating procedure based on the circuit of FIG.

[Explanation of symbols]

 1 FET 2 Motor 3 Operation Switch 4 Thyristor 5 First Delay Circuit 6 Second Delay Circuit 7 Short Circuit Prevention Circuit

Claims (3)

[Claims] 1. A motor drive FET connected in series to a motor, a regenerative braking thyristor connected in parallel to the motor, and a time period from when the thyristor is turned on to when it is completely turned off. A first delay time generation circuit that generates a first delay time from when a start signal is generated, the FET is turned on after the first delay time has elapsed, and the FET is turned off when a stop signal is generated. F
An ET control circuit, a second delay time generation circuit that generates a second delay time from the time the stop signal is generated, the thyristor is turned off from the time the start signal is generated, and the second delay time elapses. And a thyristor control circuit for turning on the thyristor later. 2. A motor driving FET connected in series to the motor, a regenerative braking thyristor connected in parallel to the motor, and an FET control circuit for selectively outputting an ON signal of the FET. A thyristor control circuit for outputting an ON signal to the thyristor, thyristor state detection means for detecting an incomplete off state of the thyristor, and the motor while the incomplete off state of the thyristor is detected. When a signal to start is generated, the above F
A motor drive circuit having a reset circuit for resetting the ET control circuit. 3. A motor driving FET connected in series to a motor, a regenerative braking thyristor connected in parallel to the motor, and thyristor state detection means for detecting an incomplete off state of the thyristor. And a FET drive control auxiliary circuit capable of turning on the FET after the thyristor is completely turned off when a start signal of the motor is generated while the incomplete off state of the thyristor is detected. A motor drive circuit having.