JPS645261B2 - - Google Patents

Info

Publication number
JPS645261B2
JPS645261B2 JP54067955A JP6795579A JPS645261B2 JP S645261 B2 JPS645261 B2 JP S645261B2 JP 54067955 A JP54067955 A JP 54067955A JP 6795579 A JP6795579 A JP 6795579A JP S645261 B2 JPS645261 B2 JP S645261B2
Authority
JP
Japan
Prior art keywords
power supply
comparator
supply voltage
voltage
power
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
JP54067955A
Other languages
Japanese (ja)
Other versions
JPS55159161A (en
Inventor
Ryosaku Taniguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP6795579A priority Critical patent/JPS55159161A/en
Publication of JPS55159161A publication Critical patent/JPS55159161A/en
Publication of JPS645261B2 publication Critical patent/JPS645261B2/ja
Granted legal-status Critical Current

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  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Testing Electric Properties And Detecting Electric Faults (AREA)

Description

【発明の詳細な説明】 この発明はデイジタルシステムの電源断検出回
路に関するものである。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a power-off detection circuit for a digital system.

従来この種の回路として第1図に示すものがあ
つた。図において1,2は抵抗、3はコンデンサ
ー、4はインバーターで、4aはその入力端子、
4bは同出力端子、4cは同電源入力端子、5は
電源装置である。
A conventional circuit of this type is shown in FIG. In the figure, 1 and 2 are resistors, 3 is a capacitor, 4 is an inverter, and 4a is its input terminal.
4b is the same output terminal, 4c is the same power input terminal, and 5 is a power supply device.

次に動作について説明する。電源電圧の立ち上
がり時インバーター4の入力は第2図にAで示す
ように、抵抗1、コンデンサー3のRC回路によ
る時定数で充電されるので電源電圧Vccの立ち上
がりよりも更に遅れて立ち上がる。抵抗1,2及
びコンデンサー3はVccがインバーター4の動作
開始電圧Vsに達してからインバーター入力電圧
がスレシヨールド電圧VTHに達するように時定数
を考慮している。従つて電源電圧VccがVsに達
してからt1入力電圧がVTHに達するt2までの間イ
ンバーター4の出力は第2図にBで示すように警
報出力される。
Next, the operation will be explained. When the power supply voltage rises, the input of the inverter 4 is charged with the time constant of the RC circuit of the resistor 1 and the capacitor 3, as shown by A in FIG. 2, so it rises even later than the rise of the power supply voltage Vcc. The time constants of the resistors 1 and 2 and the capacitor 3 are taken into consideration so that the inverter input voltage reaches the threshold voltage VTH after Vcc reaches the operation start voltage Vs of the inverter 4. Therefore, the output of the inverter 4 is outputted as an alarm as shown by B in FIG. 2 from the time when the power supply voltage Vcc reaches Vs until t2 when the input voltage reaches VTH .

従来の電源断検知回路は以上のように構成され
ているので電源電圧降下時には警報出力されなか
つた。また長時間の電源断に関してはコンデンサ
ー3の放電が充分であるため電源オンリセツトパ
ルスを出力出来るが瞬断に対してはコンデンサー
の放電が不充分であるためインバーター4の入力
電圧がスレツシヨールド電圧VTH以下に降下せず
警報出力出来なかつた。このため電源装置の交流
入力電圧の瞬断(AC100V50Hzで0.5サイクル〜
数サイクル)時デイジタル機器の誤動作、誤出力
が生じた。第3図は交流入力電圧瞬断時の電源電
圧への影響を示したものである。また電源電圧
Vccの垂下特性が数ms程度と長い場合、デイジ
タル機器には様々の集積回路が使用されているの
で、ある集積回路は動作しある集積回路は動作し
ないという状態が生じ誤動作が生じることがあつ
た。
Since the conventional power failure detection circuit is configured as described above, no alarm is output when the power supply voltage drops. In addition, when the power is cut off for a long time, the capacitor 3 is sufficiently discharged, so a power-on reset pulse can be output. However, when the power is cut off for a long time, the capacitor is not sufficiently discharged, so the input voltage of the inverter 4 becomes the threshold voltage V TH It was not possible to output a warning because the aircraft did not descend below this level. Therefore, momentary interruption of the AC input voltage of the power supply (0.5 cycles at 100 VAC, 50 Hz)
(several cycles), digital equipment malfunctions and erroneous output occurs. FIG. 3 shows the effect on the power supply voltage when there is a momentary interruption of the AC input voltage. Also power supply voltage
If the Vcc droop characteristic is long, on the order of several milliseconds, various integrated circuits are used in digital equipment, so some integrated circuits may operate while others do not, resulting in malfunctions. .

この発明は上記のような従来のものの欠点を除
去するためになされたもので瞬断に対する警報出
力を提供するものである。
The present invention has been made to eliminate the above-mentioned drawbacks of the conventional devices, and provides an alarm output for instantaneous power outages.

以下第4図に示すこの発明の一実施例について
説明する。第4図において第1図と同一符号は同
一或いは相当部分を示しており、6抵抗、7はコ
ンデンサー、8はダイオード、9は比較器であ
る。電源電圧を抵抗1a,2aで分割し比較器の
正相入力端子9aに接続する。逆相入力端子9b
には抵抗1b,2bで電源を分割し接続する。再
に抵抗2bにはコンデンサー3が並列接続されて
いる。比較器9の出力はインバータ4の入力端子
4aに接続され、また比較器9は電源5にダイオ
ード8を介して接続された比較器9の電源入力端
子9cには抵抗6及びコンデンサー7が並列接続
されている。
An embodiment of the present invention shown in FIG. 4 will be described below. In FIG. 4, the same reference numerals as in FIG. 1 indicate the same or equivalent parts, 6 a resistor, 7 a capacitor, 8 a diode, and 9 a comparator. The power supply voltage is divided by resistors 1a and 2a and connected to the positive phase input terminal 9a of the comparator. Reverse phase input terminal 9b
The power supply is divided and connected using resistors 1b and 2b. Again, a capacitor 3 is connected in parallel to the resistor 2b. The output of the comparator 9 is connected to the input terminal 4a of the inverter 4, and the comparator 9 is connected to the power supply 5 via the diode 8. A resistor 6 and a capacitor 7 are connected in parallel to the power input terminal 9c of the comparator 9. has been done.

次に動作を第5図に基き、説明する。 Next, the operation will be explained based on FIG.

ここで、第5図において、Vccは電源電圧波形
を、Vは比較器9の電源入力端子9cの電圧波
形、CA(実線で示された波形)は比較器9の正相
入力波形、CB(破線で示された波形)は比較器9
の逆相入力の波形、Cはインバータ4の入力波
形、Dはインバータ4の出力波形である。電源電
圧Vccは正常時は比較器9の正相入力端子9a側
は逆相入力端子9b側より高い値に設定されてお
り比較器9の出力は論理“H”である。今電源電
圧Vccが瞬時降下すると正相入力端子9aの電圧
は電源電圧Vccに比例して降下するが逆相入力端
子9bの電圧はRC回路を形成しているので降下
が遅く正相入力端子9a側は逆相入力端子9b側
より低くなり比較器9の出力は論理“L”とな
る。比較器の電源はダイオード8を通して供給さ
れ抵抗6、コンデンサー7が並列接続されている
ので電源電圧Vcc変動時コンデンサー7より電源
が供給され比較器はVcc変動の影響を余り受けな
い。このように比較器9の正相入力が逆相入力に
より低くなるとインバーター4を通して警報出力
される。
Here, in FIG. 5, Vcc is the power supply voltage waveform, V is the voltage waveform of the power input terminal 9c of the comparator 9, CA (the waveform indicated by a solid line) is the positive phase input waveform of the comparator 9, and CB ( The waveform shown by the broken line) is the comparator 9
C is the input waveform of the inverter 4, and D is the output waveform of the inverter 4. When the power supply voltage Vcc is normal, the positive phase input terminal 9a side of the comparator 9 is set to a higher value than the negative phase input terminal 9b side, and the output of the comparator 9 is logic "H". If the power supply voltage Vcc drops instantaneously, the voltage at the positive phase input terminal 9a will drop in proportion to the power supply voltage Vcc, but the voltage at the negative phase input terminal 9b will fall slowly because it forms an RC circuit. side is lower than the opposite phase input terminal 9b side, and the output of the comparator 9 becomes logic "L". Power to the comparator is supplied through a diode 8, and a resistor 6 and a capacitor 7 are connected in parallel, so that when the power supply voltage Vcc fluctuates, power is supplied from the capacitor 7, and the comparator is not affected much by Vcc fluctuations. In this way, when the positive phase input of the comparator 9 becomes lower due to the negative phase input, an alarm is outputted through the inverter 4.

電源電圧Vccがインバーター4の動作保証電圧
Vs以下に降下しない場合は比較器9の電源も比
較器9の動作保証電圧Vc以下に降下せず正常な
警報出力が得られる。一方電源電圧Vccがインバ
ーター4の動作保証電圧Vc以下に降下するよう
な瞬停に対しては電源電圧垂下特性がある傾斜を
もつているので第5図のCA,CBに示されるよう
に比較器9の正相入力と逆相入力とが反転した時
点t3からVccが動作保証電圧Vcに達する時点t4
での間警報出力が得られる。また比較器9は動作
保証電圧Vc以下になると論理“L”となるもの
が一般的であるので電源電圧Vcc立ち上がり時に
は電源電圧Vccがインバーターの動作保証電圧
Vsに達してから比較器9の動作保証電圧Vcに達
するまでの間警報出力が得られる。(t5よりt6
で) なお、上記実施例では比較器9の出力そのもの
を警報出力としていないが比較器9の出力を警報
出力とし計算機への異常割込入力として使用して
も良い。
Power supply voltage Vcc is the guaranteed operation voltage of inverter 4
If the voltage does not drop below Vs, the power supply of the comparator 9 will not fall below the guaranteed operation voltage Vc of the comparator 9, and a normal alarm output will be obtained. On the other hand, for instantaneous power outages such as when the power supply voltage Vcc drops below the guaranteed operating voltage Vc of the inverter 4, the power supply voltage drooping characteristic has a certain slope. An alarm output is obtained from time t 3 when the positive phase input and negative phase input of 9 are reversed to time t 4 when Vcc reaches the guaranteed operation voltage Vc. In addition, the comparator 9 generally becomes logic "L" when the voltage drops below the guaranteed operation voltage Vc, so when the power supply voltage Vcc rises, the power supply voltage Vcc becomes the guaranteed operation voltage of the inverter.
An alarm output is obtained from the time when Vs is reached until the operation guaranteed voltage Vc of the comparator 9 is reached. (From t 5 to t 6 ) In the above embodiment, the output of the comparator 9 itself is not used as an alarm output, but the output of the comparator 9 may be used as an alarm output and used as an abnormality interrupt input to the computer.

以上のようにこの発明によれば瞬断に対する警
報出力が得られるのでデイジタルシステムの誤動
作を防止することが出来る。
As described above, according to the present invention, it is possible to obtain a warning output in response to a momentary power outage, thereby making it possible to prevent malfunctions of the digital system.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は従来の電源オンクリヤー回路の構成
図、第2図は第1図の説明図であり、Vccは電源
電圧波形図、Aはインバーター4の入力電圧波形
図、Bは出力電圧波形図、第3図は従来のものを
説明するための説明図、第4図はこの発明の実施
例を示す構成図、第5図は第4図の説明図であ
り、Vccは電源電圧波形図、Vは比較器の電源電
圧波形図、CAは正相入力電圧波形図、CBは逆相
入力電圧波形図、Cはインバータゲートの入力波
形図、Dは出力波形図である。 図において、1,1a,1b,2,2a,2
b,6は抵抗、3,7はコンデンサー、8はダイ
オード、9は比較器、4はインバーター、5は電
源装置である。図中、同一符号は同一或いは相当
部分を示す。
Figure 1 is a configuration diagram of a conventional power on-clear circuit, and Figure 2 is an explanatory diagram of Figure 1, where Vcc is a power supply voltage waveform diagram, A is an input voltage waveform diagram of the inverter 4, and B is an output voltage waveform diagram. , FIG. 3 is an explanatory diagram for explaining the conventional one, FIG. 4 is a configuration diagram showing an embodiment of the present invention, and FIG. 5 is an explanatory diagram of FIG. 4, where Vcc is a power supply voltage waveform diagram, V is a power supply voltage waveform diagram of the comparator, CA is a positive phase input voltage waveform diagram, CB is a negative phase input voltage waveform diagram, C is an input waveform diagram of the inverter gate, and D is an output waveform diagram. In the figure, 1, 1a, 1b, 2, 2a, 2
b and 6 are resistors, 3 and 7 are capacitors, 8 is a diode, 9 is a comparator, 4 is an inverter, and 5 is a power supply device. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

【特許請求の範囲】[Claims] 1 比較器を具備しその入力の一方に電源電圧を
抵抗分割して加え、他方に電源電圧を先記と異な
る割合で抵抗分割し加え抵抗の一方にコンデンサ
ーを並列接続し、先記比較器の電源をダイオード
を通し供給し、再に上記比較器の電源端子に抵抗
及びコンデンサーを接続し電源電圧降下時コンデ
ンサーから電源を供給することにより比較器を動
作させ警報出力することを特徴とする電源瞬断検
知回路。
1 Equipped with a comparator, the power supply voltage is divided by a resistor and applied to one of its inputs, and the power supply voltage is divided by a resistor at a ratio different from the above to the other input, and a capacitor is connected in parallel to one of the resistors. A power supply instantaneous power source characterized in that power is supplied through a diode, a resistor and a capacitor are connected to the power supply terminal of the comparator, and when the power supply voltage drops, power is supplied from the capacitor to operate the comparator and output an alarm. disconnection detection circuit.
JP6795579A 1979-05-31 1979-05-31 Detecting circuit of hit of electric power source Granted JPS55159161A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP6795579A JPS55159161A (en) 1979-05-31 1979-05-31 Detecting circuit of hit of electric power source

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP6795579A JPS55159161A (en) 1979-05-31 1979-05-31 Detecting circuit of hit of electric power source

Publications (2)

Publication Number Publication Date
JPS55159161A JPS55159161A (en) 1980-12-11
JPS645261B2 true JPS645261B2 (en) 1989-01-30

Family

ID=13359880

Family Applications (1)

Application Number Title Priority Date Filing Date
JP6795579A Granted JPS55159161A (en) 1979-05-31 1979-05-31 Detecting circuit of hit of electric power source

Country Status (1)

Country Link
JP (1) JPS55159161A (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3963554B2 (en) * 1997-06-17 2007-08-22 セイコーエプソン株式会社 Electronic device, watch, and power consumption control method for electronic device

Also Published As

Publication number Publication date
JPS55159161A (en) 1980-12-11

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