JPH0143650Y2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a failure mode discrimination circuit, and more particularly to a mode discrimination circuit that discriminates between a short circuit of a power transistor and a disconnection of a load in a load driving device.

In recent years, with the rapid development of electronic technology, there is a tendency for various devices to be controlled by electronic circuits such as microcomputers. In this case, since the output signal of the electronic circuit is extremely small, this signal cannot be used as it is to drive a load such as a solenoid. Therefore, for example, in a control system using a microcomputer, a power transistor controlled by the microcomputer is provided, and the output of this power transistor is used to drive a load.

In this case, if the power transistor is short-circuited or the load is disconnected for some reason, problems such as incorrect control or damage to other electrical components may occur. Therefore, control systems using such electronic circuits are equipped with a failure mode discrimination circuit that constantly monitors the power transistor and load in series, and switches to fail-safe control as soon as a failure occurs. .

FIG. 1 is a circuit diagram showing an example of a conventionally commonly used failure mode discrimination circuit, particularly when applied to a solenoid drive circuit. In the figure, Q ₁ is a transistor connected between a power supply +V and ground via resistors R ₁ and R ₂ , and has a base input of a control signal A supplied from an electronic control circuit (not shown). _Q2 is a power transistor whose base input is the signal at the voltage dividing point of resistors _R1 and _R2 , and Z is a load, which is connected between the power supply +V and ground via the power transistor _Q2 . _R3
is a pull-up resistor connected in parallel to power transistor _Q1 .

In the circuit configured as described above, since the control signal A is normally "L", the transistor _Q1 is turned off, and the power supply +V is connected to the power transistor Q through the resistor _R1 . ₃ , the power transistor Q ₂ is also turned off and the load Z remains inactive. In this case, since the load Z is connected to the power supply +V via the pull-up resistor _R3 , which has a sufficiently large value relative to its internal resistance r, the power transistor _Q2 is off and the load Z is disconnected. If not,
Discrimination signal B taken out from point b becomes "L", indicating normality. Next, when a short-circuit accident occurs in the power transistor _Q2 for some reason, the discrimination signal B output from point b becomes "H", indicating that a failure has occurred. Also, load Z
If the power transistor _Q2 is off, the discrimination signal B output from point b becomes "H" due to the power supplied via the pull-up resistor _R3 , indicating that a failure has occurred. shows. Therefore,
By determining the "H" state of the discrimination signal B during the "L" period of the control signal A, the electronic circuit can know the occurrence of a failure in the power transistor _Q2 or the load Z, and accordingly control is switched to fail-safe control.

However, in the circuit having the above configuration, the discrimination signal B becomes "H" when the power transistor _Q2 is short-circuited, and also becomes "H" when the load Z is disconnected. Therefore, in the above configuration, the electronic circuit inputting the discrimination signal B can only confirm that either a short circuit in the power transistor _Q2 or a disconnection in the solenoid as a load has occurred. It is completely impossible to determine which type of failure is occurring. but,
In the case of a short-circuit accident in power transistor Q ₂ and a short-circuit accident in load Z, the fail-safe control is often completely opposite, and in such cases, there is a problem that reliable fail-safe control cannot be performed. .

Therefore, the failure mode discrimination circuit according to the present invention is as follows:
It is an object of the present invention to provide a failure mode discrimination circuit that can reliably and easily discriminate between a short circuit of a power transistor provided for driving a load and a disconnection of the load when a failure occurs.

In order to achieve such an object, the present invention provides that when the discrimination signal taken out from the connection point b between the power transistor Q ₂ , pull-up resistor R ₃ and the load Z becomes "H", this discrimination signal is When connected to the other pole of the power supply via a resistor, a voltage drop is detected to determine if the load is disconnected, and if the "H" period of the determination signal exceeds the set time, it is a malfunction of the power transistor system or This is determined as a short circuit. Hereinafter, the failure mode discrimination circuit according to the present invention will be explained in detail with reference to the drawings.

FIG. 2 is a circuit diagram showing an embodiment of the failure mode discrimination circuit according to the present invention, and the same parts as in FIG. 1 are indicated using the same symbols. In the same figure
Q ₃ is a transistor connected in parallel to the load Z via a resistor R ₄ having a relatively small resistance value, and is connected to the “H” level of the discrimination signal B from an electronic circuit (not shown).
It is turned on by the discrimination control signal C sent at the same time. TS is a timer circuit that starts operating when the discrimination signal B is "H" and whose time counting operation is reset when the discrimination signal B is inverted from "H" to "L". And this timer circuit TS
is turned on by an inverter IN that inverts the discrimination signal B, a series resistor _R5 and a capacitor C that are connected in series between the power supply +V and the ground to form an integrating circuit, and the output "H" of the inverter IN. By using the transistor _Q4 , which forcibly discharges the capacitor C of the integrating circuit by It is configured. Note that the control signal A in this case is not continuous for more than time _T1 , and the timer circuit TS is
The time is set so that an alarm signal D is generated when an input signal exceeding _T1 is supplied.

In the circuit configured in this way, when the load Z is disconnected, the power supply supplied via the pull-up resistor _R3 causes the point b to rise to the power supply +V, and accordingly, the discrimination signal B is When the discrimination signal B becomes "H", an "H" level discrimination control signal C is generated from an electronic circuit (not shown), and the transistor _Q3 is turned on. In this case, the resistance
Since _R4 is set to a sufficiently small value compared to pull-up resistor _R3 , the divided voltage of resistors _R3 and _R4 becomes "L" level discrimination signal B. Therefore, if the discrimination signal B is inverted from "H" to "L" when the discrimination control signal C is generated, this indicates that the load Z is disconnected.

Next, if the transistor Q ₁ or Q ₂ is short-circuited, the discrimination signal B will continue to be in the "H" state. On the other hand, even if the discrimination control signal C is generated and the transistor Q ₃ is turned on, the transistor Q ₂
Since the impedance is extremely low, the discrimination signal B continues to be in the "H" state. In this manner, when the discrimination signal B continues to hold the "H" state even after the discrimination control signal C is generated, the output of the timer circuit TS is used for discrimination. That is, in this case, it is specified that the control signal A is generated as a continuous signal only within time _T1 . Therefore, under normal conditions when the discrimination signal B is "L", the output of the inverter IN is "H".
In order to turn on transistor _Q4 ,
Both ends of capacitor C are short-circuited and the integral operation is forcibly stopped. Then, when the discrimination signal B becomes "H", the transistor _Q4 is turned off and the integration operation is started, corresponding to the time constant determined by the values of the resistor _R5 and the capacitor C. When the integral output increases and reaches the reference value V _R after time _T1 has elapsed, the output of the comparator CN becomes "H" and an alarm signal D is generated indicating that the power transistor system is abnormal. be done.

Next, when the power transistor _Q1 is turned on by the normal control signal A, the load Z is accordingly driven, and the discrimination signal B becomes "H", and the timer circuit TS operates as described above. The timing operation will be started in the same way as above, but the control signal A will be “H” only within the set time _T1.
Therefore, the determination signal B is inverted from "H" to "L" before the timer circuit TS completes counting the set time _T1 . As a result, the transistor _Q4 of the timer circuit TS is turned on, the capacitor C forming the integrating circuit is forcibly discharged, and the generation of the alarm signal D is prevented.

Therefore, by determining the change in the discrimination signal B when the discrimination control signal C is generated and the alarm signal D generated from the timer circuit TS, the content of the abnormality can be clearly detected, and the content of the abnormality can be clearly detected. Accordingly, fail-safe control corresponding to the content of the abnormality can be performed quickly. FIG. 3 shows a flowchart of such an operation.

As described above, the failure mode discrimination circuit according to the present invention has an excellent effect of being able to easily and reliably discriminate between a disconnection of a load and a short-circuit accident in a power transistor system that drives and controls the load.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing an example of a conventional failure mode discrimination circuit, Fig. 2 is a circuit diagram showing an embodiment of the failure mode discrimination circuit according to the present invention, and Fig. 3 shows the operation of the circuit shown in Fig. 2. FIG. Q ₁ , Q ₃ , Q ₄ ... transistor, Q ₂ ... power transistor, Z ... load, R ₁ to _{R 5} ... resistance,
IN...Inverter, C...Capacitor, CN...
Comparator, TS...timer circuit.

Claims (1)

[Scope of utility model registration request] A series body of a power transistor and a load, a pull-up resistor connected in parallel to the power transistor, a series body of a resistor and a transistor connected in parallel to the load, and a connection point of the power transistor and the load. and a timer circuit that measures the "H" period of the generated discrimination signal, and determines whether or not the load is disconnected based on the discrimination signal when the transistor is turned on, and the timer circuit determines whether or not the power is at a predetermined power level. A failure mode determination circuit that determines a short circuit in a power transistor system based on an alarm signal that is output when time is counted beyond the maximum on period of a transistor.