JPH0441368Y2 - - Google Patents
Info
- Publication number
- JPH0441368Y2 JPH0441368Y2 JP1982152826U JP15282682U JPH0441368Y2 JP H0441368 Y2 JPH0441368 Y2 JP H0441368Y2 JP 1982152826 U JP1982152826 U JP 1982152826U JP 15282682 U JP15282682 U JP 15282682U JP H0441368 Y2 JPH0441368 Y2 JP H0441368Y2
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- supply voltage
- switching element
- circuit
- voltage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000002093 peripheral effect Effects 0.000 claims description 2
- 238000001514 detection method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 4
- 230000007257 malfunction Effects 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
Description
【考案の詳細な説明】
(イ) 産業上の利用分野
本考案は電源回路、特にマイコンを用いた電子
機器の電源回路に関する。[Detailed description of the invention] (a) Industrial application field The present invention relates to a power supply circuit, and particularly to a power supply circuit for electronic equipment using a microcomputer.
(ロ) 従来の技術
フロツピーデイスク、プリンターあるいは各種
制御用モーターを付属する機器等のコンピユータ
端末機器においては、マイコン等の制御回路とメ
カニクスとが一体化されて構成されている。従つ
て電源回路はマイコン等の制御回路については＋
5Vを中心とした電源で、メカニクスについては
＋12V、＋15V、＋24Vあるいは±12V±24Vの電
源で構成する。(B) Prior Art Computer terminal devices such as floppy disks, printers, and devices equipped with various control motors are constructed by integrating control circuits such as microcomputers and mechanics. Therefore, the power supply circuit is + for control circuits such as microcontrollers.
The main power supply is 5V, and the mechanics are configured with +12V, +15V, +24V or ±12V±24V power supplies.
第１図に示す制御回路＋5V、メカニクス＋
12Vの電源回路について考えると、一次入力電圧
が定格の場合には特に問題は起らないが、一次入
力電圧のON／OFFの過渡時に相対的な出力電圧
の立上り、立下り特性によつて誤動作を生じる場
合があり得る。第２図を参照して説明すると、電
源スイツチのOFF時に＋5V、＋12Vは夫々保持時
間T1，T2後に立下る。＋5Vは一定の電源が流れ
続けるのに対し、＋12Vはメカニクスであるため
例えば制御モーターの静止状態であれば無負荷に
近く極めて長時間の保持時間であることが往々に
してあり得る。この場合＋5Vの方が先に立下り、
この期間制御回路は正常な動作指令をせずもし＋
12V側に電圧が残存していると誤動作の原因とな
る。 Control circuit +5V, mechanics + shown in Figure 1
Considering a 12V power supply circuit, no particular problem occurs when the primary input voltage is at the rated value, but malfunctions may occur due to the relative rise and fall characteristics of the output voltage during ON/OFF transitions of the primary input voltage. may occur. To explain with reference to FIG. 2, when the power switch is turned off, +5V and +12V fall after holding times T1 and T2, respectively. +5V is a constant power supply, whereas +12V is mechanical, so if the control motor is at rest, for example, there is almost no load and it can often be held for an extremely long time. In this case, +5V falls first,
During this period, the control circuit may not issue normal operation commands.
If voltage remains on the 12V side, it may cause malfunction.
(ハ) 目的
本考案は斯点に鑑みてなされ、誤動作の発生し
ない電源回路を提供することを目的とする。(c) Purpose The present invention has been made in view of this point, and its purpose is to provide a power supply circuit that does not cause malfunctions.
(ニ) 構成
本考案に依れば第３図に示す如く、制御用モー
タ等の周辺機器等のメカニクスを駆動する＋12V
の第１図の電源電圧と、マイコン等の制御電回路
を駆動する＋5Vの第２電源電圧とを具備し、電
源スイツチのOFF時に第２の電源電圧の立下り
を検出する第１のスイツチング素子Q1を設け、
第１電源電圧と接地（GND）間に第２のスイツ
チング素子Q2を設け、第１のスイツチング素子
Q1の出力でスイツチング素子Q2を導通させて第
１の電源電圧を急峻に立下る様に構成している。(d) Configuration According to the present invention, as shown in Figure 3, +12V is used to drive the mechanics of peripheral devices such as control motors.
A first switching element that is equipped with the power supply voltage shown in FIG. Set up Q 1 ,
A second switching element Q2 is provided between the first power supply voltage and ground (GND), and the first switching element
The switching element Q2 is made conductive by the output of Q1 , and the first power supply voltage is configured to fall sharply.
(ホ) 実施例
本考案による実施例を第３図および第４図を参
照して説明する。第１のスイツチング素子である
トランジスタQ1は＋5Vの電源電圧と接地間に直
列に接続されたツエナーダイオードZD、抵抗
R1，R2によつてそのベースが接続されている。(E) Embodiment An embodiment of the present invention will be described with reference to FIGS. 3 and 4. The first switching element, transistor Q1, consists of a Zener diode ZD and a resistor connected in series between the +5V power supply voltage and ground.
Its bases are connected by R1 and R2.
即ち、所定の電圧Vpで動作するようにトラン
ジスタQ1のベース電圧が抵抗R1，R2によつてバ
イアスされている。従つて、ツエナー電圧をVZ
とすると、Vpは
Vp＝Vz＋R1＋R2／R2×0.6
で与えられる。本実施例ではVpを4.5Vに設定し
た。第２のスイツチング素子であるトランジスタ
Q2は＋12Vと接地（GND）間に電流制限用の抵
抗R′を介して接続され、ベースコレクタ間にバ
イアス抵抗Ｒを接続され、更にトランジスタQ1
のコレクタをベースに接続されている。 That is, the base voltage of transistor Q1 is biased by resistors R1 and R2 so that it operates at a predetermined voltage Vp. Therefore, the Zener voltage is VZ
Then, Vp is given by V p =V z +R 1 +R 2 /R 2 ×0.6. In this example, V p was set to 4.5V. Transistor, which is the second switching element
Q 2 is connected between +12V and ground (GND) via a current-limiting resistor R', a bias resistor R is connected between the base and collector, and the transistor Q 1
The collector is connected to the base.
斯上の構成では一次入力電圧が定格時では、ト
ランジスタQ1は導通し、トランジスタQ2は遮断
している。次に電源スイツチがOFF時において
は＋5Vは立下り前述したVPを下回るとトランジ
スタQ1は遮断し、トランジスタQ2は導通して＋
12Vと接地間の間に接続された制限抵抗R′を介し
て短絡するので第４図の如く＋12Vは急峻に立下
げ、コンデンサーの放電による放電路を制御でき
るものである。 In the above configuration, when the primary input voltage is at the rated value, transistor Q1 is conductive and transistor Q2 is cut off. Next, when the power switch is OFF, +5V falls and when it falls below the above-mentioned V P , transistor Q 1 is cut off, and transistor Q 2 is conductive, and +
Since a short circuit is made through the limiting resistor R' connected between 12V and ground, +12V falls sharply as shown in Fig. 4, and the discharge path due to the discharge of the capacitor can be controlled.
(ヘ) 効果
本考案に依ればマイコン等の制御回路の＋5V
の電源の立下りを検出してメカニクスの＋12V＋
15V、＋25Vあるいは±12V、±15Vの電源を＋5V
より急峻に立下げるので、完全に誤動作を防止で
きるのである。また、本考案に依れば、出力端子
数に対応するトランジスタの数で簡単な回路構成
で本考案の目的を達成できる。(F) Effect According to the present invention, +5V of control circuits such as microcontrollers
+12V+ of the mechanics by detecting the fall of the power supply.
15V, +25V or ±12V, ±15V power supply to +5V
Since it falls more steeply, malfunctions can be completely prevented. Further, according to the present invention, the object of the present invention can be achieved with a simple circuit configuration using a number of transistors corresponding to the number of output terminals.
第１図は従来の電源回路を説明する回路図、第
２図は第１図の電源の立下り特性を説明する特性
図、第３図は本考案の実施例を説明する回路図、
第４図は本考案の電源の立下り特性を説明する特
性図である。
主な図番の説明、Q1は第１のスイツチング素
子、Q2は第２のスイツチング素子である。
FIG. 1 is a circuit diagram illustrating a conventional power supply circuit, FIG. 2 is a characteristic diagram illustrating the fall characteristics of the power supply shown in FIG. 1, and FIG. 3 is a circuit diagram illustrating an embodiment of the present invention.
FIG. 4 is a characteristic diagram illustrating the fall characteristics of the power supply according to the present invention. Explanation of the main figure numbers: Q 1 is the first switching element, Q 2 is the second switching element.
Claims (1)
電源電圧と、マイコン等の制御回路を駆動する第
２の電源電圧とを具備し電源スイツチの開成時に
前記第２の電源電圧の立下りを前記第２の電源電
圧と接地間に接続された第１のスイツチング素子
で検出し、前記第１のスイツチング素子の出力で
前記第１の電源電圧と接地間に接続された第２の
スイツチング素子を導通させて、前記第１の電源
電圧を急峻に立下げることを特徴とする電源回
路。 A first power supply voltage for driving peripheral equipment such as a control motor, and a second power supply voltage for driving a control circuit such as a microcomputer are provided, and the fall of the second power supply voltage is detected when the power switch is opened. Detection is performed by a first switching element connected between a second power supply voltage and ground, and the output of the first switching element conducts a second switching element connected between the first power supply voltage and ground. The power supply circuit is characterized in that the first power supply voltage is abruptly lowered.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15282682U JPS5958817U (en) | 1982-10-07 | 1982-10-07 | power circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15282682U JPS5958817U (en) | 1982-10-07 | 1982-10-07 | power circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5958817U JPS5958817U (en) | 1984-04-17 |
| JPH0441368Y2 true JPH0441368Y2 (en) | 1992-09-29 |
Family
ID=30338286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15282682U Granted JPS5958817U (en) | 1982-10-07 | 1982-10-07 | power circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5958817U (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5755428A (en) * | 1980-09-18 | 1982-04-02 | Canon Inc | Protection circuit |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS54107036U (en) * | 1978-01-13 | 1979-07-27 |
-
1982
- 1982-10-07 JP JP15282682U patent/JPS5958817U/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5755428A (en) * | 1980-09-18 | 1982-04-02 | Canon Inc | Protection circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5958817U (en) | 1984-04-17 |
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