JPH0219856Y2 - - Google Patents

Description

[Detailed description of the invention] This invention relates to a voltage stabilizing circuit with a reset signal generation function that has a function of generating a reset signal when the power is turned on and when the power is turned off. The present invention aims to provide a voltage stabilizing circuit with functions.

<Background of the Idea> For example, a device with a built-in microprocessor requires an initialization reset signal to initialize the microprocessor when the power is turned on. Therefore, when the power is turned on, the rise of the power supply voltage is detected,
The configuration is such that a reset signal is generated by detecting the rising edge. Also, when the power is turned off, the RAM
Operations to protect data stored in etc., e.g.
Operations such as connecting a backup battery to RAM are required. For this reason, the device is generally configured to detect the rise and fall of the power supply voltage, generate a reset signal when the power is turned on and off, and use this reset signal to perform initialization, data protection operations, etc.

<Description of Prior Art> FIG. 1 shows a conventional reset signal generating device.
In the figure, 1 is a commercial power source, 2 is a power switch, and 3 is a power transformer. Stepping down or stepping up the voltage of the commercial power supply 1 to a desired voltage by the power transformer 3,
The secondary output voltage is supplied to a rectifying and smoothing circuit 4, rectified and smoothed, and controlled to a constant voltage by a DC stabilizing circuit 5, and the output of the stabilizing circuit 5 is supplied to a load 6. configured to operate. The load 6 here refers to an electronic circuit including at least a logic circuit.

7 shows a reset signal generation circuit. The reset signal generating circuit 7 includes a capacitor 8 charged with the output voltage of the DC voltage stabilizing circuit 5, and a capacitor 8 charged with the output voltage of the DC voltage stabilizing circuit 5.
a resistor 9 that limits the current charging the capacitor 8, and a diode 10 that quickly discharges the charge in the capacitor 8.
and a level detection circuit 11 that detects that the charging voltage of the capacitor 8 has fallen below a predetermined value. The level detection circuit 11 is
For example, a Schmitt trigger circuit can be used.

<Explanation of operation in FIG. 1> When the power switch 2 is turned on, the secondary voltage of the transformer 3 rises at the same time as the switch 2 is turned on, as shown in FIG. 2A. As shown in FIG. 2B, the output voltage V _CC of the DC voltage stabilizing circuit 5 reaches the normal voltage with some delay from the time when the switch 2 is turned on. This time delay is caused mainly by the time constant of the rectifying and smoothing circuit 4.

On the other hand, the charging voltage of the capacitor 8 of the reset signal generating circuit 7 rises at a slower rate than the rise of the output voltage V _CC of the DC voltage stabilizing circuit 5, as shown in FIG. 2C. This delay results from charging the output voltage V _CC of the DC voltage stabilization circuit 5 through the resistor 9 .

The level detection circuit 11 uses the output voltage V _CC of the DC voltage stabilization circuit 5 as a power supply for operation, and when the charging voltage of the capacitor 8 is below the low level threshold V _TL , it is approximately equal to the output voltage V _CC of the DC voltage stabilization circuit 5. It outputs an equal voltage H logic, when it is above the high level threshold V _TH it outputs an almost OV L logic, and when it exceeds the low level threshold and is less than the high level threshold V _TH it outputs the output logic just before entering this range. Hold. Yotsute capacitor 8
In the process in which the voltage of the voltage level gradually increases as shown in FIG. 2C, the level detection circuit 11 generates the reset signal _RS1 shown in FIG. 2D.

On the other hand, when the power is cut off, the output voltage of the DC stabilizing circuit 5
V _CC gradually decreases, but since the charge charged in capacitor 8 is discharged through diode 10 , the voltage charged in capacitor 8 decreases to approximately equal to the output voltage V _CC of DC stabilizing circuit 5 . This allows the level detection circuit 11 to generate an H logic reset signal _RS2 (D in Figure 2) even when the power is turned off.
Next, the capacitor 8 is sufficiently discharged in preparation for the power being turned on again.

<Disadvantages of the Conventional Method> As described above, in the conventional method, the charge stored in the capacitor 8 is discharged by the diode 10, and the reset signal _RS2 is generated even when the power is cut off.

However, the reset signal _RS2 is generated only after the output voltage _VCC of the DC voltage stabilizing circuit 5 becomes below the low level threshold _VTL , and at this point the logic circuit of the load 6 is no longer operating normally. There is a risk that the reset signal RS 2 will be meaningless because the power supply voltage that allows the reset signal RS ₂ is not supplied.

In addition, after the power supply is temporarily cut off and the output voltage V _CC of the DC voltage stabilizing circuit 5 decreases, and the logic circuit of the load 6 is no longer able to continue normal operation, and the voltage of the capacitor 8 reaches the low level threshold. If the power is restored before the voltage drops below V _TL , the voltage of the capacitor 8 will start to rise again, so the output of the level detection circuit 11 will remain at L logic, and neither reset signals RS ₂ nor RS ₁ will be generated. The logic circuit of the load 6 starts operating without being initialized and therefore malfunctions.

<Purpose of the invention> The object of this invention is to provide a voltage stabilizing circuit having a reset signal generation function that can reliably generate a reset signal when the power is turned on and when the power is turned off.

<Summary of the invention> In this invention, a sub-rectifier circuit that generates a voltage higher than the main rectifier circuit for providing an operating voltage to the load 6 is provided, and a DC stabilizing circuit is configured by the output voltage of this sub-rectifier circuit. This causes the output voltage of the error amplifier to rise while the output voltage of the DC stabilizing circuit is lower than the specified value, and this voltage rise turns on the switch element, and this switch element turns on. This makes the charging voltage of the capacitor zero, thereby causing the level detection circuit 11 to immediately and reliably generate a reset signal.

<Example of the invention> Fig. 3 shows an example of the invention. 1st in the diagram
Portions corresponding to those in the figure are designated by the same reference numerals. In this invention, a sub-rectifying and smoothing circuit 12 is provided for the main rectifying and smoothing circuit 4 to output a voltage higher than the main rectifying and smoothing circuit 4, and the output voltage _VB of this sub-rectifying and smoothing circuit 12 is used to generate an error that constitutes the DC stabilizing circuit 5. The amplifier 13 is operated. Furthermore, the output voltage V _B of the sub-rectifying and smoothing circuit 12 is also applied to the reference voltage generation circuit 14 which provides a reference voltage to the error amplifier 13, so that the reference voltage V _R
to occur.

The output voltage V _A of the error amplifier 13 is as usual,
It is supplied to the base of the control transistor 15 through the resistor R _B and operates to control the voltage between the collector and emitter of the transistor 15 so that the voltage V _CC output to the output terminal OU becomes a constant value.

Here, in this invention, the output voltage V _A of the error amplifier 13 is derived, and this output voltage V _A is supplied to a voltage dividing circuit 17 including, for example, a constant voltage diode 16 . This voltage regulator diode 16 is kept off when the output voltage V _CC of the DC voltage stabilizing circuit 5 is at a specified value, and turned on when it is lower than the specified value, such as when the power is turned on or off. Select the constant voltage value so that it operates as follows. When the constant voltage diode 16 turns on, the switch element 18 is turned on, and when the switch element 18 turns on, both ends of the capacitor 8 are short-circuited, and this short circuit ensures that a reset signal is sent from the level detector 11. generate.

<Explanation of operation of the invention> FIG. 4 shows a waveform diagram for explaining the operation of this invention. FIG. 4A shows the state of the power switch 2. Here, a case is shown in which the switch is turned on at time _t1 and turned off at time _t2 . Fourth
4B shows the smoothed output voltage of the main rectifying and smoothing circuit 4, and FIG. 4C shows the rectifying and smoothing output voltage of the auxiliary rectifying and smoothing circuit 12. As shown in FIG. 4C, the sub-rectifying and smoothing circuit 1
2 has a characteristic that the voltage decreases at a relatively slow speed when the power is cut off. This can be realized because the load on the sub-rectifying and smoothing circuit 12 is only the error amplifier 13 and the reference voltage generating circuit 14, and the load current is small.

The output voltage V _CC of the DC voltage stabilizing circuit 5 is at the time t ₁ when the power switch is turned on, as shown in FIG. 4D.
It rises with a delay from t2 and falls with a delay from the time _t2 when it is turned off.

Here, the output voltage V _A of the error amplifier 13 changes as shown in FIG. 4E. In other words, until the output voltage V _CC of the DC voltage stabilizing circuit 5 reaches a specified value and when the output voltage V _CC falls below the specified voltage, the error amplifier 13 operates the transistor 15 to increase the output voltage V _CC . Outputs a polar signal that reduces the resistance between collector and emitter. However, since the error amplifier 13 is operated by the output voltage V _B of the sub-rectifying and smoothing circuit 12, the DC stabilized power supply 5
When the output voltage V _CC of the error amplifier 13 becomes lower than the specified value, the output voltage V _A of the error amplifier 13 becomes higher than the voltage during normal operation and becomes a voltage close to the output voltage V _B of the sub-rectifying and smoothing circuit 12 . Therefore, when the power switch 2 is turned on and when it is turned off, the output voltage V _A of the error amplifier 13 always outputs a high voltage as shown in FIG. 4E. By applying this high voltage to the voltage dividing circuit 17, the constant voltage diode 16 is controlled to be turned on, and the switch element 18 is controlled to be turned on. When the output voltage V _CC of the DC voltage stabilization circuit 5 is at the specified value, the output voltage V _A of the error amplifier 13 is only slightly higher than the output voltage V _CC of the DC voltage stabilization circuit 5. be. Therefore, when the power is turned on and the device is in a steady state, the constant voltage diode 16 is controlled to be off, and the switch element 18 is also controlled to be off. Figure 4 F shows switch element 1
8 on and off states. Switch element 18
While the capacitor 8 is controlled to be on, both ends of the capacitor 8 are short-circuited, so the charging voltage is held at 0.
The output of the level detection circuit 11 becomes H logic as shown in FIG. 4H, and a reset signal _RS1 is output.

When the output voltage V _CC of the DC voltage stabilizing circuit 5 reaches the specified value, the output voltage V _A of the error amplifier 13 decreases, and when the switch element 18 is turned off, the capacitor 8 stabilizes the DC voltage through the resistor 9. Since the charging voltage is charged by the output voltage V _CC of the conversion circuit 5, the charging voltage starts to rise as shown in FIG. 4G.
When the charging voltage of the capacitor 8 becomes equal to or higher than the high level threshold value V _TH of the level detection circuit 11, the output of the level detection circuit 11 becomes L logic.

Therefore, when power switch 2 is turned on, the 4th
As shown in FIG. H, the reset signal RS ₁ is output from before the output voltage V _CC of the DC voltage stabilizing circuit 5 reaches the specified value until a certain period of time after it reaches the specified value.

On the other hand, when the power switch 2 is turned off, the smoothed output voltage of the main rectifying and smoothing circuit 4 starts to decrease as shown in _FIG . When the voltage cannot be maintained, the output V _A of the error amplifier 13 becomes a high voltage, the voltage regulator diode 16 is turned on, and the switch element 18 is turned on.
is also controlled on. Therefore, the capacitor 8 is rapidly discharged and its charging voltage becomes 0, and the output of the level detection circuit 11 becomes H logic as shown in FIG. 4H, and the reset signal _RS2 is output. This reset signal _RS2 is output almost at the same time as the output voltage V _CC of the DC voltage stabilizing circuit 5 becomes equal to or less than the specified value, and the logic circuit of the load is reliably reset.

Thereafter, the output voltage V _B of the sub-rectifying and smoothing circuit 12 decreases, and the output voltage V _A of the error amplifier 13 decreases, and the constant voltage diode 16 is turned off and the switch element 18 is also turned off, so that the capacitor 8 Charging begins again through the resistor 9, but at that point the output voltage V _CC of the DC voltage stabilizing circuit 5 has dropped to almost OV, so
The charging voltage of capacitor 8 increases only slightly,
The high level threshold V _TH of the level detection circuit 11 is not reached.

<Effects of the Invention> As explained above, according to this invention, a reset signal can be reliably generated not only when the power is turned on but also when it is turned off. However, since the reset signal is output at the same time as the output voltage V _CC of the DC voltage stabilizing circuit 5 becomes lower than the specified value when the power is turned off, it is possible to initialize the load logic circuit before it operates abnormally. can. Furthermore, for instantaneous power outages in which the power is cut off for only a short period of time,
If that time is sufficiently short and the drop in the output voltage of the main rectifying and smoothing circuit 4 is small and the output voltage V _CC of the DC voltage stabilizing circuit 5 maintains a specified value, the output voltage of the error amplifier 13 Since V _A does not rise, no reset signal is output, and the load logic circuit can continue to operate normally. In addition, in the event of a momentary power outage, if the power is cut off for a certain length of time and the output voltage V _CC of the DC voltage stabilizing circuit 5 once drops below the specified value and then returns to the specified value, the switch element 18 is controlled to be on once, and charging starts after the charging voltage of capacitor 8 is completely discharged to OV, so the reset signal is output once and the load logic circuit is reliably reset before operation starts. Start. In this case, the reset signal _RS2 when the power is off and the reset signal _RS1 when the power is on are output continuously.

Therefore, according to this invention, when the power supply voltage supplied to a load including a logic circuit drops below a specified value and a reset is necessary, a reliable reset signal is immediately output in any case, and there is no need for a reset. Since the reset signal is not output at certain times, the reliability of the device can be improved, and the effect is extremely large in practical use.

In the above description, the level detection circuit 11 is powered by the output voltage V _CC of the DC voltage stabilizing circuit 5, but it may be operated by the output voltage of the sub-rectifying and smoothing circuit 12. Further, if the voltage doubler rectifier circuit 12 is constructed, the tertiary winding of the transformer 3 can be omitted.

[Brief explanation of drawings]

Figure 1 is a block diagram for explaining a conventional DC voltage stabilization circuit with a reset signal generation function.
3 is a block diagram showing an embodiment of this invention, and FIG. 4 is a waveform diagram for explaining the operation. 1: Commercial power supply, 2: Power switch, 4: Main rectifier smoothing circuit, 5: DC voltage stabilization circuit, 8: Capacitor, 11: Level detection circuit, 12: Sub-rectifier smoothing circuit, 13: Error amplifier, 14: Reference Voltage generating circuit, 18: switch element.

Claims (1)

[Claims for Utility Model Registration] A: A main rectifier and smoothing circuit; B: A voltage higher than the smoothed output voltage of the main rectifier and smoothing circuit, and when the power is turned off, the output voltage is lower than the voltage drop rate of the main rectifier and smoothing circuit. A sub-rectifying and smoothing circuit in which the relationship between the time constant of the smoothing circuit and the load current is set so as to decrease; C a reference voltage generation circuit that generates a constant reference voltage from the output voltage of this sub-rectifying and smoothing circuit; D this A voltage stabilizing circuit that stabilizes the output voltage of the main rectifying and smoothing circuit using the reference voltage output from the reference voltage generating circuit; a switch element that is controlled to be turned on when the error amplifier used in the voltage stabilization circuit outputs a control voltage larger than a predetermined value;
A capacitor whose charging voltage is quickly discharged through the switch element each time the switch element is turned on, and a Schmitt trigger circuit to which the voltage of this capacitor is applied to the input terminal, the voltage of the capacitor G outputs different logic signals depending on whether it is below a predetermined value or above a predetermined value,
A voltage stabilizing circuit with a reset signal generation function, comprising: a level detection circuit that outputs a logic signal as a reset signal when the voltage of the capacitor is below a predetermined value.