CN113391690A - FLASH abnormal power failure protection circuit, device and method - Google Patents
FLASH abnormal power failure protection circuit, device and method Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
Abstract
The invention relates to a FLASH abnormal power failure protection circuit, comprising: the power supply management circuit is electrically connected with the FLASH power supply and the FLASH and is used for providing a direct current power supply signal for the FLASH, detecting the real-time voltage value of the FLASH power supply and generating a low-voltage state signal under the condition that the real-time voltage value is reduced to a preset voltage threshold value; the power-down protection control circuit is electrically connected with the power management circuit and the FLASH and used for providing a state control signal for the FLASH, changing the level state of the state control signal according to the received low-voltage state signal so as to control the programming enabling signal of the FLASH to be changed from an enabling state to an invalid state within a first preset time and control the direct-current power supply signal to continuously supply power for a second preset time; the starting time of the first preset time and the starting time of the second preset time are both the time when the real-time voltage value reaches the preset voltage threshold, and the first preset time is less than the second preset time. The FLASH abnormal power failure protection circuit can realize the orderly power failure of the FLASH under the abnormal power failure condition, and avoids data loss.
Description
Technical Field
The invention relates to the field of design of nonvolatile memories, in particular to a FLASH abnormal power failure protection circuit, device and method.
Background
FLASH memory belongs to one type of memory devices. FLASH memory is a Non-Volatile (Non-Volatile) memory that can hold data for a long time without current supply. The existing FLASH provided by FLASH manufacturers usually does not have a peripheral protection circuit, and in the programming process, if accidental power failure accidents occur to cause accidental power failure of FLASH, not only data loss can be caused, but also physical damage can be caused to FLASH, and the service life of FLASH is seriously influenced.
Disclosure of Invention
Therefore, it is necessary to provide a FLASH abnormal power failure protection circuit, device and method for solving the problems of data loss and FLASH life influence caused by FLASH abnormal power failure.
A kind of FLASH unusual power-down protection circuit, including: the power supply management circuit is electrically connected with a FLASH power supply and the FLASH and is used for providing a direct current power supply signal for the FLASH, detecting a real-time voltage value of the FLASH power supply and generating a low-voltage state signal under the condition that the real-time voltage value is reduced to a preset voltage threshold value; the power-down protection control circuit is electrically connected with the power management circuit and the FLASH and is used for providing a state control signal for the FLASH, changing the level state of the state control signal according to the received low-voltage state signal so as to control the programming enabling signal of the FLASH to be changed from an enabling state to an invalid state within a first preset time and control the direct-current power supply signal to continuously supply power for a second preset time; the starting time of the first preset time and the starting time of the second preset time are both the time when the real-time voltage value reaches the preset voltage threshold, and the first preset time is smaller than the second preset time.
According to the FLASH abnormal power-down protection circuit, after the FLASH power supply is powered off or cannot be normally powered on, delayed power-down of the FLASH and proper processing of FLASH control signals and data signals are realized through the mutual matching of the power management circuit and the power-down protection control circuit, so that not only can data loss caused by sudden power-down be avoided, but also physical damage to the FLASH caused by sudden power-down can be avoided.
In one embodiment, a power management circuit includes: the rectification voltage boosting unit is electrically connected with the FLASH power supply and is used for generating an initial direct current power supply signal according to the real-time voltage value of the FLASH power supply; the low-dropout linear voltage stabilizing circuit is electrically connected with the rectification boosting unit and the power-down protection control circuit and is used for generating the direct-current power supply signal according to the received initial direct-current power supply signal; the low-voltage detection circuit is electrically connected with the rectification boosting unit and the power-down protection control circuit and is used for detecting the initial direct-current power supply signal so as to generate the low-voltage state signal within a third preset time from the moment that the real-time voltage value reaches the preset voltage threshold value; the third preset time is less than the first preset time.
In one embodiment, the power management circuit further comprises: and the power-on reset circuit is electrically connected with the rectifying and boosting unit and the power-down protection control circuit and is used for generating a power-on reset signal according to the initial direct-current power supply signal so as to control the power-on reset of the FLASH.
In one embodiment, the power down protection control circuit includes: and the FLASH power-down controller is electrically connected with the power management circuit and used for providing a state control signal for the FLASH and changing the working state of the state machine of the FLASH according to the received low-voltage state signal so as to change the level state of the state control signal.
In one embodiment, the power down protection control circuit further includes: the FLASH power-down controller is electrically connected with the FLASH through the output isolation device; and/or the input isolation device, wherein the FLASH is electrically connected with the FLASH power-down controller through the input isolation device.
In one embodiment, the FLASH power down controller is configured to: and controlling the state control signal to change from a first level state to a second level state according to the received low-voltage state signal.
In one embodiment, the first level state is a low level and the second level state is a high level.
In one embodiment, the rectifying and boosting unit comprises a spare energy storage element.
A kind of FLASH unusual power-fail protection device, including: FLASH and the FLASH abnormal power failure protection circuit of any of the above embodiments; and the FLASH abnormal power-down protection circuit is electrically connected with the FLASH and is used for performing abnormal power-down protection on the FLASH.
A FLASH abnormal power failure protection method comprises the following steps: providing a direct current power supply signal to the FLASH on the basis of a real-time voltage value provided by a FLASH power supply, detecting the real-time voltage value of the FLASH power supply, and generating a low-voltage state signal under the condition that the real-time voltage value is reduced to a preset voltage threshold value; changing the level state of a state control signal provided for the FLASH according to the received low-voltage state signal so as to control the programming enabling signal of the FLASH to be changed from an enabling state to an invalid state within a first preset time and control the direct-current power supply signal to continuously supply power for a second preset time; the starting time of the first preset time and the starting time of the second preset time are both the time when the real-time voltage value reaches the preset voltage threshold, and the first preset time is smaller than the second preset time.
According to the FLASH abnormal power failure protection method, after the FLASH power supply is powered off or cannot be normally powered on, delayed power failure of the FLASH and proper processing of FLASH control signals and data signals can be realized, data loss caused by sudden power failure can be avoided, and physical damage to the FLASH caused by sudden power failure can also be avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings needed to be used in the description of the embodiments are briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and it is obvious for those skilled in the art to obtain drawings of other embodiments based on these drawings without any creative effort.
Fig. 1 is a block diagram of a FLASH abnormal power down protection circuit in an embodiment of the present application.
Fig. 2 is a timing diagram illustrating a state change of a part of signals when the FLASH is abnormally powered down in an embodiment of the present application.
Fig. 3 to fig. 8 are block diagrams of structures of several FLASH abnormal power down protection circuits in other embodiments of the present application.
Fig. 9 is a block diagram of a power down protection control circuit in an embodiment of the present application.
Fig. 10 is a flowchart of a FLASH abnormal power down protection method in an embodiment of the present application.
The reference numbers illustrate: 1. a power management circuit; 11. a rectification and voltage boosting unit; 111. a backup energy storage element; d1, a diode; 12. a low dropout linear voltage regulator circuit; 13. a low voltage detection circuit; 14. a power-on reset circuit; 2. a power down protection control circuit; 21. a FLASH power-down controller; 22. an output isolation device; 23. an input isolation device; 3. a FLASH power supply; 4. and (5) a FLASH power switch.
Detailed Description
To facilitate an understanding of the invention, the invention will now be described more fully with reference to the accompanying drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used in the description of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the term "and/or" includes any and all combinations of one or more of the associated listed items.
In describing positional relationships, unless otherwise specified, when an element such as a layer, film or substrate is referred to as being "on" another layer, it can be directly on the other layer or intervening layers may also be present. Further, when a layer is referred to as being "under" another layer, it can be directly under, or one or more intervening layers may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
Where the terms "comprising," "having," and "including" are used herein, another element may be added unless an explicit limitation is used, such as "only," "consisting of … …," etc. Unless mentioned to the contrary, terms in the singular may include the plural and are not to be construed as being one in number.
As shown in fig. 1, an embodiment of the present application provides a FLASH abnormal power down protection circuit, which includes: the power supply management circuit 1 is electrically connected with the FLASH power supply 3 and the FLASH and is used for providing a direct current power supply signal for the FLASH, detecting the real-time voltage value of the FLASH power supply 3 and generating a low-voltage state signal under the condition that the real-time voltage value is reduced to a preset voltage threshold value; the power-down protection control circuit 2 is electrically connected with the power management circuit 1 and the FLASH and is used for providing a state control signal for the FLASH, changing the level state of the state control signal according to the received low-voltage state signal so as to control the programming enable signal of the FLASH to be changed from an enable state to an invalid state within a first preset time t1 and control the direct-current power supply signal to continuously supply power for a second preset time t 2; the starting time of the first preset time t1 and the starting time of the second preset time t2 are both the time when the real-time voltage value reaches the preset voltage threshold, and the first preset time t1 is less than the second preset time t 2.
Specifically, please refer to fig. 2, wherein the real-time voltage value provided by the FLASH power supply 3 is denoted as VDD, the LOW-voltage state signal is denoted as LOW-DET, the WEB signal is a write enable signal, the PROG is a program enable signal, both the WEB signal and the PROG belong to the state control signal provided by the power-down protection control circuit 2 to the FLASH, and the dc power supply signal directly supplying power to the FLASH is denoted as VDD-FLASH.
When the real-time voltage value VDD supplied from the FLASH power supply 3 changes from the high level to the LOW level, the power management circuit 1 may detect the voltage change of the FLASH power supply 3 in time, and generate the LOW-voltage state signal LOW-DET within a third preset time t3 from the time when the real-time voltage value VDD reaches a preset voltage threshold (e.g., changes from the high level to the LOW level). The power down protection control circuit 2, after receiving the LOW-DET signal, sequentially adjusts the level states of the respective state control signals to change from the enabled state to the disabled state. The control state signal refers to a signal sent by the power down protection control circuit 2 to the FLASH to adjust the state of the FLASH, such as a chip select signal, a write enable signal, an erase signal, a program enable signal, and the like. As an example, for the write enable signal WEB that is active LOW, the power down protection control circuit 2 adjusts the WEB signal from LOW to high state after receiving the LOW-DET signal. For the program enable signal PROG being active at high level, the power down protection control circuit 2 changes the PROG signal from high level to low level within a first preset time t1 after VDD changes from high level to low level, wherein the first preset time t1 is greater than the third preset time t 3. As an example, the first preset time t1 is equal to or greater than 50 microseconds, and may be, for example, 50 microseconds, 55 microseconds, 60 microseconds, or 70 microseconds. Optionally, after receiving the LOW voltage state signal LOW-DET, the power down protection control circuit 2 may adjust the level state of the state control signal, and may also clear the data bus and the address bus of the FLASH.
The real-time voltage VDD provided by the FLASH power supply 3 is processed by the power management circuit 1 to obtain a direct current power supply signal VDD-FLASH which can directly supply power to the FLASH. The VDD-FLASH does not go low immediately after VDD goes low but continues to power the FLASH for at least a second preset time t 2. As an example, the second preset time t2 is greater than or equal to 100 microseconds, and may be, for example, 100 microseconds, 110 microseconds, or 120 microseconds.
The starting time of the first preset time t1 and the starting time of the second preset time t2 are the same, and are both the time when the real-time voltage value decreases to the preset voltage threshold, for example, the time when VDD changes from high level to low level. And, the first preset time t1 is set to be less than the second preset time t 2.
According to the FLASH abnormal power failure protection circuit, after the FLASH power supply 3 is powered off or cannot normally supply power, delayed power failure of the FLASH and proper processing of FLASH control signals and data signals are realized through the mutual matching of the power management circuit 1 and the power failure protection control circuit 2, so that not only can data loss caused by sudden power failure be avoided, but also physical damage to the FLASH caused by sudden power failure can be avoided.
In one embodiment, as shown in fig. 3, the power management circuit 1 includes: the rectification voltage boosting unit 11 is electrically connected with the FLASH power supply 3 and is used for generating an initial direct current power supply signal according to the real-time voltage value of the FLASH power supply 3; the low-dropout linear voltage stabilizing circuit 12 is electrically connected with the rectifying and boosting unit 11 and the power-down protection control circuit 2 and is used for generating a direct-current power supply signal according to the received initial direct-current power supply signal; the low-voltage detection circuit 13 is electrically connected with the rectification voltage boosting unit 11 and the power failure protection control circuit 2 and is used for detecting an initial direct-current power supply signal so as to generate a low-voltage state signal within a third preset time t3 from the moment when the real-time voltage value reaches a preset voltage threshold; the third preset time t3 is less than the first preset time t 1.
As an example, when the FLASH power supply 3 provides direct current, the rectifying and boosting unit 11 may include a diode D1 and a backup energy storage element 111, as shown in fig. 4. The standby energy storage element 111 can be a large-capacitance energy storage element and is used for storing standby electric energy, and when the power supply 3 fails and is suddenly powered off, the standby energy storage element 111 can continue to supply power to the FLASH and the power-down protection control circuit 2, so that the ordered power-down process of the FLASH is realized, and data loss and physical damage are avoided. The diode D1 has unidirectional guidance, and current can only flow from the FLASH power supply 3 to the power management circuit 1, so that when the standby energy storage element 111 is activated to supply power, the diode D1 can prevent the current from flowing back to the FLASH power supply 3, and damage to the FLASH power supply 3 is avoided.
The low-voltage detection circuit 13 is electrically connected with the rectification voltage boosting unit 11 and the power-down protection control circuit 2, and is used for detecting an initial direct-current power supply signal, and the change of the real-time voltage value of the FLASH power supply 3 can be obtained through the initial direct-current power supply signal. When the real-time voltage value is decreased to the preset voltage threshold, the low-voltage detection circuit 13 generates a low-voltage state signal within a third preset time t3, and sends the low-voltage state signal to the power-down protection control circuit 2. The third preset time t3 is less than the first preset time t1 and the second preset time t 2.
Optionally, when the voltage provided by the FLASH power supply 3 is an alternating current, a plurality of diodes D1 may be disposed in the rectifying and boosting unit 11 to construct a rectifying circuit, so as to change the alternating current into the direct current, and obtain an initial direct current power supply signal. After the initial dc power supply signal is processed by the low-dropout linear voltage stabilizing circuit 12, a dc power supply signal capable of being input to the FLASH can be obtained. Firstly, when the voltage provided by the FLASH power supply 3 is insufficient and the normal working state of the FLASH cannot be maintained, the standby energy storage element 111 can be started to perform auxiliary power supply, so as to improve the voltage of the initial direct current power supply signal and ensure the normal working of the FLASH.
In one embodiment, as shown in fig. 5, the FLASH abnormal power down protection circuit further includes a FLASH power switch 4 connected to the low dropout linear voltage regulator 12 and the FLASH. The direct current power supply signal output by the low dropout linear voltage stabilizing circuit 12 passes through the FLASH power switch 4 and then is input into FLASH. The FLASH power switch 4 can control whether the direct current supply signal can reach the FLASH. When the power switch 4 of the FLASH is in an off state, any power signal cannot be transmitted to the FLASH, the FLASH is in a power-off state, and the external cannot read and write data and/or control the state of the FLASH. When the FLASH power switch 4 is in the on state, the external world can read and write data and/or control the state of the FLASH power switch.
In one embodiment, as shown in fig. 6, the power management circuit 1 further includes a power-on reset circuit 14. The power-on reset circuit 14 is electrically connected to the rectifying and boosting unit 11 and the power-down protection control circuit 2, and is configured to generate a power-on reset signal according to the initial dc power supply signal to control the power-on reset of the FLASH.
Specifically, after the FLASH power supply 3 recovers the normal power supply, the power-on reset circuit 14 may detect the change of the initial dc power supply signal in time, generate a power-on reset signal and send the power-on reset signal to the power-down protection control circuit 2, and the power-down protection control circuit 2 sequentially recovers the level state of each signal port of the FLASH.
In one embodiment, as shown in fig. 7, the power down protection control circuit 2 includes: and the FLASH power-down controller 21 is electrically connected with the power management circuit 1 and the FLASH and is used for providing a state control signal for the FLASH and changing the working state of a state machine of the FLASH according to the received low-voltage state signal so as to change the level state of the state control signal.
Specifically, the FLASH power-down controller 21 is internally provided with a state machine (not shown in the figure) for controlling the power-up/power-down sequence. After the FLASH power-down controller 21 receives the LOW-voltage state signal LOW-DET, the level state of each state control signal can be changed by the control state machine according to the timing sequence shown in fig. 2, and each state signal of the FLASH is adjusted from the enabled state to the disabled state.
In one embodiment, as shown in fig. 8, the power down protection control circuit 2 further includes: the output isolation device 22, the FLASH power-down controller 21 is electrically connected with the FLASH through the output isolation device 22; and/or an input isolation device 23, the FLASH being electrically connected to the FLASH power down controller 21 via the input isolation device 23.
When a sudden power failure occurs, for signals of which the state of the FLASH power-down controller 21 cannot be adjusted, the output isolation device 22 may forcibly pull down or pull up the states of these signals so that the signals belong to a known state, but not an unknown state, thereby avoiding an unknown error occurring during power-up recovery of the FLASH. Optionally, the output isolation device 22 may further be configured to latch each state control signal and data sent to the FLASH, and the input isolation device 23 may be configured to latch data output from the FLASH, where when the power supply is recovered to be normal, the FLASH may quickly recover the level state of the data and each state control signal, and may also quickly determine data output before power failure, so that the FLASH may start to operate from the state before power failure after being powered on again.
As an example, the internal structure and signal processing procedure of the power down protection control circuit 2 are as shown in fig. 9. Where, PORB is a power-on reset signal, PROG _ PRE is a PRE-programming enable signal, ERASE _ PRE is a PRE-ERASE enable signal, ADDR _ PRE is a PRE-address signal, DATAIN _ PRE is a PRE-data input signal, WEB _ PRE is a PRE-write enable signal, CEB _ PRE is a PRE-chip select signal, LOW-DET is a LOW-voltage state signal, and DOUT is a data output signal. When the FLASH power-down controller 21 receives the LOW-voltage state signal LOW-DET, the control state machine adjusts the level states of the ERASE signal ERASE, the address signal ADDR, the data input signal DATAIN, the write enable signal WEB, and the chip select signal CEB. As an example, the adjustment timing diagram of the partial signals refers to fig. 2. Each state control signal after the state adjustment is transmitted to the FLASH through the output isolation device 22, and the output isolation device 22 records the level state of each state control signal. And the data signal DOUT output by the FLASH is transmitted to the FLASH power failure controller through the input isolation device. The input isolation device 23 backs up DOUT.
In one embodiment, the FLASH power-down controller 21 is configured to control the state control signal to change from the first level state to the second level state according to the received low voltage state signal. The first level state is a low level, and the second level state is a high level; alternatively, the first level is a high state and the second level is a low state.
The application also discloses a FLASH abnormal power failure protection device, which comprises: FLASH and the FLASH abnormal power failure protection circuit of any of the above embodiments. The FLASH abnormal power-down protection circuit is electrically connected with the FLASH and used for performing abnormal power-down protection on the FLASH.
The application also discloses a FLASH abnormal power failure protection method, which comprises the following steps:
s10: and providing a direct current power supply signal for the FLASH based on the real-time voltage value provided by the FLASH power supply 3, detecting the real-time voltage value of the FLASH power supply 3, and generating a low-voltage state signal under the condition that the real-time voltage value is reduced to a preset voltage threshold value.
S20: changing the level state of the state control signal provided to the FLASH according to the received low-voltage state signal so as to control the programming enable signal of the FLASH to change from an enable state to an invalid state within a first preset time t1 and control the direct current power supply signal to continuously supply power for a second preset time t 2; the starting time of the first preset time t1 and the starting time of the second preset time t2 are both the time when the real-time voltage value reaches the preset voltage threshold, and the first preset time t1 is less than the second preset time t 2.
In particular, the above method can be understood in conjunction with fig. 1 and 2. The real-time voltage value provided by the FLASH power supply 3 is recorded as VDD, the LOW-voltage state signal is recorded as LOW-DET, the WEB signal is one of state control signals for controlling FLASH, the PROG is a programming enable signal, and the direct-current power supply signal capable of directly supplying power to FLASH is recorded as VDD-FLASH.
When the real-time voltage value VDD provided by the FLASH power supply 3 changes from a high level to a LOW level, the LOW-voltage state signal LOW-DET changes from a LOW level to a high level, that is, the LOW-voltage state signal LOW-DET changes from an inactive state to an enabled state, and transmits information of power supply voltage abnormality (power failure or voltage lower than a preset voltage threshold) to the power-down protection control circuit 2.
After the power down protection control circuit 2 receives the LOW-DET signal, the level states of the state control signals are orderly adjusted to change from the enabled state to the disabled state. The control status signal refers to a signal sent to the FLASH to adjust the status of the FLASH, such as an erase signal and a program enable signal. As an example, for a WEB signal that is active LOW, the power down protection control circuit 2 adjusts the WEB signal from LOW to high after receiving the LOW-DET signal. For the program enable signal PROG being active high, the power down protection control circuit 2 changes the PROG signal from high to LOW at a first preset time t1 after receiving the LOW-DET signal. As an example, the first preset time t1 is greater than 50 microseconds, and may be, for example, 50 microseconds, 55 microseconds, 60 microseconds, or 70 microseconds. Optionally, after receiving the LOW-DET signal, the power down protection control circuit 2 may adjust the level state of the state control signal, and may also clear the data bus and the address bus of the FLASH.
The real-time voltage VDD provided by the FLASH power supply 3 is processed by the power management circuit 1 to obtain a direct current power supply signal VDD-FLASH which can directly supply power to the FLASH. The VDD-FLASH does not go low immediately after VDD goes low but continues to power the FLASH for at least a second preset time t 2. As an example, the second preset time t2 may be 100 microseconds, 110 microseconds, or 120 microseconds.
The starting time of the first preset time t1 and the starting time of the second preset time t2 are the same, and are both the time when the real-time voltage value decreases to the preset voltage threshold, for example, the time when VDD changes from high level to low level. And, the length of the first preset time t1 is set to be less than the length of the second preset time t 2.
The technical features of the embodiments described above may be arbitrarily combined, and for the sake of brevity, all possible combinations of the technical features in the embodiments described above are not described, but should be considered as being within the scope of the present specification as long as there is no contradiction between the combinations of the technical features.
The above-mentioned embodiments only express several embodiments of the present invention, and the description thereof is more specific and detailed, but not construed as limiting the scope of the invention. It should be noted that, for a person skilled in the art, several variations and modifications can be made without departing from the inventive concept, which falls within the scope of the present invention. Therefore, the protection scope of the present patent shall be subject to the appended claims.
Claims (10)
1. A FLASH abnormal power failure protection circuit is characterized by comprising:
the power supply management circuit is electrically connected with a FLASH power supply and the FLASH and is used for providing a direct current power supply signal for the FLASH, detecting a real-time voltage value of the FLASH power supply and generating a low-voltage state signal under the condition that the real-time voltage value is reduced to a preset voltage threshold value;
the power-down protection control circuit is electrically connected with the power management circuit and the FLASH and is used for providing a state control signal for the FLASH, changing the level state of the state control signal according to the received low-voltage state signal so as to control the programming enabling signal of the FLASH to be changed from an enabling state to an invalid state within a first preset time and control the direct-current power supply signal to continuously supply power for a second preset time;
the starting time of the first preset time and the starting time of the second preset time are both the time when the real-time voltage value reaches the preset voltage threshold, and the first preset time is smaller than the second preset time.
2. The FLASH abnormal power down protection circuit of claim 1, wherein the power management circuit comprises:
the rectification voltage boosting unit is electrically connected with the FLASH power supply and is used for generating an initial direct current power supply signal according to the real-time voltage value of the FLASH power supply;
the low-dropout linear voltage stabilizing circuit is electrically connected with the rectification boosting unit and the power-down protection control circuit and is used for generating the direct-current power supply signal according to the received initial direct-current power supply signal;
the low-voltage detection circuit is electrically connected with the rectification boosting unit and the power-down protection control circuit and is used for detecting the initial direct-current power supply signal so as to generate the low-voltage state signal within a third preset time from the moment that the real-time voltage value reaches the preset voltage threshold value; the third preset time is less than the first preset time.
3. The FLASH abnormal power down protection circuit of claim 2, wherein the power management circuit further comprises:
and the power-on reset circuit is electrically connected with the rectifying and boosting unit and the power-down protection control circuit and is used for generating a power-on reset signal according to the initial direct-current power supply signal so as to control the power-on reset of the FLASH.
4. The FLASH abnormal power down protection circuit according to any one of claims 1-3, wherein the power down protection control circuit comprises:
and the FLASH power-down controller is electrically connected with the power management circuit and used for providing a state control signal for the FLASH and changing the working state of the state machine of the FLASH according to the received low-voltage state signal so as to change the level state of the state control signal.
5. The FLASH abnormal power-down protection circuit according to claim 4, wherein the power-down protection control circuit further comprises:
the FLASH power-down controller is electrically connected with the FLASH through the output isolation device; and/or
And the FLASH is electrically connected with the FLASH power-down controller through the input isolation device.
6. The FLASH abnormal power down protection circuit according to any of claims 1-3, wherein the FLASH power down controller is configured to:
and controlling the state control signal to change from a first level state to a second level state according to the received low-voltage state signal.
7. The FLASH abnormal power down protection circuit of claim 6, wherein the first level state is a low level and the second level state is a high level.
8. The FLASH abnormal power down protection circuit of claim 2, wherein the rectifying and boosting unit comprises a backup energy storage element.
9. A FLASH abnormal power failure protection device is characterized by comprising:
FLASH; and
the abnormal power-down protection circuit of any one of claims 1-8, electrically connected to said FLASH, for performing abnormal power-down protection on said FLASH.
10. A FLASH abnormal power failure protection method is characterized by comprising the following steps:
providing a direct current power supply signal to the FLASH on the basis of a real-time voltage value provided by a FLASH power supply, detecting the real-time voltage value of the FLASH power supply, and generating a low-voltage state signal under the condition that the real-time voltage value is reduced to a preset voltage threshold value;
changing the level state of a state control signal provided for the FLASH according to the received low-voltage state signal so as to control the programming enabling signal of the FLASH to be changed from an enabling state to an invalid state within a first preset time and control the direct-current power supply signal to continuously supply power for a second preset time;
the starting time of the first preset time and the starting time of the second preset time are both the time when the real-time voltage value reaches the preset voltage threshold, and the first preset time is smaller than the second preset time.
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