CN113391690B - FLASH abnormal power-down protection circuit, device and method - Google Patents
FLASH abnormal power-down protection circuit, device and method Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/26—Power supply means, e.g. regulation thereof
- G06F1/30—Means for acting in the event of power-supply failure or interruption, e.g. power-supply fluctuations
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
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Abstract
The invention relates to a FLASH abnormal power-down protection circuit, which comprises: the power management circuit is electrically connected with the FLASH power supply and the FLASH and is used for providing a direct current power supply signal for the FLASH, detecting the real-time voltage value of the FLASH power supply and generating a low-voltage state signal under the condition that the real-time voltage value is reduced to a preset voltage threshold value; the power-down protection control circuit is electrically connected with the power management circuit and the FLASH, and is used for providing a state control signal for the FLASH, changing the level state of the state control signal according to the received low-voltage state signal so as to control the programming enabling signal of the FLASH to be changed from the enabling state to the invalid state within a first preset time and control the direct-current power supply signal to continuously supply power for a second preset time; the starting time of the first preset time and the starting time of the second preset time are the time when the real-time voltage value reaches the preset voltage threshold value, and the first preset time is smaller than the second preset time. The FLASH abnormal power-down protection circuit can realize orderly power-down of the FLASH under the abnormal power-down condition, and avoid data loss.
Description
Technical Field
The invention relates to the field of design of nonvolatile memories, in particular to a FLASH abnormal power-down protection circuit, a device and a method.
Background
FLASH memory is one type of memory device. FLASH memory is a Non-Volatile memory that can retain data for a long time even without current supply. The FLASH provided by the existing FLASH manufacturer generally does not have a peripheral protection circuit, if unexpected power failure accidents occur in the programming process, the FLASH is powered down accidentally, not only can data be lost, but also physical damage can be caused to the FLASH, and the service life of the FLASH is seriously influenced.
Disclosure of Invention
Based on the above, it is necessary to provide a circuit, a device and a method for protecting the FLASH from abnormal power failure, aiming at the problems of data loss caused by the abnormal power failure of the FLASH and the influence on the service life of the FLASH.
A FLASH abnormal power down protection circuit comprising: the power management circuit is electrically connected with the FLASH power supply and the FLASH and is used for providing a direct current power supply signal for the FLASH, detecting a real-time voltage value of the FLASH power supply and generating a low-voltage state signal under the condition that the real-time voltage value is reduced to a preset voltage threshold value; the power-down protection control circuit is electrically connected with the power management circuit and the FLASH, and is used for providing a state control signal for the FLASH, changing the level state of the state control signal according to the received low-voltage state signal so as to control the programming enabling signal of the FLASH to be changed from an enabling state to an invalid state within a first preset time and control the direct-current power supply signal to continuously supply power for a second preset time; the starting time of the first preset time and the starting time of the second preset time are the time when the real-time voltage value reaches the preset voltage threshold value, and the first preset time is smaller than the second preset time.
The FLASH abnormal power-down protection circuit realizes the delay power-down of the FLASH and the proper processing of FLASH control signals and data signals through the mutual coordination of the power management circuit and the power-down protection control circuit after the power of the FLASH is off or the power of the FLASH cannot be normally supplied, so that the data loss caused by sudden power failure can be avoided, and the physical damage to the FLASH caused by sudden power failure can also be avoided.
In one embodiment, a power management circuit includes: the rectification boosting unit is electrically connected with the FLASH power supply and used for generating an initial direct current power supply signal according to the real-time voltage value of the FLASH power supply; the low-dropout linear voltage stabilizing circuit is electrically connected with the rectifying and boosting unit and the power-down protection control circuit and is used for generating the direct-current power supply signal according to the received initial direct-current power supply signal; the low-voltage detection circuit is electrically connected with the rectifying and boosting unit and the power-down protection control circuit and is used for detecting the initial direct-current power supply signal so as to generate the low-voltage state signal in a third preset time from the moment that the real-time voltage value reaches the preset voltage threshold value; the third preset time is smaller than the first preset time.
In one embodiment, the power management circuit further comprises: and the power-on reset circuit is electrically connected with the rectifying and boosting unit and the power-off protection control circuit and is used for generating a power-on reset signal according to the initial direct current power supply signal so as to control the FLASH power-on reset.
In one embodiment, the power down protection control circuit includes: and the FLASH power-off controller is electrically connected with the power management circuit and is used for providing a state control signal for the FLASH and changing the working state of a state machine according to the received low-voltage state signal so as to change the level state of the state control signal.
In one embodiment, the power down protection control circuit further comprises: the FLASH power-off controller is electrically connected with the FLASH through the output isolation device; and/or an input isolation device, wherein the FLASH is electrically connected with the FLASH power-off controller through the input isolation device.
In one embodiment, the FLASH power down controller is configured to: and controlling the state control signal to change from a first level state to a second level state according to the received low-voltage state signal.
In one embodiment, the first level state is low and the second level state is high.
In one embodiment, the rectifying and boosting unit comprises a standby energy storage element.
A FLASH abnormal power down protection device, comprising: FLASH and the FLASH abnormal power-down protection circuit in any embodiment; the FLASH abnormal power-down protection circuit is electrically connected with the FLASH and is used for carrying out abnormal power-down protection on the FLASH.
A FLASH abnormal power-down protection method comprises the following steps: providing a direct current power supply signal for the FLASH based on a real-time voltage value provided by the FLASH power supply, detecting the real-time voltage value of the FLASH power supply, and generating a low-voltage state signal under the condition that the real-time voltage value is reduced to a preset voltage threshold value; changing the level state of a state control signal provided for the FLASH according to the received low-voltage state signal so as to control the programming enabling signal of the FLASH to be changed from an enabling state to an invalid state within a first preset time and control the direct-current power supply signal to continuously supply power for a second preset time; the starting time of the first preset time and the starting time of the second preset time are the time when the real-time voltage value reaches the preset voltage threshold value, and the first preset time is smaller than the second preset time.
According to the FLASH abnormal power-down protection method, after the FLASH power supply is powered off or cannot normally supply power, the FLASH is delayed to be powered down and the FLASH control signals and the data signals are properly processed, so that data loss caused by sudden power failure can be avoided, and physical damage to the FLASH caused by sudden power failure can be avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the description of the embodiments will be briefly described below, it being obvious that the drawings in the following description are only some embodiments of the present application, and that other embodiments of the drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a block diagram of a FLASH abnormal power-down protection circuit according to an embodiment of the present application.
Fig. 2 is a timing diagram of a state change of a portion of signals when a FLASH is abnormally powered down in an embodiment of the present application.
Fig. 3-8 are block diagrams of several FLASH abnormal power-down protection circuits according to other embodiments of the present application.
Fig. 9 is a block diagram of a power-down protection control circuit according to an embodiment of the application.
Fig. 10 is a flow chart of a method for protecting FLASH from abnormal power failure according to an embodiment of the present application.
Reference numerals illustrate: 1. a power management circuit; 11. a rectifying and boosting unit; 111. a standby energy storage element; d1, a diode; 12. a low dropout linear voltage regulator circuit; 13. a low voltage detection circuit; 14. a power-on reset circuit; 2. a power-down protection control circuit; 21. a FLASH power-off controller; 22. an output isolation device; 23. an input isolation device; 3. a FLASH power supply; 4. FLASH power switch.
Detailed Description
In order that the invention may be readily understood, a more complete description of the invention will be rendered by reference to the appended drawings. Preferred embodiments of the present invention are shown in the drawings. This invention may, however, be embodied in many different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.
In describing positional relationships, when an element such as a layer, film or substrate is referred to as being "on" another film layer, it can be directly on the other film layer or intervening film layers may also be present, unless otherwise indicated. Further, when a layer is referred to as being "under" another layer, it can be directly under, or one or more intervening layers may also be present. It will also be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or one or more intervening layers may also be present.
Where the terms "comprising," "having," and "including" are used herein, another component may also be added unless a specifically defined term is used, such as "consisting of only," "… …," etc. Unless mentioned to the contrary, singular terms may include plural and are not to be construed as being one in number.
As shown in fig. 1, an embodiment of the present application provides a FLASH abnormal power-down protection circuit, including: the power management circuit 1 is electrically connected with the FLASH power supply 3 and the FLASH and is used for providing direct current power supply signals for the FLASH, detecting the real-time voltage value of the FLASH power supply 3 and generating a low-voltage state signal under the condition that the real-time voltage value is reduced to a preset voltage threshold value; the power-down protection control circuit 2 is electrically connected with the power management circuit 1 and the FLASH, and is used for providing a state control signal for the FLASH, changing the level state of the state control signal according to the received low-voltage state signal so as to control the programming enabling signal of the FLASH to be changed from the enabling state to the invalid state within a first preset time t1 and control the direct-current power supply signal to continuously supply power for a second preset time t2; the starting time of the first preset time t1 and the second preset time t2 are the time when the real-time voltage value reaches the preset voltage threshold, and the first preset time t1 is smaller than the second preset time t2.
Specifically, as will be understood with reference to fig. 2, the real-time voltage value provided by the FLASH power supply 3 is denoted as VDD, the LOW-voltage status signal is denoted as LOW-DET, the WEB signal is a write enable signal, the PROG is a program enable signal, the WEB signal and the PROG are all status control signals provided by the power-down protection control circuit 2 to the FLASH, and the dc power supply signal for directly supplying power to the FLASH is denoted as VDD-FLASH.
When the real-time voltage value VDD supplied from the FLASH power supply 3 changes from a high level to a LOW level, the power management circuit 1 may timely detect the voltage change of the FLASH power supply 3 and generate the LOW voltage state signal LOW-DET for a third preset time t3 from the time when the real-time voltage value VDD reaches a preset voltage threshold (e.g., changes from a high level to a LOW level). The power-down protection control circuit 2 sequentially adjusts the level states of the respective state control signals to change from the enabled state to the disabled state after receiving the LOW-DET signal. The control status signal refers to a signal sent by the power-down protection control circuit 2 to the FLASH to perform status adjustment on the signal, for example, a chip select signal, a write enable signal, an erase signal, a program enable signal, and the like. As an example, for the write enable signal WEB active LOW, the power-down protection control circuit 2 adjusts the WEB signal from a LOW level to a high level state after receiving the LOW-DET signal. For the program enable signal PROG active high, the power-down protection control circuit 2 changes the PROG signal from high to low within a first preset time t1 after VDD changes from high to low, wherein the first preset time t1 is greater than the third preset time t3. As an example, the first preset time t1 is equal to or greater than 50 microseconds, which may be, for example, 50 microseconds, 55 microseconds, 60 microseconds, or 70 microseconds. Optionally, after receiving the LOW voltage state signal LOW-DET, the power-down protection control circuit 2 may not only adjust the level state of the state control signal, but also clear the data bus and the address bus of the FLASH.
The real-time voltage VDD provided by the FLASH power supply 3 is processed by the power management circuit 1 to obtain a direct current power supply signal VDD-FLASH which can directly supply power to the FLASH. VDD-FLASH does not go low immediately after VDD goes low, but is continuously supplied with power for at least a second preset time t2. As an example, the second preset time t2 is equal to or greater than 100 microseconds, which may be, for example, 100 microseconds, 110 microseconds, or 120 microseconds.
The starting time of the first preset time t1 and the starting time of the second preset time t2 are the same, and are the time when the real-time voltage value decreases to the preset voltage threshold, for example, the time when VDD changes from high level to low level. And, the first preset time t1 is set to be smaller than the second preset time t2.
The FLASH abnormal power-down protection circuit realizes the delay power-down of FLASH and the proper treatment of FLASH control signals and data signals through the mutual cooperation of the power management circuit 1 and the power-down protection control circuit 2 after the FLASH power supply 3 is powered down or cannot normally supply power, so that the data loss caused by sudden power failure can be avoided, and the physical damage to the FLASH caused by sudden power failure can also be avoided.
In one embodiment, as shown in fig. 3, the power management circuit 1 includes: the rectification boosting unit 11 is electrically connected with the FLASH power supply 3 and is used for generating an initial direct current power supply signal according to the real-time voltage value of the FLASH power supply 3; the low-dropout linear voltage stabilizing circuit 12 is electrically connected with the rectifying and boosting unit 11 and the power-down protection control circuit 2 and is used for generating a direct-current power supply signal according to the received initial direct-current power supply signal; the low-voltage detection circuit 13 is electrically connected with the rectifying and boosting unit 11 and the power-down protection control circuit 2 and is used for detecting an initial direct-current power supply signal so as to generate a low-voltage state signal within a third preset time t3 from the moment that the real-time voltage value reaches a preset voltage threshold value; the third preset time t3 is smaller than the first preset time t1.
As an example, when the FLASH power supply 3 supplies direct current, the rectifying and boosting unit 11 may include a diode D1 and a standby energy storage element 111, as shown in fig. 4. The standby energy storage element 111 may be a large-capacitance energy storage element, and is configured to store standby electric energy, and when the FLASH power supply 3 fails and is suddenly powered off, the standby energy storage element 111 may continuously supply power to the FLASH and the power-down protection control circuit 2, so as to implement an orderly power-down process of the FLASH, and avoid data loss and physical damage. The diode D1 has unidirectional guidance, and current can only flow from the FLASH power supply 3 to the power management circuit 1, so that when the standby energy storage element 111 is started to supply power, the diode D1 can prevent current from flowing back to the FLASH power supply 3, and damage to the FLASH power supply 3 is avoided.
The low-voltage detection circuit 13 is electrically connected with the rectifying and boosting unit 11 and the power-down protection control circuit 2, and is used for detecting an initial direct current power supply signal, and the change of the real-time voltage value of the FLASH power supply 3 can be obtained through the initial direct current power supply signal. When the real-time voltage value falls to the preset voltage threshold, the low voltage detection circuit 13 generates a low voltage state signal within a third preset time t3, and sends the low voltage state signal to the power-down protection control circuit 2. The third preset time t3 is smaller than the first preset time t1 and the second preset time t2.
Alternatively, when the voltage provided by the FLASH power supply 3 is an alternating current, a plurality of diodes D1 may be provided in the rectifying and boosting unit 11 to construct a rectifying circuit, so as to implement alternating current-to-direct current, and obtain an initial direct current power supply signal. The initial dc power supply signal is processed by the low dropout linear voltage regulator 12 to obtain a dc power supply signal capable of inputting FLASH. Firstly, when the voltage provided by the FLASH power supply 3 is insufficient and the normal working state of the FLASH cannot be maintained, the standby energy storage element 111 can be started to perform auxiliary power supply so as to increase the voltage of the initial direct current power supply signal and ensure the normal working of the FLASH.
In one embodiment, as shown in fig. 5, the FLASH abnormal power-down protection circuit further comprises a FLASH power switch 4, and is connected with the low dropout linear voltage regulator 12 and the FLASH. The dc power supply signal output by the low dropout linear voltage regulator 12 is input into the FLASH via the FLASH power switch 4. The FLASH power switch 4 can control whether the dc power signal can reach FLASH. When the FLASH power switch 4 is in an off state, any power signal cannot be transmitted to the FLASH, so that the FLASH is in a power-off state, and the external world cannot read and write data and/or control the state of the FLASH. When the FLASH power switch 4 is in an on state, the outside world can read and write data and/or control the state of the FLASH power switch.
In one embodiment, as shown in fig. 6, the power management circuit 1 further includes a power-on reset circuit 14. The power-on reset circuit 14 is electrically connected with the rectifying and boosting unit 11 and the power-off protection control circuit 2, and is used for generating a power-on reset signal according to an initial direct current power supply signal so as to control FLASH power-on reset.
Specifically, after the FLASH power supply 3 resumes normal power supply, the power-on reset circuit 14 may timely detect a change of the initial dc power supply signal, generate a power-on reset signal, send the power-on reset signal to the power-off protection control circuit 2, and sequentially resume the level states of all signal ports of the FLASH by the power-off protection control circuit 2.
In one embodiment, as shown in fig. 7, the power-down protection control circuit 2 includes: the FLASH power-off controller 21 is electrically connected with the power management circuit 1 and the FLASH, and is used for providing a state control signal for the FLASH and changing the working state of a state machine according to the received low-voltage state signal so as to change the level state of the state control signal.
Specifically, the FLASH power-down controller 21 is internally provided with a state machine (not shown in the figure) for controlling the power-on/power-off timing. When the FLASH power-down controller 21 receives the LOW-voltage state signal LOW-DET, the state machine may be controlled to change the level state of each state control signal, and adjust each state signal of the FLASH from the enabled state to the disabled state, using the timing sequence shown in fig. 2.
In one embodiment, as shown in fig. 8, the power-down protection control circuit 2 further includes: the output isolation device 22, the FLASH power-off controller 21 is electrically connected with FLASH through the output isolation device 22; and/or an input isolation device 23, the FLASH is electrically connected with the FLASH power-down controller 21 via the input isolation device 23.
When the sudden power-off condition occurs, for the signals of which the FLASH power-off controller 21 fails to perform state adjustment, the output isolation device 22 can forcedly pull the states of the signals low or high so as to enable the signals to belong to a known state instead of an unknown state, and unknown errors are avoided when the FLASH is powered on and recovered. Optionally, the output isolation device 22 may be further used to latch each state control signal and data sent to the FLASH, and the input isolation device 23 may be used to latch the data output from the FLASH, where when the power supply is restored to be normal, the FLASH may quickly restore the level state of the data and each state control signal, and may also quickly determine the data output before power failure, so that the FLASH may start to operate from the state before power failure after being powered up again.
As an example, the internal structure and signal processing procedure of the power-down protection control circuit 2 are shown in fig. 9. Where PORB is a power-on reset signal, PROG_PRE is a PRE-program enable signal, ERASE_PRE is a PRE-ERASE enable signal, ADDR_PRE is a PRE-address signal, DATAIN_PRE is a PRE-data input signal, WEB_PRE is a PRE-write enable signal, CEB_PRE is a PRE-chip select signal, LOW-DET is a LOW voltage state signal, DOUT is a data output signal. When the FLASH power-down controller 21 receives the LOW voltage state signal LOW-DET, the control state machine adjusts the level states of the ERASE signal ERASE, the address signal ADDR, the data input signal DATAIN, the write enable signal WEB, and the chip select signal CEB. As an example, the timing diagram of the adjustment of the partial signals refers to fig. 2. The state control signals after the state adjustment are transmitted to the FLASH through the output isolation device 22, and the output isolation device 22 records the level state of the state control signals. And the data signal DOUT output by the FLASH is transmitted to the FLASH power-off controller through the input isolation device. The input isolation device 23 backs up DOUT.
In one embodiment, the FLASH power-down controller 21 is configured to control the state control signal to change from the first level state to the second level state in accordance with the received low voltage state signal. The first level state is a low level, and the second level state is a high level; or the first level is in a high level state and the second level is in a low level state.
The application also discloses a FLASH abnormal power-down protection device, which comprises: FLASH and the FLASH abnormal power-down protection circuit of any embodiment. The FLASH abnormal power-down protection circuit is electrically connected with the FLASH and is used for carrying out abnormal power-down protection on the FLASH.
The application also discloses a FLASH abnormal power-down protection method, which comprises the following steps:
S10: and providing a direct current power supply signal for the FLASH based on the real-time voltage value provided by the FLASH power supply 3, detecting the real-time voltage value of the FLASH power supply 3, and generating a low-voltage state signal under the condition that the real-time voltage value is reduced to a preset voltage threshold value.
S20: changing the level state of a state control signal provided for the FLASH according to the received low-voltage state signal so as to control the programming enabling signal of the FLASH to be changed from an enabling state to an invalid state within a first preset time t1 and control the direct-current power supply signal to continuously supply power for a second preset time t2; the starting time of the first preset time t1 and the second preset time t2 are the time when the real-time voltage value reaches the preset voltage threshold, and the first preset time t1 is smaller than the second preset time t2.
In particular, the above method can be understood in connection with fig. 1 and 2. The real-time voltage value provided by the FLASH power supply 3 is recorded as VDD, the LOW-voltage state signal is recorded as LOW-DET, the WEB signal is one of the state control signals for controlling the FLASH, the PROG is a programming enabling signal, and the direct current power supply signal capable of directly supplying power to the FLASH is recorded as VDD-FLASH.
When the real-time voltage value VDD supplied from the FLASH power supply 3 is changed from a high level to a LOW level, the LOW-voltage state signal LOW-DET is changed from a LOW level to a high level, that is, the LOW-voltage state signal LOW-DET is changed from an inactive state to an enabled state, and information of power supply voltage abnormality (power-off or voltage lower than a preset voltage threshold) is transferred to the power-down protection control circuit 2.
After receiving the LOW-DET signal, the power-down protection control circuit 2 sequentially adjusts the level states of the respective state control signals so as to change from the enabled state to the disabled state. The control state signal refers to a signal, such as an erase signal and a program enable signal, sent to the FLASH to perform state adjustment on the signal. As an example, for a WEB signal that is active LOW, the power-down protection control circuit 2 adjusts the WEB signal from a LOW level to a high level state after receiving the LOW-DET signal. For the program enable signal PROG active high, the power-down protection control circuit 2 changes the PROG signal from high to LOW for a first preset time t1 after receiving the LOW-DET signal. As an example, the first preset time t1 is greater than 50 microseconds, which may be, for example, 50 microseconds, 55 microseconds, 60 microseconds, or 70 microseconds. Optionally, after receiving the LOW-DET signal, the power-down protection control circuit 2 may clear the data bus and the address bus of the FLASH, in addition to adjusting the level state of the state control signal.
The real-time voltage VDD provided by the FLASH power supply 3 is processed by the power management circuit 1 to obtain a direct current power supply signal VDD-FLASH which can directly supply power to the FLASH. VDD-FLASH does not go low immediately after VDD goes low, but is continuously supplied with power for at least a second preset time t2. As an example, the second preset time t2 may be 100 microseconds, 110 microseconds, or 120 microseconds.
The starting time of the first preset time t1 and the starting time of the second preset time t2 are the same, and are the time when the real-time voltage value decreases to the preset voltage threshold, for example, the time when VDD changes from high level to low level. And, the length of the first preset time t1 is set to be smaller than the length of the second preset time t 2.
The technical features of the above-described embodiments may be arbitrarily combined, and all possible combinations of the technical features in the above-described embodiments are not described for brevity of description, however, as long as there is no contradiction between the combinations of the technical features, they should be considered as the scope of the description.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that it will be apparent to those skilled in the art that several variations and modifications can be made without departing from the spirit of the invention, which are all within the scope of the invention. Accordingly, the scope of protection of the present invention is to be determined by the appended claims.
Claims (10)
1. The FLASH abnormal power-down protection circuit is characterized by comprising:
The power management circuit is electrically connected with the FLASH power supply and the FLASH and is used for providing a direct current power supply signal for the FLASH, detecting a real-time voltage value of the FLASH power supply and generating a low-voltage state signal under the condition that the real-time voltage value is reduced to a preset voltage threshold value;
The power-down protection control circuit is electrically connected with the power management circuit and the FLASH, and is used for providing a state control signal for the FLASH, changing the level state of the state control signal according to the received low-voltage state signal so as to control the programming enabling signal of the FLASH to be changed from an enabling state to an invalid state within a first preset time and control the direct-current power supply signal to continuously supply power for a second preset time;
The starting time of the first preset time and the starting time of the second preset time are the time when the real-time voltage value reaches the preset voltage threshold value, and the first preset time is smaller than the second preset time; wherein the power management circuit comprises:
the rectification boosting unit is electrically connected with the FLASH power supply and used for generating an initial direct current power supply signal according to the real-time voltage value of the FLASH power supply;
The low-dropout linear voltage stabilizing circuit is electrically connected with the rectifying and boosting unit and the power-down protection control circuit and is used for generating the direct-current power supply signal according to the received initial direct-current power supply signal;
The low-voltage detection circuit is electrically connected with the rectifying and boosting unit and the power-down protection control circuit and is used for detecting the initial direct-current power supply signal so as to generate the low-voltage state signal in a third preset time from the moment that the real-time voltage value reaches the preset voltage threshold value; the third preset time is smaller than the first preset time.
2. The FLASH exception power down protection circuit of claim 1, wherein the power management circuit further comprises:
And the power-on reset circuit is electrically connected with the rectifying and boosting unit and the power-off protection control circuit and is used for generating a power-on reset signal according to the initial direct current power supply signal so as to control the FLASH power-on reset.
3. The FLASH abnormal power-down protection circuit according to any one of claims 1-2, wherein the FLASH power-down controller is configured to provide a state control signal to the FLASH, and change an operating state of a state machine thereof according to the received low-voltage state signal, so as to change a level state of the state control signal.
4. The FLASH abnormal power down protection circuit of claim 3, wherein the power down protection control circuit further comprises:
The FLASH power-off controller is electrically connected with the FLASH through the output isolation device; and/or
And the FLASH is electrically connected with the FLASH power-off controller through the input isolation device.
5. The FLASH abnormal power down protection circuit of claim 4, wherein the FLASH power down controller is configured to:
and controlling the state control signal to change from a first level state to a second level state according to the received low-voltage state signal.
6. The FLASH abnormal power down protection circuit of claim 5, wherein the first level state is a low level and the second level state is a high level.
7. The FLASH abnormal power down protection circuit of claim 1, wherein the rectifying and boosting unit comprises a standby energy storage element.
8. The FLASH abnormal power-down protection circuit according to claim 7, wherein the rectifying and boosting unit further comprises a diode, wherein an anode of the diode is connected with the FLASH power supply, a cathode of the diode is connected with the low dropout linear voltage stabilizing circuit, and one end of the standby energy storage element is connected to a path between the cathode of the diode and the low dropout linear voltage stabilizing circuit.
9. The FLASH abnormal power-down protection device is characterized by comprising:
FLASH; and
The FLASH abnormal power-down protection circuit of any one of claims 1-8, electrically connected to the FLASH, for performing abnormal power-down protection on the FLASH.
10. A method for protecting a FLASH abnormal power failure, which is characterized by being applied to a FLASH abnormal power failure protecting device as claimed in claim 9, and comprising the following steps:
Providing a direct current power supply signal for the FLASH based on a real-time voltage value provided by the FLASH power supply, detecting the real-time voltage value of the FLASH power supply, and generating a low-voltage state signal under the condition that the real-time voltage value is reduced to a preset voltage threshold value;
Changing the level state of a state control signal provided for the FLASH according to the received low-voltage state signal so as to control the programming enabling signal of the FLASH to be changed from an enabling state to an invalid state within a first preset time and control the direct-current power supply signal to continuously supply power for a second preset time;
The real-time voltage provided by the FLASH power supply is processed by the power supply management circuit to obtain the direct current power supply signal for supplying power to the FLASH; the starting time of the first preset time and the starting time of the second preset time are the time when the real-time voltage value reaches the preset voltage threshold value, and the first preset time is smaller than the second preset time.
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| CN202110769200.3A CN113391690B (en) | 2021-07-07 | 2021-07-07 | FLASH abnormal power-down protection circuit, device and method |
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| CN202110769200.3A CN113391690B (en) | 2021-07-07 | 2021-07-07 | FLASH abnormal power-down protection circuit, device and method |
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