CN216751184U

CN216751184U - Storage device and power management unit thereof

Info

Publication number: CN216751184U
Application number: CN202123324977.3U
Authority: CN
Inventors: 徐志剑; 刘志远; 谢欣
Original assignee: Beijing Memblaze Technology Co Ltd
Current assignee: Beijing Memblaze Technology Co Ltd
Priority date: 2021-12-27
Filing date: 2021-12-27
Publication date: 2022-06-14
Anticipated expiration: 2031-12-27
Also published as: CN114977453A

Abstract

The application relates to a storage technology, especially relates to storage device and power management unit thereof, including: the charging and discharging management unit comprises a booster circuit, a charging and discharging control circuit, a charging and discharging management unit and an energy storage capacitor; the booster circuit is connected to the first end of the charge-discharge control circuit, the second end of the charge-discharge control circuit is connected to the first pole of the energy storage capacitor, and the second pole of the energy storage capacitor is grounded; the charge and discharge management unit is connected to the control end of the booster circuit and is also connected to the first end of the charge and discharge control circuit and the second end of the charge and discharge control circuit; the booster circuit is used for being connected to an interface of the storage device, and the charge and discharge management unit is used for being connected to a control component of the storage device. The reliability of the storage device can be improved.

Description

Storage device and power management unit thereof

Technical Field

The present disclosure relates to storage technologies, and in particular, to an abnormality detection and protection circuit for an energy storage capacitor of a storage device and a power management unit thereof.

Background

FIG. 1 illustrates a block diagram of a prior art storage device. The storage device 102 is coupled to a host for providing storage capabilities to the host. The host and the storage device 102 may be coupled by various methods, including but not limited to, connecting the host and the solid state storage device 102 by, for example, SATA (Serial Advanced Technology Attachment), SCSI (Small Computer System Interface), SAS (Serial Attached SCSI), IDE (Integrated Drive Electronics), USB (Universal Serial Bus), PCIE (Peripheral Component Interconnect Express, PCIE, high speed Peripheral Component Interconnect), NVMe (NVM Express, high speed nonvolatile storage), ethernet, fibre channel, wireless communication network, etc. The host may be an information processing device, such as a personal computer, tablet, server, portable computer, network switch, router, cellular telephone, personal digital assistant, etc., capable of communicating with the storage device in the manner described above. The Memory device 102 includes an interface 103, a control section 104, one or more NVM chips 105, and a DRAM (Dynamic Random Access Memory) 110.

NAND flash Memory, phase change Memory, FeRAM (Ferroelectric RAM), MRAM (magnetoresistive Memory), RRAM (Resistive Random Access Memory), XPoint Memory, and the like are common NVM.

The interface 103 may be adapted to exchange data with a host by means such as SATA, IDE, USB, PCIE, NVMe (NVMExpress), SAS, ethernet, fibre channel, etc.

The control unit 104 is used to control data transfer between the interface 103, the NVM chip 105, and the DRAM 110, and also used for memory management, host logical address to flash physical address mapping, erase leveling, bad block management, and the like. The control component 104 can be implemented in various manners of software, hardware, firmware, or a combination thereof, for example, the control component 104 can be in the form of an FPGA (Field-programmable gate array), an ASIC (Application-Specific Integrated Circuit), or a combination thereof. The control component 104 may also include a processor or controller in which software is executed to manipulate the hardware of the control component 104 to process IO (Input/Output) commands. The control component 104 may also be coupled to the DRAM 110 and may access data of the DRAM 110. FTL tables and/or cached IO command data may be stored in the DRAM.

Control section 104 includes a flash interface controller (otherwise referred to as a media interface controller, flash channel controller) that is coupled to NVM chip 105 and issues commands to NVM chip 105 in a manner that conforms to the interface protocol of NVM chip 105 to operate NVM chip 105 and receive the command execution results output from NVM chip 105. Known NVM chip interface protocols include "Toggle", "ONFI", etc.

The storage device 102 uses the interface 103 to obtain power from the host during operation. In order to avoid the data which is not written into the NVM in the storage device from being lost due to the unexpected shutdown or power failure of the host, the storage device further comprises a standby power supply which is used for providing emergency power for all parts of the storage device when the unexpected power failure occurs. The power management unit 120 manages power supply of each component including the backup power. For example, the power management unit 120 obtains power from the interface 103 and distributes the power to the various components of the storage device 102. And the power management unit 120 also controls the sequence of powering up and powering down the various components of the memory device 102, monitors the power consumption of the memory device 102, and the like. In the example where the backup power source is the energy storage capacitor 125, the power management unit 120 also boosts the voltage provided to the backup power source to boost the energy of the electrical energy stored in the backup power source.

SUMMERY OF THE UTILITY MODEL

The backup power supply of the storage device is a less reliable component than the other components of the electronic device. It may malfunction because it requires a long-term storage of more energy during its operation, operating at a higher voltage. For example, when a capacitor is used as a backup power supply, the voltage across the charged capacitor may reach tens of volts during use, which is much higher than the operating voltage of other components of the storage device. In a capacitor which is exposed to a high voltage for a long time, the capacitor plates may be broken down to cause a short circuit. The short-circuited capacitor can generate potential safety hazards, and the energy storage capacity of the standby power supply is also reduced. The short circuit of the energy storage capacitor may not be apparent but only manifest as heating, leakage, and/or a different degree of reduction in voltage across the capacitor. Due to the reduction of the energy storage capacity, the short circuit of the energy storage capacitor also causes the working time of the storage device after power failure to be possibly shorter than the design time, and therefore the reliability of the storage device is reduced.

Thus, there is a need for an anomaly detection circuit and protection mechanism for the storage capacitor to enhance the reliability of the memory device. In addition, the short-circuit fault of the energy storage capacitor may occur at any time after the storage device leaves the factory, and emergency protection needs to be provided for the electronic device after the storage capacitor is suddenly short-circuited, so that the storage device is prevented from being damaged, and the storage device has time to process the short-circuit event of the energy storage circuit, so that the risk of data loss is reduced.

According to a first aspect of the present application, there is provided a power management unit of a first storage device according to the first aspect of the present application, comprising: the charging and discharging management unit comprises a booster circuit, a charging and discharging control circuit, a charging and discharging management unit and an energy storage capacitor; the booster circuit is connected to the first end of the charge-discharge control circuit, the second end of the charge-discharge control circuit is connected to the first pole of the energy storage capacitor, and the second pole of the energy storage capacitor is grounded; the charge and discharge management unit is connected to the control end of the booster circuit and is also connected to the first end of the charge and discharge control circuit and the second end of the charge and discharge control circuit; the booster circuit is used for being connected to an interface of the storage device, and the charge and discharge management unit is used for being connected to a control component of the storage device.

The power management unit of the first storage device according to the first aspect of the present application, the power management unit of the second storage device according to the first aspect of the present application is provided, and the boost circuit is configured to be connected to a power input pin of an interface of the storage device.

According to the power management unit of the first storage device of the first aspect of the present application, a power management unit of the third storage device of the first aspect of the present application is provided, and the charge and discharge management unit is connected with an indicator lamp located outside the storage device.

According to one of the power management units of the first to third memory devices of the first aspect of the present application, there is provided the power management unit of the fourth memory device of the first aspect of the present application, wherein the current limiting resistor of the charge and discharge control circuit is connected between the first terminal and the second terminal.

According to the power management unit of the fourth memory device of the first aspect of the present application, there is provided the power management unit of the fifth memory device of the first aspect of the present application, wherein the resistance value of the current limiting resistor is 100 ohms.

According to one of the power management units of the first to fourth memory devices of the first aspect of the present application, there is provided the power management unit of the sixth memory device of the first aspect of the present application, wherein a cathode of the diode/MOSFET switch of the charge and discharge control unit is connected to the first terminal, an anode of the diode/MOSFET switch of the charge and discharge control circuit is connected to the second terminal, and the diode/MOSFET switch is connected in parallel with the current limiting resistor; the charge and discharge management unit is also connected to the control terminal of the diode/MOSFET switch.

According to one of the power management units of the first to fourth storage devices of the first aspect of the present application, there is provided the power management unit of the seventh storage device of the first aspect of the present application, and the charge and discharge management unit is connected to the control terminal of the switching tube in the voltage boost circuit.

According to one of the power management units of the first to fourth storage devices of the first aspect of the present application, there is provided the power management unit of the eighth storage device of the first aspect of the present application, the energy storage capacitor has a plurality of energy storage capacitors, and the plurality of energy storage capacitors are connected in parallel between the second end of the charge and discharge control circuit and the ground.

According to a second aspect of the present application, there is provided a first storage device according to the second aspect of the present application, comprising: an interface of a storage device, a control unit and a power management unit of any one of the above storage devices; the boosting circuit of the power management unit of the storage device is connected to the interface of the storage device; the charging and discharging management unit of the power management unit of the storage device is connected to the control component of the storage device.

According to a second aspect of the present application, there is provided a second storage device according to the first aspect of the present application, further comprising: the NVM and the DRAM are connected, and the control unit is connected to the NVM and the DRAM.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the description below are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to these drawings.

FIG. 1 illustrates a block diagram of a prior art storage device;

FIG. 2 illustrates a schematic diagram of an anomaly detection mechanism for an energy storage capacitor according to an embodiment of the present application;

FIG. 3A illustrates a block diagram of a power management unit according to an embodiment of the present application;

FIG. 3B illustrates a block diagram of an energy storage capacitor according to an embodiment of the present application;

fig. 4 shows a flowchart of a charging and discharging management process of an energy storage capacitor according to an embodiment of the present application.

Detailed Description

The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.

Fig. 2 shows a schematic diagram of an anomaly detection mechanism of an energy storage capacitor according to an embodiment of the present application.

In the embodiment of fig. 2, the energy storage capacitor 228 serves as a backup power source. The power management unit of the storage device 200 includes a voltage boosting circuit 222, a charge and discharge control circuit 224, a charge and discharge management unit 226, and an energy storage capacitor 228. The power input pin of the interface 203 of the memory device 200 is connected to the boost circuit 222. The boost circuit 222 boosts the voltage of the power supplied by the host to the storage device 200 and supplies the boosted voltage to the energy storage capacitor 228. The amount of power stored in the storage capacitor 228 is proportional to the square of the voltage across the storage capacitor 228, thereby boosting the amount of power stored in the storage capacitor 228 by boosting the voltage. The boost circuit 222 is connected to the energy storage capacitor 228 through the charge and discharge control circuit 224. The charge and discharge management unit 226 is connected to the charge and discharge control circuit 224, and manages the charge and discharge processes of the energy storage capacitor 228 by controlling the working state of the charge and discharge control circuit 224, and provides protection for the energy storage capacitor 228.

When the power obtained from the interface 203 of the storage device 200 is normal, the obtained power is supplied to each component (for example, the control component 204, the NVM205, and the DRAM210) of the storage device 200, and the energy storage capacitor 228 is charged or maintained in a charged state by the voltage boosting circuit 222 and the charge/discharge control circuit 224.

In response to the storage device 200 receiving a power down or shutdown command, the control part 204 notifies the charge and discharge management unit 226 of the power down event. The charging and discharging management unit 226 discharges the energy storage capacitor 228 through the charging and discharging control circuit 224 to drain the energy in the energy storage capacitor 228, thereby avoiding negative or unexpected influence on the storage device caused by the remaining energy of the energy storage capacitor 228. For example, if the energy storage capacitor 228 has a large amount of remaining energy, the energy may cause the control component 204 to restart after being turned off, but due to the insufficient amount of energy in the energy storage capacitor 228, the control component 204 is turned off again after being turned off again, thereby causing data of the storage device 200 to be damaged or components to be damaged.

When the storage device 200 is abnormally powered down (no power-down or shutdown command is received, but normal power cannot be obtained from the interface), the charging and discharging management unit 226 discharges the energy storage capacitor 228 through the charging and discharging control circuit 224, and the electric energy released by the energy storage capacitor 228 is redistributed to each component of the storage device 200 by the charging and discharging management unit 226 to maintain the short-time operation of the storage device 200. The charge and discharge management unit 226 also notifies the control section 204 of the occurrence of an abnormal power failure, and in response, the control section 204 performs corresponding processing to emergency-shut down the storage apparatus 200.

Since the energy storage capacitor 228 may fail at any time, according to the embodiment of the present application, the failure of the energy storage capacitor 228 is detected through one or more mechanisms, and damage to components of the storage device 200 caused by the failure of the energy storage capacitor 228 is avoided, and failure of the emergency shutdown process of the storage device 200 after abnormal power down due to insufficient power of the energy storage capacitor 228 is also avoided.

The energy storage capacitor 228 may have failed before the memory device 200 is powered up. According to an embodiment of the present application, in response to the storage device 200 being powered on, the charging and discharging management unit 226 detects whether the storage capacitor 228 is abnormal through the charging and discharging control circuit 224 before charging the storage capacitor 228. At this time, the charge and discharge management unit 226 does not turn on the boost circuit 222 (or ensures that the boost circuit 222 is turned off) (indicated by (1) in fig. 2), and a charging path from the power input pin of the interface 203 of the storage device 200 to the energy storage capacitor 228 is not yet established. At this time, the power input pin of the interface of the storage device 200 has a power supply voltage (for example, 5V or 12V), and although the boost circuit 222 is not turned on, the charge/discharge control circuit 224 is connected to the electric path of the energy storage capacitor 228, and an induced voltage is generated due to the operating voltage of the power input pin, and a weak charging current is formed in the electric path due to the charging action of the induced voltage on the energy storage capacitor 228. In the absence of a short circuit fault on the storage capacitor 228, the charging current will diminish or disappear after a period of time has elapsed. In the case of a short-circuit fault in the energy storage capacitor 228, the charging current will continue to exist. Thus, the charging and discharging management unit 226 does not turn on the voltage boosting circuit 222 after the storage device 200 is powered on, and detects the current flowing to the energy storage capacitor 228 or the voltage generated by the current flowing to the energy storage capacitor 228 by the charging and discharging control circuit 224 after a specified time (e.g., several milliseconds) of power on, so as to identify whether there is a short circuit or other fault in the energy storage capacitor 228. During this time, the charge and discharge control circuit 224 may indicate a fault in the storage capacitor 228, for example, when the current flowing to the storage capacitor 228 exceeds 5 mA. If the energy storage capacitor 228 is identified as faulty, the charging and discharging management unit 226 does not turn on the boost circuit 222 any more to avoid charging the faulty energy storage capacitor 228. Alternatively, the charging and discharging management unit 226 may supply power to the control component 204 of the storage device and other components to enable the control component 204 to start up and inform the control component 204 about the failure of the energy storage capacitor 228. Still alternatively, the charging and discharging management unit 226, after recognizing the energy storage capacitor 228 as a fault, neither turns on the voltage boost circuit 222 nor supplies power to the control component 204 (or NVM205, DRAM210) and so on, and indicates the occurrence of the fault to the user by means of an indicator light and so on.

After the storage device 200 is powered on, if it is recognized that the energy storage capacitor 228 is normal (no abnormal state exists), the charge/discharge management unit 226 turns on the voltage boost circuit 222 (indicated by (2) in fig. 2), and charges the energy storage capacitor 228 through the charge/discharge control circuit 224 (indicated by (3) in fig. 2). During the charging process of the energy storage capacitor 228, the charging and discharging management unit 226 cannot detect whether the energy storage capacitor 228 is short-circuited or not temporarily due to the existence of a large charging current. Alternatively or additionally, to avoid the charging of the energy storage capacitor 228 being turned on at the moment, and the large charging current having an adverse effect on the power supply system of the host, the charging and discharging control circuit 224 further includes a current limiting device on the charging path to the energy storage capacitor 228, so as to avoid the generation of an excessive current during the charging process. The current limiting device is, for example, a resistor (also referred to as a current limiting resistor). The presence of the current limiting resistor allows the charge and discharge management unit 226 to identify the current supplied to the energy storage capacitor 228 by measuring the voltage across the resistor. Alternatively or additionally, during the charging of the energy storage capacitor 228, the charging and discharging management unit 226 still does not supply power to the control component 204, and power is supplied to the control component 204 only after the charging of the energy storage capacitor 228 is completed, so that the control component 204 operates in a fully charged state of the energy storage capacitor 228 after being powered on, so as to ensure the reliability of the storage device 200. Still alternatively, in order to shorten the time from power-up to the time when the storage device 200 can respond to the host IO command, the charge and discharge management unit 226 supplies power to the control component 204 in advance even though the charging of the energy storage capacitor 228 is not completed.

After the energy storage capacitor 228 is charged, the current supplied to the energy storage capacitor 228 by the charge/discharge control circuit 224 is removed, or a small current is maintained to maintain the charge of the energy storage capacitor 228. During normal operation of the memory device 200, the storage capacitor 228 is maintained in a fully charged state. The charge/discharge management unit 226 discharges the energy storage capacitor 228 through the charge/discharge control circuit 224. For example, the energy storage capacitor 228 is discharged in order to measure the charge of the energy storage capacitor 228 (the charge of the energy storage capacitor 228 is identified by the discharge current and the voltage change of the energy storage capacitor 228). As another example, during a time period when the storage device 200 is not powered down or does not need to provide high-reliability data storage capacity, the charging and discharging management circuit 224 discharges the energy storage capacitor 228 to reduce the voltage of the energy storage capacitor 228, thereby reducing the time for the energy storage capacitor 228 to bear a high voltage and further prolonging the life of the energy storage capacitor 228.

According to the embodiment of the present application, after the energy storage capacitor 228 is charged, the charging and discharging management unit 226 further monitors the current provided to the energy storage capacitor 228 by the charging and discharging control circuit 224, and checks whether the energy storage capacitor 228 is leaky or short-circuited by the current. During the operation of the energy storage capacitor 228, faults such as short circuit and leakage may occur, and at this time, the current supplied to the energy storage capacitor 228 by the charging and discharging control circuit 224 is increased (larger than a normal value) to detect the fault of the energy storage capacitor 2278. The charge and discharge management unit 226 recognizes whether the current is excessive by, for example, the voltage across the current limiting resistor of the charge and discharge control circuit 224. As an example, the charge and discharge management unit 226 initiates detection of the current provided to the energy storage capacitor 228 by the charge and discharge control circuit 224 periodically, or in response to an instruction from the control component 204. As yet another example, the charge and discharge management unit 226 also monitors the voltage between the two plates of the energy storage capacitor 228, and in the event of a sudden drop in voltage or a voltage less than a specified threshold, initiates detection of the current provided to the energy storage capacitor 228 by the charge and discharge control circuit 224. During this time, the charge and discharge control circuit 224 flows a current exceeding, for example, 20mA to the storage capacitor 228 as an indication of a failure of the storage capacitor 228, for example.

In response to detecting the energy storage capacitor 228 failure, to avoid damage to the storage device 200 due to abnormal discharge of the energy storage capacitor 228, the charge and discharge management unit 226 also turns on the charge and discharge control circuit 224 (indicated by (4) in fig. 2) to actively discharge the energy storage capacitor 228. For example, the path for the energy storage capacitor 228 to supply power to each component of the storage device 200 during abnormal power failure is opened, so that the electric quantity of the energy storage capacitor 228 flows to the charge and discharge management unit 226 (indicated by (6) in fig. 2) through the charge and discharge control circuit 224 (indicated by (5) in fig. 2), and further flows to the control component 204 (indicated by (7) in fig. 2), so as to actively discharge the electric quantity of the energy storage capacitor 228. Optionally, the charge and discharge management unit 226 further keeps the boost circuit 222 off during the draining of the charge of the energy storage capacitor 228.

Further, since the occurrence of the fault of the energy storage capacitor 228 is random, the charging and discharging management unit 226 may detect the fault of the energy storage capacitor 228 later than the occurrence of the fault of the energy storage capacitor 228. When the charge and discharge management unit 226 does not detect the fault after the storage capacitor 228 fault occurs, the storage capacitor 228 fault puts the storage device 200 in danger, for example, an excessive current discharge caused by a short circuit may cause damage to the components of the current path. Because the charge and discharge control circuit 224 is connected in series with the energy storage capacitor 228, the short-circuit current discharged from the energy storage capacitor 228 may cause the same current to appear on the charge and discharge control circuit 224, and the current limiting resistor is arranged on the charge and discharge control circuit 224 to prevent the short-circuit current discharged from the energy storage capacitor 228 from being too large. Further, the current limiting resistor for limiting the short-circuit current discharged by the energy storage capacitor 228 may be the same resistor or the same group of resistors as the current limiting resistor with excessive current during the power-up of the storage device 200 or the charging process of the energy storage capacitor 228. By way of example, the resistance of the resistor is 100 ohms. Since the resistor is located on the charging path and the discharging path of the energy storage capacitor 228, the resistance of the resistor should not be too large to avoid energy waste caused by too much heat generated during charging and discharging, and should not be too small to play a role in limiting current.

Alternatively or additionally, bleeding current through the storage capacitor 228 through the resistor may generate heat that is detrimental to the electronic components of the memory device 200. After the charging and discharging management unit 226 detects the failure of the energy storage capacitor 228, the charging and discharging control circuit 224 is controlled to provide a low resistance path for discharging the energy of the energy storage capacitor 228, for example, a discharge path provided by a controlled diode or a MOSFET switch.

Still optionally, the charging and discharging management unit 226 further identifies the completion of the discharging of the energy storage capacitor 228. For example, the bleed-off completion is identified by detecting the voltage or the bleed-off current of the energy storage capacitor 228. The control component 204 is then notified that the storage capacitor 228 is drained. Thus, the storage device 200 may be shut down without further safety concerns.

FIG. 3A illustrates a block diagram of a power management unit according to an embodiment of the application.

The power management unit includes a boost circuit 222, a charge/discharge control circuit 224, a charge/discharge management unit 226, and an energy storage capacitor 228. The power input pin of the memory device 200 is connected to the boost circuit 222. The voltage boost circuit 222 boosts the voltage provided by the power input pin and outputs the boosted voltage to the first end 320 of the charge and discharge control circuit 224, and the second end 340 of the charge and discharge control circuit 224 is connected to the energy storage capacitor 228. The two plates of the energy storage capacitor 228 are connected between the second end 340 of the charge control circuit 224 and Ground (GND).

The charge/discharge management unit 226 is connected to the control terminal 310 of the boost circuit 222 to control the boost circuit 222 to be turned on or off, for example: the charge and discharge management unit 226 is connected to a control terminal (transistor/MOS transistor) of a switching transistor in the boost circuit 222 to control the boost circuit 222 to be turned on or off by applying or cancelling a predetermined voltage to the control terminal of the switching transistor. When the voltage boosting circuit 222 is turned on, the voltage of the power input pin is boosted and supplied to the charge/discharge control circuit 224. When the booster circuit 222 is turned off, the booster circuit 222 cuts off the path from the power input pin to the charge/discharge control circuit 224.

The charge and discharge management unit 226 is also connected to a control terminal of the diode (D1) of the charge and discharge control circuit 224, and can control the on/off of the diode (D1) by applying or canceling a predetermined voltage to the control terminal of the diode (D1). Diode D1 operates on the diode principle when turned on, connecting the terminals of diode D1, and disconnecting the terminals of diode D1 when diode D1 is disconnected.

The charge and discharge management unit 226 also provides power to components of the storage device 200, such as the control component 204, the DRAM210, the NVM205, and the like. The charge and discharge management unit 226 is also connected to the control section 204 to provide an interrupt signal to the control section 204. In response to the interrupt signal, the control component 204 processes the interrupt and identifies an event (e.g., a failure of the energy storage capacitor 228) that the charge and discharge management unit 226 indicates to the control component 204.

The charge and discharge management unit 226 is further connected to the first terminal 320 and the second terminal 340 of the charge and discharge control circuit 224 respectively to detect the current flowing through the resistor R1 and/or the voltage across the resistor R1. The current flowing through resistor R1 is generally representative of the current flowing through the energy storage capacitor 228.

The charge and discharge control circuit 224 includes a resistor R1 and a diode D1 connected in parallel between the first terminal 320 and the second terminal 340, wherein an anode of the diode D1 is connected to the second terminal 340 and a cathode thereof is connected to the first terminal 320.

After the memory device 200 is powered up and during the period when the boost circuit 222 charges the energy storage capacitor 228, the charging current flows from the first terminal 320 to the second terminal 340, the voltage at the first terminal 320 is higher than the voltage at the second terminal 340, the diode D1 is turned off, and the charging current is provided to the energy storage capacitor 228 from the resistor R1. The resistor R1 also acts as a current limiting resistor during charging of the energy storage capacitor 228 to prevent excessive current from forming in the charging path during charging and during charging. By way of example, the resistor R1 has a value of 100 ohms. After the energy storage capacitor 228 is fully charged, while the energy storage capacitor 228 is in the energy holding state, the charging current flowing through the resistor R1 is 0 or only weak current to provide the leakage of the energy storage capacitor 228, and at this time, the voltages at the first end 320 and the second end 340 are substantially equal, and the diode D1 is still turned off. Optionally, after the storage device 200 is powered on, the energy storage capacitor 228 is charged, and during the time period that the energy storage capacitor 228 keeps the charge, the charge and discharge management unit 226 further turns off the diode D1 to further prevent the current of the energy storage capacitor 228 from being discharged from the diode D1.

When the energy storage capacitor 228 supplies power to, for example, the control component 204, the power supply to the power input pin is lost and the voltage at the first end 320 is lower than the voltage at the second end 340. The charging and discharging management unit 226 controls the diode D1 to turn on, the voltage of the second end 340 is higher than that of the first end 320, so that the diode D1 is turned on, and the power released by the energy storage capacitor 228 is provided to the charging management unit 226 from the diode D1 and further provided to the control unit 204 to provide power for the storage device 200.

Alternatively, the charge and discharge management unit 226 does not respond to turn on the charge and discharge control circuit 224 in a short time after the occurrence of the abnormal power failure. As the voltage at the first end 320 drops, less than the voltage at the second end 340, the power at the energy storage capacitor 228 forms a current from the second end 340 to the first end 320, which is drained via the resistor R1. The resistor R1 of the charge and discharge control circuit 224 thus provides a path for the draining of the energy storage capacitor 228.

Alternatively or additionally, if the energy storage circuit fails, for example, a short circuit, a current from the energy storage capacitor 228 to Ground (GND) is formed, which in turn also causes a current from the resistor R1 to the energy storage capacitor 228. The charging and discharging management unit 226 detects the current magnitude and the current direction of the resistor R1 by measuring the voltage across the first terminal 320 and the second terminal 340, so as to identify whether the energy storage capacitor 228 has a fault. If the energy storage capacitor 228 is short-circuited in the fully charged state, the current flows from the first end 320 to the second end 340, and then is discharged to the ground through the energy storage current, and at this time, the resistor R1 also serves as a current limiting resistor to avoid an excessive short-circuit current caused by the high voltage of the energy storage capacitor 228. After the energy storage capacitor 228 fails, the discharge current of the energy storage capacitor 228 flows through the resistor R1 (from the first end 320 to the second end 340) before the charge and discharge management unit 226 identifies the failure and responds. After the charging and discharging management unit 226 turns on the diode D1 in response to the fault being identified, the leakage current of the energy storage capacitor 228 flows from the diode D1 to the charging and discharging management unit 226, and the charging and discharging management unit 226 manages the current leakage of the energy storage capacitor 228. After the energy storage capacitor 228 fails, the charge and discharge management unit 226 can identify the failure within about 100ms and turn on the diode D1. Within this 100ms, the bleed current passes through resistor R1, and due to the shorter time, the amount of heat generated is lower and does not cause damage to the components of the memory device 200. As an example, the charge and discharge management unit 226 periodically measures the voltage across the resistor R1 to identify whether the energy storage capacitor 228 is faulty, and the detection period is, for example, 100 ms. Still by way of example, the difference between the voltage at the second terminal 340 and the reference voltage is used to generate an interrupt signal to the charge/discharge management unit 226, and the charge/discharge management unit 226 can process the interrupt within 100ms and identify the fault of the energy storage capacitor 228.

Fig. 3B illustrates a block diagram of an energy storage capacitor according to an embodiment of the present application.

Alternatively or additionally, the present application has a plurality of energy storage capacitors 228, and the plurality of energy storage capacitors 228 are connected in parallel between the second end 340 of the charge and discharge control circuit 224 and the ground.

The storage device is loaded into the host or the host is powered on and begins operating, and the host begins supplying power to the storage device and, in response, the storage device powers up (410). In response to power-up, the charge and discharge management unit 226 (see also fig. 3) of the storage device starts operating with power supplied by the host. The charge and discharge management unit 226 ensures that the charging path (e.g., the boost circuit 222 and the charge and discharge control circuit 224 in fig. 2 and 3) to the energy storage capacitor 228 is closed, and detects whether the state of the energy storage capacitor 228 in the uncharged state is normal or abnormal (420). For example, the charging and discharging management unit 226 measures the current on the charging path or the voltage across the current limiting resistor R1 on the charging path to identify whether there is a short circuit or breakdown of the energy storage capacitor 228 when the charging path to the energy storage capacitor 228 is closed. For example, if the voltage across the current limiting resistor R1 is smaller than a predetermined threshold, the state of the energy storage capacitor 228 is identified as normal, and otherwise, the state of the energy storage capacitor 228 is identified as abnormal.

In case the state of the energy storage capacitor 228 is abnormal, the charging and discharging management unit 226 does not charge the energy storage capacitor 228 any more to protect the storage device. If the state of the energy storage capacitor 228 is normal, the charge/discharge management unit 226 turns on the boost circuit 222 to charge the energy storage capacitor 228 (430) until the charging of the energy storage capacitor 228 is completed (440). Thereafter, the charge/discharge management unit 226 turns off the booster circuit 222 and keeps the storage capacitor 228 in a fully charged state. Optionally, the charge/discharge management unit 226 turns on/off the boost circuit 222 occasionally to supplement the amount of power leaked from the energy storage capacitor 228. The charge and discharge management unit 226 also powers up other components of the storage device to operate the storage device.

During operation of the storage device, the charge and discharge management unit 226 checks the state of the energy storage capacitor 228 from time to time (450) to account for possible sudden failures (such as breakdown or short circuits) of the energy storage capacitor 228. For example, the charge and discharge management unit 226 measures the current on the charging path, or the voltage across the current limiting resistor R1 on the charging path, to identify whether there is a short circuit or breakdown of the energy storage capacitor 228. After the energy storage capacitor 228 is shorted or leaked, a leakage current flows through the charging path. Therefore, if the voltage across the current limiting resistor R1 is smaller than a specified threshold, it is recognized that the state of the energy storage capacitor 228 is normal, and otherwise, it is recognized that the state of the energy storage capacitor 228 is abnormal.

If the charging and discharging management unit 226 identifies that the fully charged energy storage capacitor 228 is normal (460), the procedure returns to step 450 to enter the next checking of the status of the energy storage capacitor 228. If the energy storage capacitor 228 is identified as abnormal (460), the charging and discharging management unit 226 turns off the boost circuit 222 and opens the energy discharge path of the energy storage capacitor 228, and alerts the control component 204 of the storage device (470). For example, the charging and discharging management unit 226 opens a power supply path from the energy storage capacitor 228 to itself, and provides the amount of power of the energy storage capacitor 228 to various components of the storage device. The charging and discharging management unit 226 also identifies the completion of the discharging of the energy storage capacitor 228 to confirm that the energy storage capacitor 228 and the storage device are safe (not causing a fault or danger due to a short circuit of the energy storage capacitor 228).

Optionally, the charging and discharging management unit 226 also discharges the energy storage capacitor 228 in response to the storage device being turned off or powered down or abnormally powered down. For example, the charging and discharging management unit 226 opens a power supply path from the energy storage capacitor 228 to itself, and supplies the amount of power of the energy storage capacitor 228 to each component of the storage device.

While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all alterations and modifications as fall within the scope of the application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims

1. A power management unit for a storage device, comprising: the charging and discharging management unit comprises a booster circuit, a charging and discharging control circuit, a charging and discharging management unit and an energy storage capacitor;

the booster circuit is connected to the first end of the charge-discharge control circuit, the second end of the charge-discharge control circuit is connected to the first pole of the energy storage capacitor, and the second pole of the energy storage capacitor is grounded;

the charge and discharge management unit is connected to the control end of the booster circuit and is also connected to the first end of the charge and discharge control circuit and the second end of the charge and discharge control circuit;

the booster circuit is used for being connected to an interface of the storage device, and the charge and discharge management unit is used for being connected to a control component of the storage device.

2. The power management unit of the storage device of claim 1, wherein the boost circuit is for connection to a power input pin of an interface of the storage device.

3. The power management unit of the storage device of claim 1, wherein the charge and discharge management unit is connected to an indicator light located outside the storage device.

4. The power management unit of the memory device according to any one of claims 1 to 3, wherein the current limiting resistor of the charge and discharge control circuit is connected between the first terminal and the second terminal.

5. The power management unit of the memory device of claim 4, wherein the current limiting resistor has a resistance of 100 ohms.

6. The power management unit of the memory device of claim 5, wherein a cathode of the diode/MOSFET switch of the charge and discharge control unit is connected to the first terminal, an anode of the diode/MOSFET switch of the charge and discharge control circuit is connected to the second terminal, and the diode/MOSFET switch is connected in parallel with the current limiting resistor;

the charge and discharge management unit is also connected to the control terminal of the diode/MOSFET switch.

7. The power management unit of the storage device according to any one of claims 1 to 3, wherein the charge and discharge management unit is connected to a control terminal of a switching tube in the boost circuit.

8. The power management unit of the storage device according to any one of claims 1 to 3, wherein the energy storage capacitor has a plurality of capacitors, and the plurality of capacitors are connected in parallel between the second terminal of the charge and discharge control circuit and ground.

9. A storage device, comprising: an interface, a control unit of a storage device and a power management unit of the storage device of any one of claims 1 to 8 above;

the boosting circuit of the power management unit of the storage device is connected to an interface of the storage device;

the charging and discharging management unit of the power management unit of the storage device is connected to the control component of the storage device.

10. The storage device of claim 9, further comprising: the NVM and the DRAM are connected, and the control unit is connected to the NVM and the DRAM.