CN113608930B - System chip and electronic device - Google Patents
System chip and electronic device Download PDFInfo
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- CN113608930B CN113608930B CN202110977669.6A CN202110977669A CN113608930B CN 113608930 B CN113608930 B CN 113608930B CN 202110977669 A CN202110977669 A CN 202110977669A CN 113608930 B CN113608930 B CN 113608930B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1435—Saving, restoring, recovering or retrying at system level using file system or storage system metadata
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1438—Restarting or rejuvenating
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1441—Resetting or repowering
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application provides a system chip and an electronic device, the system chip comprising: at least one business processing module and a nonvolatile storage module; the nonvolatile memory module is electrically connected with the service processing module; the business processing module is used for processing corresponding business; and after the abnormal power-off signal is received, storing the verification data of the corresponding service in a nonvolatile storage module, wherein the verification data is used for verifying the service data generated by the corresponding service. According to the system and the method, the nonvolatile memory module is integrated on the system chip, so that after the system chip is abnormally powered down, the check data on the service processing module is stored in the nonvolatile memory module, the loss of the check data is avoided, and then the service processing module can still work normally after the next power-up after the abnormal power-down.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to a system chip and an electronic device.
Background
In general, when the electronic device is powered off normally, the user data in the system chip is stored in a nonvolatile memory (flash) from a dynamic random access memory (DDR), and then the related user data can be recovered when the electronic device is powered on next time.
However, various abnormal power failure situations may occur in the use process of the electronic device, for example, sudden power failure, abnormal battery of the electronic device, abnormal closing of an electric switch, and the like. Under these circumstances, the dynamic random access memory and the nonvolatile memory will stop working, so that the dynamic random access memory cannot store the user data into the nonvolatile memory, and the electronic device cannot work normally when being started next time.
Disclosure of Invention
The application provides a system chip and electronic equipment for solve the problem that the check data is lost when the system chip is abnormally powered down.
In a first aspect, the present application provides a system-on-chip, comprising: at least one business processing module and a nonvolatile storage module; the nonvolatile memory module is electrically connected with the service processing module;
the business processing module is used for processing corresponding business; and after the abnormal power-off signal is received, storing the verification data of the corresponding service in a nonvolatile storage module, wherein the verification data is used for verifying the service data generated by the corresponding service.
Optionally, the system chip further includes: the power management module is connected with the application processor, the application processor is connected with the power management module, and the service processing module is connected with the application processor and the power management module; the power management module is used for detecting whether the service processing module and the nonvolatile storage module are powered down or not after receiving the abnormal power-down signal; if the service processing module and/or the nonvolatile storage module are powered down, transmitting an abnormal power-down signal to the application processor; and the application processor is used for responding to the received abnormal power-down signal and controlling the power supply management module to power up the power-down business processing module and/or the nonvolatile storage module.
Optionally, the service processing module includes: the device comprises a random storage unit and an operation unit, wherein the target stack of the random storage unit stores check data; the operation unit is a unit in an operation state before abnormal power failure; the application processor is specifically used for controlling the power management module to power up the target stack and the running unit.
Optionally, the service processing module is specifically configured to: and storing the verification data in the target stack in the nonvolatile memory module through the operation unit.
Optionally, the system chip further includes: a control module; the power management module is connected with the control modules and is also used for powering off the control modules after receiving the abnormal power-off signal.
Optionally, the service processing module is further configured to: after the verification data is stored in the nonvolatile memory module, generating a storage completion identification, and transmitting the storage completion identification to the application processor; the application processor is also used for receiving the storage completion identification transmitted by the service processing module and controlling the power management module to power off the system chip according to the storage completion identification.
Optionally, the service processing module is further configured to: after the restarting of the electronic equipment is detected, acquiring check data from a nonvolatile storage module; and operating the service processing module according to the verification data.
Optionally, the service processing module is specifically configured to: and after the electronic equipment is detected to restart, if the verification data acquisition from the random storage unit fails, the verification data is acquired from the nonvolatile storage module.
Optionally, the nonvolatile memory module is integrated in the service processing module.
Optionally, the nonvolatile memory module includes: one-time programmable memory.
A second aspect of the present application provides an electronic device, including a system chip as any one of the above, the electronic device further including: the system comprises a battery, a power management chip, a nonvolatile memory and a dynamic random access memory; the battery is connected with the power management chip, the power management chip is connected with the system chip, the nonvolatile memory is connected with the application processor, and the dynamic random access memory is used for being connected with the service processing module.
The application provides a system chip and an electronic device, the system chip comprising: at least one business processing module and a nonvolatile storage module; the nonvolatile memory module is electrically connected with the service processing module; the business processing module is used for processing corresponding business; and after the abnormal power-off signal is received, storing the verification data of the corresponding service in a nonvolatile storage module, wherein the verification data is used for verifying the service data generated by the corresponding service. According to the system and the method, the nonvolatile memory module is integrated on the system chip, so that after the system chip is abnormally powered down, the check data on the service processing module is stored in the nonvolatile memory module, the loss of the check data is avoided, and then the service processing module can still work normally after the next power-up after the abnormal power-down.
Drawings
For a clearer description of the technical solutions of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being obvious that the drawings in the following description are some embodiments of the invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of an application scenario of a system chip provided in the present application;
FIG. 2 is a block diagram of a system-on-chip provided herein;
FIG. 3 is a block diagram of another electronic device provided herein;
FIG. 4 is a block diagram of another electronic device provided herein;
FIG. 5 is a schematic flow chart of steps executed by a system on chip in normal power-down;
FIG. 6 is a schematic flow chart of steps performed by the system chip in the event of abnormal power failure;
fig. 7 is a flowchart illustrating steps performed by the system on chip after restarting.
Detailed Description
For the purposes, technical solutions and advantages of the present application, the technical solutions in the present application will be clearly and completely described below with reference to the drawings in the present application, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to fall within the scope of the invention.
First, for ease of understanding, some terms of the present application will be explained:
PMIC: power Management Integrated Circuit power management chips are chips that are responsible for the conversion, distribution, detection, and other power management of power in electronic device systems.
SoC: system On Chip, a System Chip, is an integrated circuit that integrates a computer or electronic System into a single Chip.
PMU: power Management Unit, a power management unit in the SOC is responsible for powering up and down and low power (low power consumption) management of each module in the SOC.
Wdg: the watch dog is a module for monitoring the working state of the electronic equipment, and the electronic equipment is triggered when abnormal. Integrated on the system chip, the electronic device operates Wdg at intervals of a preset time when operating normally, and if Wdg does not operate after exceeding the preset time, the electronic device is determined to be abnormal.
7s Reset: it means that 7 seconds of pressing the electronic device, the PMIC is forced to power off the system chip and then power up again.
OTP: over-temperature Protection, the Over-temperature protection refers to the action of protecting the electronic equipment by adopting a special means when the temperature of the running electronic equipment exceeds the set temperature.
OVP: over-voltage Protection, overvoltage protection, refers to a protection mode that when the line voltage of an electronic device exceeds a set voltage, the power supply is disconnected or the voltage of the electronic device is reduced.
Efuse: the one-time programmable memory is an electronic fuse, and can realize data updating and permanent storage for thousands of times through hardware special design optimization.
AON: always on, refer to the corresponding module always being on/powered.
APDU: application Protocol Data Unit, application protocol data unit, is a legal data/communication channel for the outside of the service module
AP: application processor, an application processor, is a very large scale integrated circuit that extends the audio functions and dedicated interfaces on the basis of a low power CPU (central processing unit).
Exemplary, fig. 1 is a schematic view of an application scenario of a system chip provided in the present application, and specifically, the system chip is disposed in an electronic device, for example, a mobile phone, a tablet computer, a smart watch, or a smart home. In addition, the system chip is battery powered as shown in fig. 1. In fig. 1, an electronic device 100 includes: a system chip 10, a battery 20, a power management chip 30, a nonvolatile memory 40, and a dynamic random access memory 50. The system chip 10 includes a power management module 11, an application processor 12, and a service processing module 13. The service processing module 13 includes a random storage unit 131.
In fig. 1, the service processing module 13 is a processing module set for a specific service, for example, a banking service, an insurance service, a communication service, and the like. The service processing module 13 generates service data and check data during operation. The service data is encrypted and checked and then output to the dynamic random access memory 50. The application processor 12 further transfers the service data in the dynamic random access memory 50 to the nonvolatile memory 40, thereby realizing access according to the service requirement. And the verification data generated by the service processing module 13 is stored in the random access memory 131. Under the condition that the service processing module 13 is powered down, but the random storage unit 131 is always powered up, after the service processing module 13 is powered up again, the check data can be directly read in the random storage unit 131, so that the service processing module can be operated in real time, and the service processing efficiency is improved.
When the normal program is adopted for power-down, the service processing module 13 will store the check data in the random storage unit 131 in the dynamic random storage 50, and then the check data is transferred to the nonvolatile memory 40 by the application processor 12, so that the check data can be obtained from the nonvolatile memory 40 when the power-up is performed next time, and the service processing module 13 is operated.
The verification data is used for verifying the service data, so that the service processing module can work normally. Illustratively, in banking, service data such as fingerprint data, bank card amount, change log records, and the like. The check data is comparison data corresponding to the service data and is used for comparing the integrity and the correctness of the service data.
However, under the abnormal power failure condition, the nonvolatile memory 40 and the dynamic random access memory 50 usually stop working, so that the check data in the random access memory 131 cannot be stored in the nonvolatile memory 40, and further, the service processing module 13 cannot obtain the check data when the power is next turned on, which results in the problem that the service processing module cannot work normally.
In order to solve the above problems, the present application provides a system chip, in which a nonvolatile memory module is disposed, and after an electronic device is abnormally powered down, check data in a random memory unit can be stored in the nonvolatile memory module, so that after the next power-up of the system chip, the check data can be directly obtained in the nonvolatile memory module, thereby realizing normal operation of a service processing module.
The technical scheme of the invention is described in detail below by specific examples. The following specific embodiments of the results may be combined with each other and may not be described in detail for the same or similar concepts or processes in some embodiments.
Fig. 2 is a block diagram of a system chip provided in the present application, and as shown in fig. 2, the system chip 10 includes: at least one service processing module 13 and a nonvolatile memory module 14; the nonvolatile memory module 14 is electrically connected with the service processing module 13; a service processing module 13, configured to process a corresponding service; and after receiving the abnormal power-down signal, storing the verification data of the corresponding service in the nonvolatile storage module 14, wherein the verification data is used for verifying the service data generated by the corresponding service.
Wherein the nonvolatile memory module includes: one time programmable memory (Efuse). The Efuse is simple to initialize, and corresponding check data can be permanently stored under the abnormal power failure condition. Efuse has a certain life, can be permanently saved and updated thousands of times, but in this application Efuse will only be used in the event of an abnormal power loss. The abnormal power down frequency of the electronic device is usually low, so the Efuse is sufficient to support the storage of verification data of the electronic device when the electronic device is abnormally powered down during the service life of the electronic device.
In addition, before storing the verification data of the corresponding service in the nonvolatile memory module, the method further comprises: the stored data in the nonvolatile memory module 14 is emptied. And then storing the verification data of the corresponding service in a nonvolatile storage module. In the embodiment of the present application, when the check data is stored in the nonvolatile memory module 14, the stored data in the nonvolatile memory module 14 is emptied in advance. The check data stored in the nonvolatile memory module 14 can be the check data needed after the electronic device is restarted next time, and can be directly obtained.
Specifically, the system chip includes a plurality of modules, such as a power management module 11, an application processor 12, a service processing module 13, and other control modules 15 in fig. 3. In normal operation of the electronic device, the power management module 11 is always in an electrical state (AON), and other modules (the application processor 12, the service processing module 13, and the other control modules 15) are in an electrical state only during operation, and are in a power-down state during non-operation.
Further, each hardware of the electronic device monitors various abnormal power failures, and then sends the abnormal power failure signals to the service processing module. For example, referring to fig. 2, the system chip 10 may be connected to a circuit board of the battery 20 through the power management chip 30, and after the battery 20 of the electronic device is unplugged, the circuit board of the battery 20 may detect that the battery 20 is unplugged, and then generate an abnormal power-down signal to send to the service processing module 13. In addition, when the user presses the electronic device for 7 seconds (7 s Reset), the system chip 10 can monitor the corresponding operation and send an abnormal power-down signal to the service processing module 13.Wdg does not operate for a preset time, wdg transmits an abnormal power down signal to the service processing module 13. The system-on-chip 10 further includes: temperature sensor and voltage sensor, temperature sensor monitor whether Over Temperature Protection (OTP) or voltage sensor monitor whether overvoltage protection (OVP) is needed, if need temperature sensor or voltage sensor send unusual power down signal to business processing module 13. In the embodiment of the present application, any hardware in the electronic device may also monitor whether there is an abnormal power failure in other manners, and if so, send a corresponding abnormal power failure signal to the service processing module, which is not limited herein.
In the embodiment of the present application, referring to fig. 2 to 4, the system chip 10 further includes: the power management module 11 and the application processor 12, the application processor 12 and the power management module 11 are connected, and the service processing module 13 is connected with the application processor 12 and the power management module 11; the power management module 11 is used for detecting whether the service processing module 13 and the nonvolatile storage module 14 are powered down after receiving the abnormal power-down signal; if the service processing module 13 and/or the nonvolatile storage module 14 are powered down, transmitting an abnormal power-down signal to the application processor 12; an application processor 12, configured to control the power management module 11 to power up the power-down service processing module 13 and/or the nonvolatile storage module 14 in response to receiving the abnormal power-down signal.
Specifically, abnormal power failure in the present application refers to a situation that the battery stops supplying power to the electronic device or the battery power is small enough to support power supply to the whole electronic device. After the battery stops supplying power to the electronic device, the power management chip comprises: the capacitor can store a part of the electric quantity and continuously supply power to the system chip 10. In addition, however, due to the limited amount of electricity in the capacitor, the service processing module 13 may be in a power-up state after abnormal power failure, and may also be powered down.
If the service processing module 13 and the nonvolatile storage module 14 are in the power-on state, the hardware sends the corresponding abnormal power-off signal to the service processing module 13, and the service processing module 13 stores the verification data of the corresponding service in the nonvolatile storage module 14, where the verification data is used for verifying the service data generated by the corresponding service. If the service processing module 13 and/or the nonvolatile storage module 14 are in the power-down state, the hardware sends the corresponding abnormal power-down signal to the power management module 11 and the service processing module 13, and after the power management module 11 powers on the service processing module 13 and/or the nonvolatile storage module 14, the service processing module 13 stores the verification data in the nonvolatile storage module 14.
Further, referring to fig. 3, the service processing module 13 includes: a random storage unit 131 and an operation unit 132, wherein the target stack of the random storage unit 131 stores check data; the operation unit 132 is a unit that is in an operation state before abnormal power-off; the application processor 12 is specifically configured to control the power management module 11 to power up the target stack and the execution unit 132.
The service processing module 13 is specifically configured to: the check data in the target stack is saved in the nonvolatile memory module 14 by the execution unit 132.
Specifically, during the operation of the service processing module 13, the service processing module 13 only operates a part of the operation units 132 therein. The check data is also stored in a portion of the stack space of the random access memory 131, and the portion of the stack space is the target stack. Controlling the power management module 11 to power up the service processing module 13 means powering up only the target stack and the execution unit 132.
In the embodiment of the present application, after the power supply to the system chip 10 is abnormally interrupted by the battery 20, the power supply to the system chip 10 is only performed by the capacitor in the power management chip 30, and since the electric quantity of the capacitor of the power management chip 30 is limited, only the target stack and the operation unit 132 need to be powered, so that power supply to the stack and other operation units of unnecessary parts is avoided, and electric quantity waste is caused.
Wherein, referring to fig. 4, the system chip 10 further includes: a control module 15; the power management module 11 is connected with the control modules 15, and the power management module 11 is further configured to power off the plurality of control modules 15 after receiving the abnormal power-off signal.
Specifically, referring to fig. 4, the control module a is a module for controlling the operation of the nonvolatile memory 40, and the control module B is a module for controlling the operation of the dynamic random access memory 50. The control module 15 in the embodiment of the present application may also be any module on the system chip 10 other than the power management module 11, the application processor 12, the service processing module 13, and the nonvolatile storage module 14. Such as a wireless module, an audio module, a video module, etc.
In the embodiment of the present application, each control module 15 is powered off, so that the waste of the electric quantity of the power management chip 30 can be avoided under the abnormal power failure condition.
Wherein, the business processing module is further used for: after the verification data is stored in the nonvolatile memory module, generating a storage completion identification, and transmitting the storage completion identification to the application processor; the application processor is also used for receiving the storage completion identification transmitted by the service processing module and controlling the power management module to power off the system chip according to the storage completion identification.
Specifically, after the verification data is stored in the nonvolatile memory module 14, the verification data is saved, and the entire system chip may be powered down.
Wherein, the business processing module is further used for: after the restarting of the electronic equipment is detected, acquiring check data from a nonvolatile storage module; and operating the service processing module according to the verification data.
It will be appreciated that the restart of the electronic device is detected with reference to detecting an abnormal power loss. Illustratively, after the battery 20 of the electronic device is plugged, the circuit board of the battery 20 may detect that the battery 20 is plugged, and generate a restart signal to send to the service processing module 13.Wdg is run again within the preset time, wdg will restart sending the service processing module 13 etc.
The service processing module is specifically configured to: and after the electronic equipment is detected to restart, if the verification data acquisition from the random storage unit fails, the verification data is acquired from the nonvolatile storage module.
Referring to fig. 4, a nonvolatile memory module 14 is integrated in the service processing module 13. In the embodiment of the present application, the nonvolatile storage module 14 is integrated in the service processing module 13, so that the verification data can be more efficiently stored in the nonvolatile storage module 14.
Fig. 5 shows a flowchart of specific working steps of the system chip provided in the present application in a normal power-down situation. The method specifically comprises the following steps:
s101, the power management module receives the normal power-down signal and sends the normal power-down signal to the application processor.
The normal power-down signal is a signal triggered by a user after the electronic equipment is normally turned off. The power management module receives the normal power-down signal and sends the normal power-down signal to the application processor.
S102, the application processor determines whether the power management module works normally or not, and controls the power management module to power up the service processing module or wake up the service processing module.
The application processor can acquire the working state of the power management module in real time, and acquires whether the power management module powers on the service processing module or not, or whether the service processing module is in a low-power consumption state, if so, the power management module is controlled to power on the service processing module or wake up the service processing module.
S103, the power management module powers on the service processing module or wakes up the service processing module.
S104, initializing a service processing module, performing self-checking operation and recovering a low-power consumption state.
The initialization refers to APDU (application protocol data unit) channel initialization, and the self-checking operation refers to state self-checking of security of a service processing module. The service processing module may consume more time and power to perform a full power up or service processing module initialization, self-checking operations, and low power state restoration.
S105, the application processor sends a normal complete power-down instruction to the service processing module.
The application processor initiates a normal complete power-down instruction to the service processing module through an APDU (application protocol data unit) to request the service processing module to execute a complete power-down operation.
And S106, the service processing module responds to the normal complete power-down instruction and stores the check data into the random dynamic memory.
After the initialization of the service processing module is completed, an APDU channel instruction is analyzed, a 'normal complete power-down' instruction is responded, a complete power-down flow is carried out, and verification data protection processing (encryption, message verification code generation and the like) is output to a random dynamic memory (DDR).
S107, the service processing module sends a power-down instruction waiting for normal power-down to the application processor.
And the service processing module feeds back the information of the power-down instruction waiting for normal power-down to the application processor through the APDU channel.
S108, the application processor judges whether the power-down instruction is normal power-down, if so, S109 is executed.
S109, the application processor stores the verification data from the random dynamic memory into the nonvolatile memory.
And the application processor stores the check data random dynamic memory after the protection processing into the nonvolatile memory according to the response of the transaction system.
S110, the application processor sends a complete power-down instruction to the power management module.
Wherein, completely powering down refers to the whole service processing module, including: random memory cells, operation cells, nonvolatile memory modules, and the like.
The application processor then proceeds to perform other power-down flows.
S111, the power management module cuts off power supply to the service processing module.
In addition, the power management module also cuts off the power supply to other modules in the system chip so as to completely power down the electronic equipment.
The system chip provided by the application can execute the normal power-down flow, and can still store the verification data when the power is normally down, so that the next time the electronic equipment is started.
However, when the power supply is abnormal, the capacity in the PMIC alone cannot meet the electric quantity required by all hardware, modules or systems including AP, DDR, flash, service processing modules and the like to execute the complete power-down flow. In practical tests, the DDR and flash are found to normally work, and a large amount of electricity is consumed. Other hardware triggers power down when the electronic device is substantially in an abnormal (unstable, untrusted) state. DDR, flash and other necessary modules are hung up, and the storage operation of check data cannot be completed. Therefore, many objective factors under the abnormal electric field failure scene may cause that check data cannot be stored in time to flash, if the business processing module executes some transaction business, the business processing module is abnormal and crashed, and further user data loss and fund loss are caused.
Fig. 6 shows a flowchart of specific working steps of the system chip provided in the present application in an abnormal power-down situation. The method specifically comprises the following steps:
s201, the power management module receives an abnormal power-down signal sent by hardware.
S202, the service processing module receives an abnormal power-down signal sent by hardware.
The hardware detects abnormal power failure and then generates an abnormal power failure signal to the service processing module and the power management module, and the abnormal power failure signal is sent to the power management module and the service processing module.
The hardware referred to herein includes: battery circuit boards, wdg, voltage sensors, temperature sensors, and the like.
S203, the power management module sends an abnormal power-down signal to the application processor.
And S204, the application processor controls the power supply management module to power up the service processing module and controls the power off of other control modules.
The power management module is used for controlling the control module (the power-off control module is an unnecessary module or an unnecessary system which does not operate on the system chip, and the power-off control module can save the data and reserve the electric quantity for the service processing module.
S205, if the service processing module is in the power-down state, S206 is executed, and if the service processing module is in the power-up state, S207 is executed.
S206, the power management module powers on the service processing module.
The power management module preferentially powers up the target stack and the running unit in the service processing module. If the service processing module is in a low power consumption state, the power management module wakes up the service processing module.
S207, after the service processing module is powered on, initializing the service processing module or a program for recovering the low-power consumption state and enabling abnormal power failure interruption.
If the service processing module is in the power-down state previously, the target stack and the running unit running before abnormal power failure are initialized preferentially after power-up. If the service processing module is in a power-on state previously, after receiving the abnormal power-down signal, other units in the service processing module can be initialized and self-checking operation is performed. The target stack and the execution unit are also preferably initialized after waking up if the traffic processing module was previously in a low power state.
S208, the business processing module initializes the nonvolatile memory module and stores the verification data to the nonvolatile memory module.
If the service processing module finds that the power is lost again after S208, steps S201 to S208 are not triggered again, that is, the flow is ended. And the step of repeatedly storing the check data is avoided by electrifying the service processing module again.
Specifically, when the service processing module operates normally, the normal operation of the service processing module is interrupted due to abnormal power failure. In the system chip, the code for interrupting the normal operation is an interrupt code. The present application S201 to S208 are designed at the tail of the interrupt code. It is avoided that S201 to S208 are continued after the interrupt code is exited, and related data read-write actions are generated.
S209, the business processing module generates an abnormal power-down identifier and sends the abnormal power-down identifier to the application processor.
S210, the application processor judges whether an abnormal power-down identification is accepted, if yes, S211 is executed.
S211, the application processor executes other power-down flows.
In the embodiment of the application, DDR and flash work abnormally under the condition of abnormal power failure, and the state is unstable and unreliable. The system chip cannot save the check data to the DDR and flash. If no anomaly occurs in the service processing module and the Efuse, the check data (a small amount but very important) can be saved to the Efuse in an urgent manner. Typically, after a battery power failure or a PMIC power failure, a capacitor in the PMIC still stores a portion of the power. The voltage reduction of the capacitor is a continuous process, and the application can complete corresponding hardware and software operations to store the verification data before the voltage is gradually reduced to the lowest voltage at which the application processor, the service processing module and the Efuse thereof cannot be maintained to operate.
Fig. 7 shows a flowchart of specific working steps when the system chip provided in the present application is powered down normally or abnormally and the electronic device is started again. The method specifically comprises the following steps:
s301, if the nonvolatile memory has check data, the application processor saves the check data to the random dynamic memory.
S302, the application processor monitors the power management module and controls the power management module to power up the service processing module.
S303, the power management module powers on the service processing module.
S304, initializing a service processing module, performing self-checking operation and recovering a low-power consumption state.
S305, the business processing module acquires the check data from the random storage unit, if so, the business processing module executes S308, and if not, the business processing module executes S306.
Specifically, the service processing module acquires the check data from the random storage unit, if the check data is acquired, checks the check data, if the check data passes, the check data is required, and then S308 is executed. If the verification is not passed or the verification data is not obtained, S306 is performed.
S306, the business processing module acquires the check data from the random dynamic memory, if so, the business processing module executes S308, and if not, the business processing module executes S307.
Specifically, the service processing module acquires the check data from the random dynamic memory, if the check data is acquired, checks the check data, if the check data passes, the check data is required, and then S308 is executed.
If the verification is not passed or the verification data is not obtained, S307 is executed.
S307, the business processing module acquires the check data from the nonvolatile storage module, if so, the business processing module executes S308, and if not, the business processing module ends the flow.
Specifically, the service processing module acquires the check data from the nonvolatile storage module, if the check data is acquired, checks the check data, if the check data passes, the check data is required, and then S308 is executed.
If the verification is not passed or the verification data is not obtained, the service processing module runs through, and the flow is ended.
S308, the service processing module works normally.
In the embodiment of the application, in the next complete power-on of the electronic device, the application processor transmits the processed check data and service data from flash to DDR. After the service processing module is powered on, the random storage unit is detected to have no check data, and the check data is obtained from the DDR. And if the verification process finds that the verification data in the DDR is not the latest version data, the verification fails. And further acquiring corresponding check data from the Efuse, checking the correctness and performing initialization operation.
In the present embodiment, the Efuse is able to save and update data about thousands of times. Wherein, except the testing environment of the research personnel, the user does not intentionally make abnormal electric field drop scenes. Therefore, the life of the Efuse is enough to be used in the life cycle of the electronic equipment, and the effectiveness of storing the verification data is improved.
Referring to fig. 3 and 4, there is shown an electronic device 100 provided herein, including a system chip 10 as any one of the above, the electronic device further comprising: a battery 20, a power management chip 30, a nonvolatile memory 40, and a dynamic random access memory 50; the battery 20 is connected to the power management chip 30, the power management chip 30 is connected to the system chip 10, the nonvolatile memory 40 is connected to the application processor 12, and the dynamic random access memory 50 is connected to the service processing module 13.
The application provides a system chip and an electronic device, the system chip comprising: at least one business processing module and a nonvolatile storage module; the nonvolatile memory module is electrically connected with the service processing module; the business processing module is used for processing corresponding business; and after the abnormal power-off signal is received, storing the verification data of the corresponding service in a nonvolatile storage module, wherein the verification data is used for verifying the service data generated by the corresponding service. According to the system and the method, the nonvolatile memory module is integrated on the system chip, so that after the system chip is abnormally powered down, the check data on the service processing module is stored in the nonvolatile memory module, the loss of the check data is avoided, and then the service processing module can still work normally after the next power-up after the abnormal power-down.
In the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the front and rear associated objects are an "or" relationship; in the formula, the character "/" indicates that the front and rear associated objects are a "division" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c may represent: a, b, c, a-b, a-c, b-c, or a-b-c, wherein a, b, c may be single or plural.
It will be appreciated that the various numerical numbers referred to in the embodiments of the present application are merely for ease of description and are not intended to limit the scope of the embodiments of the present application. In the embodiments of the present application, the sequence number of each process does not mean the sequence of execution sequence, and the execution sequence of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present application, and not for limiting the same; although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the corresponding technical solutions from the scope of the technical solutions of the embodiments of the present application.
Claims (6)
1. A system-on-chip, comprising: the system comprises at least one business processing module, a nonvolatile storage module, a power management module and an application processor; the nonvolatile memory module is electrically connected with the service processing module; the application processor is connected with the power management module, and the service processing module is connected with the application processor and the power management module;
the service processing module is used for processing corresponding services; after receiving the abnormal power-off signal, storing the verification data of the corresponding service in the nonvolatile storage module, wherein the verification data is used for verifying the service data generated by the corresponding service;
the service processing module comprises: the target stack of the random storage unit stores the check data; the operation unit is a unit in an operation state before abnormal power failure;
the service processing module is specifically configured to: storing the check data in the target stack in the nonvolatile memory module through the operation unit;
the nonvolatile memory module is integrated in the service processing module;
the nonvolatile memory module includes: a one-time programmable memory;
the power management module is used for detecting whether the service processing module and the nonvolatile storage module are powered down or not after the abnormal power-down signal is received; if the service processing module and/or the nonvolatile storage module is powered down, transmitting the abnormal power-down signal to the application processor; if the service processing module and the nonvolatile storage module are in a power-on state, an abnormal power-off signal is sent to the service processing module, and the service processing module stores verification data of corresponding service in the nonvolatile storage module;
the application processor is used for responding to the received abnormal power-down signal and controlling the power management module to power up the power-down business processing module and/or the nonvolatile storage module;
the application processor is specifically configured to control the power management module to power up the target stack and the running unit.
2. The system chip of claim 1, wherein the system chip further comprises: a control module;
the power management module is connected with the control module and is also used for powering off the control module after receiving the abnormal power-off signal.
3. The system chip of claim 1, wherein the traffic processing module is further configured to:
after the verification data is stored in the nonvolatile storage module, a storage completion identification is generated, and the storage completion identification is transmitted to the application processor;
the application processor is further configured to receive a storage completion identifier transmitted by the service processing module, and control the power management module to power off the system chip according to the storage completion identifier.
4. The system chip of claim 3, wherein the traffic processing module is further configured to:
after the restarting of the electronic equipment is detected, acquiring the check data from the nonvolatile storage module;
and operating the service processing module according to the verification data.
5. The system chip of claim 4, wherein the service processing module is specifically configured to:
and after the electronic equipment is detected to restart, if the verification data is failed to be acquired from the random storage unit, acquiring the verification data from the nonvolatile storage module.
6. An electronic device comprising the system chip of any one of claims 1 to 5, the electronic device further comprising: the system comprises a battery, a power management chip, a nonvolatile memory and a dynamic random access memory;
the power management chip is connected with the system chip, the nonvolatile memory is connected with the application processor, and the dynamic random access memory is used for being connected with the service processing module.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110977669.6A CN113608930B (en) | 2021-08-24 | 2021-08-24 | System chip and electronic device |
| PCT/CN2022/110174 WO2023024863A1 (en) | 2021-08-24 | 2022-08-04 | System chip and electronic device |
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| CN202110977669.6A CN113608930B (en) | 2021-08-24 | 2021-08-24 | System chip and electronic device |
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| CN113608930B (en) * | 2021-08-24 | 2023-06-13 | 厦门紫光展锐科技有限公司 | System chip and electronic device |
| CN117093535A (en) * | 2022-05-13 | 2023-11-21 | 华为技术有限公司 | System on chip and power-on recovery method of related system |
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| US10331203B2 (en) * | 2015-12-29 | 2019-06-25 | Texas Instruments Incorporated | Compute through power loss hardware approach for processing device having nonvolatile logic memory |
| CN105677588A (en) * | 2016-01-06 | 2016-06-15 | 浪潮(北京)电子信息产业有限公司 | Method and device for protecting data |
| CN106648982B (en) * | 2016-12-15 | 2019-12-20 | 宁波迦南智能电气股份有限公司 | Power-down protection data storage method for electric energy meter |
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| CN113608930B (en) * | 2021-08-24 | 2023-06-13 | 厦门紫光展锐科技有限公司 | System chip and electronic device |
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| CN103345189A (en) * | 2013-07-29 | 2013-10-09 | 浙江中控技术股份有限公司 | Controller and power fail safeguard method |
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| WO2023024863A1 (en) | 2023-03-02 |
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