CN104035893A - Method for data storage during abnormal power down of computer - Google Patents
Method for data storage during abnormal power down of computer Download PDFInfo
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Abstract
The invention discloses a method for data storage during abnormal power down of a computer. The method comprises the steps that a PSU gives out power down warning signals to a mainboard CPLD before the power down; the mainboard CPLD sends a request for triggering synchronization to a PCH; the PCH sends a synchronizing signal to all CPUs after receiving the request; each CPU writes data in a Cache into a DRAM after receiving the synchronizing signal, and then sends a write-in completing mark to a controller of a mixed cache after write-up operation; when the controller detects the write-in completing mark, all the data in the DRAM are transferred to an NVM, and a storage completing signal is sent to the PCH after data transfer is completed; the PCH writes in a marking state of abnormal power down shutdown in an internal memory. According to the method for the data storage during the abnormal power down of the computer, when the computer powers down suddenly, running data of the computer can be stored in the NVM, when a system is restarted, the data can be read from the NVM, and reproduction of an accident site can be achieved, and losses of a user are reduced.
Description
Technical field
The present invention relates to computer realm, be specifically related to a kind of data save method when computing machine powered-off fault.
Background technology
General computer memory system is comprised of internal memory and external memory, according to storage speed speed, be respectively the cache memory Cache of CPU inside, dynamic RAM (Dynamic Random Access Memory, be called for short DRAM) internal memory and solid state hard disc (Solid State Disk, be called for short SSD) or mechanical hard disk external memory, wherein Cache and DRAM consist of volatile storage medium, its key property is that after power-off, data can not be preserved, and SSD or mechanical hard disk are by non-volatile memory medium (Non-Volatile Memory, be called for short NVM) form, after its power-off, data can not lost.During computer operation, first CPU obtains data from Cache, if do not found from DRAM in Cache, if also just do not found from hard disk in DRAM again.If computing machine is system power down suddenly when normal work, because data in Cache and DRAM are not preserved in time, all data of moving in Cache and DRAM all can be lost, and in some crucial applied field credit unions, bring massive losses.
Summary of the invention
The technical issues that need to address of the present invention are to provide a kind of data save method when computing machine powered-off fault, when the unexpected power down of computing machine, the data that computing machine can moved are saved in non-volatile memory medium NVM, when system restart, can from NVM, read the data of these preservations again, thereby realized the reproduction to the scene of the accident, can reduce the loss to user.
In order to solve the problems of the technologies described above, the invention provides a kind of data save method when computing machine powered-off fault, comprising:
When sequential logical circuit detects after power supply power-fail alarm signal, the controller that triggers mixing internal memory writes the data in volatile storage medium in non-volatile memory medium.
Further, described sequential logical circuit is realized by complex programmable logic device (CPLD), and described volatile storage medium comprises: cache memory Cache and dynamic RAM DRAM;
The controller of described triggering mixing internal memory also comprises before the data in volatile storage medium are write in non-volatile memory medium:
When described CPLD detects after power supply power-fail alarm signal, flip chip group PCH notice CPU writes the data in described Cache in DRAM.
Further, the controller of described triggering mixing internal memory writes the data in volatile storage medium in non-volatile memory medium, comprising:
After described CPU completes in the data in described Cache are write to described DRAM, write complement mark to the controller transmission that mixes internal memory;
When the controller of described mixing internal memory detects said write complement mark, the data in described DRAM are transferred in non-volatile memory medium NVM.
Further, described CPU comprises one or more, and described mixing internal memory comprises: controller, DRAM and NVM, the corresponding one or more mixing internal memories of CPU.
Further, adopt the mode of super capacitor power supply in described mixing internal memory, super capacitor supports described controller, DRAM and NVM to continue to work until completing of data transfer by the electric charge of storage.
Further, described method also comprises:
After data have shifted, the controller of described mixing internal memory sends preserves settling signal to described PCH, notifies described PCH to complete the operation that data shift.
Further, described method also comprises:
When described PCH receives after the preservation settling signal that the controller of described mixing internal memory sends, in internal register, write the sign state of a powered-off fault shutdown.
Further, described method also comprises:
When again starting shooting, basic input/output BIOS judges whether powered-off fault shutdown according to described sign state, if so, selects from described NVM, data to be recovered.
Compared with prior art, in an embodiment provided by the invention, when the unexpected power down of computing machine, the data that computing machine can moved are saved in non-volatile memory medium NVM, when system restart, can from NVM, read the data of these preservations again, thereby realized the reproduction to the scene of the accident, can reduce user's loss; In another embodiment, can all preserve the service data in Cache and DRAM, so just can guarantee the integrality of data, the data in the time of can be on-the-spot to powered-off fault when system restart are carried out complete recovery; In another embodiment, in order to improve whole data, preserve the reliability of process, prevent that system power supply PSU continued power deficiency of time, Memory Controller Hub after power down warning is sent from cannot complete the problem that data shift, the present invention proposes the mode that adopts super capacitor power supply in mixing internal memory, super capacitor can allow Memory Controller Hub, DRAM and NVM continue to work until completing of data transfer by the electric charge of storage.
Accompanying drawing explanation
Fig. 1 is the structural drawing of a kind of data store system when computing machine powered-off fault in embodiment;
Fig. 2 is the structural drawing that mixes internal memory in embodiment;
Fig. 3 is a kind of data save method process flow diagram when computing machine powered-off fault in embodiment.
Embodiment
For making the object, technical solutions and advantages of the present invention clearer, hereinafter in connection with accompanying drawing, embodiments of the invention are elaborated.It should be noted that, in the situation that not conflicting, the embodiment in the application and the feature in embodiment be combination in any mutually.
Embodiment:
As shown in Figure 1, the present embodiment provides a kind of data store system when computing machine powered-off fault, comprise: power module PSU (Power Supply Unit, power supply provides unit), sequential logical circuit is (mainly by mainboard CPLD (Complex Programmable Logic Device, CPLD) realization), the chipset PCH (Platform Controller Hub) of Intel, one or more CPU, and the mixing internal memory being connected with CPU, wherein:
Power module PSU has power down warning function, before power module power down, can send alerting signal to CPLD, and direct supply can also continue to provide the supporting time that is greater than 1ms;
Mainboard CPLD, for after detecting the power down alerting signal of power module, notifies PCH to carry out internal memory power-down data protection process immediately;
PCH is used for receiving after the request of processing, carries out power down protection flow process immediately by " synchronous bus " notice CPU;
CPU is for receiving after the synchronization request of PCH, in order to guarantee that in whole volatile storage medium, (DRAM and Cache) data can be preserved, first the data in Cache are write in DRAM at once, write complement mark then after Cache data write, to one of the controller transmission that mixes internal memory;
Once mix the controller of internal memory for detecting said write complement mark, carry out immediately the process of the data in DRAM all being transferred to NVM, etc. data, send " preservation completes " signal to PCH after having shifted, the completing of indication internal storage data preservation;
PCH also for, when PCH receives, mix after " preservation completes " signal that the controller of internal memory sends, in internal register, write the sign state of a powered-off fault shutdown, for example, a zone bit of register is configured to represent powered-off fault shutdown at 1 o'clock, is set to 0 and represents normal shutdown; Can by BIOS, be selected with which internal register to identify the state of shutdown, the feature of this register maximum is exactly: the value of system power failure late register can not lost, by the button cell power supply on mainboard.
When again starting shooting, basic input/output (Basic Input Output System is called for short BIOS) reads this sign state and judges normal shutdown or powered-off fault shutdown, for example, sign state is 1 expression powered-off fault shutdown, is 0 expression normal shutdown.If powered-off fault shutdown, data when BIOS can select from NVM power down before read out, and are about to data and recover.
Wherein, as shown in Figure 2, mix internal memory as Installed System Memory, by controller, dram chip, NVM chip, feed circuit and super capacitor etc., formed.
Wherein, dram chip is used as the internal memory of CPU, and NVM only just enables when the system power failure as slack storage equipment; Controller is connected respectively dram chip and NVM chip by DRAM bus and NVM bus, can realize the synchronous of data between the two, when detecting, write complement mark position, carry out immediately the process of the data in DRAM all being transferred to NVM, etc. data, send " preservation completes " signal to PCH after having shifted, what indication internal storage data was preserved completes.
In addition, the effect of super capacitor is when system power failure, to can be used as a stand-by power supply device for mixing memory bar power supply.
The present embodiment provides a kind of data save method when computing machine powered-off fault, comprising:
When sequential logical circuit detects after power supply power-fail alarm signal, the controller that triggers mixing internal memory writes the data in volatile storage medium in non-volatile memory medium.
Described sequential logical circuit is realized by CPLD, and described volatile storage medium is cache memory Cache and dynamic RAM DRAM;
In order to guarantee the integrality of data, data in the time of can be on-the-spot to powered-off fault when system restart are carried out complete recovery, preferably, in the controller that trigger to mix internal memory writes non-volatile memory medium by the data in volatile storage medium before, also comprise:
When described CPLD detects after power supply power-fail alarm signal, trigger PCH notice CPU the data in Cache are write in DRAM;
Wherein, the controller of described triggering mixing internal memory writes the data in volatile storage medium in non-volatile memory medium, comprising:
After described CPU completes in the data in Cache are write to DRAM, write complement mark to the controller transmission that mixes internal memory;
When the controller of described mixing internal memory detects said write complement mark, the data in DRAM are transferred in non-volatile memory medium NVM.
Described CPU comprises one or more, and described mixing internal memory comprises: controller, DRAM and NVM, mix internal memory and be on the main memory access that is inserted in CPU.For instance, if 1 CPU has 4 main memory accesses, each passage is supported at most 3 mixing internal memories, and this CPU can insert at most 12 mixing internal memories so, the corresponding one or more mixing internal memories of CPU.Wherein, dram chip is used as the internal memory of CPU, and NVM only just enables when the system power failure as slack storage equipment; Controller is connected respectively dram chip and NVM chip by DRAM bus and NVM bus, can realize the synchronous of data between the two, when detecting while writing complement mark, carries out immediately the process of the data in DRAM all being transferred to NVM.
In order to improve whole data, preserve the reliability of process, prevent that system power supply PSU continued power deficiency of time, Memory Controller Hub after power down warning is sent from cannot complete the problem that data shift, the present invention proposes the mode that adopts super capacitor power supply in mixing internal memory, super capacitor can allow Memory Controller Hub, DRAM and NVM continue to work until completing of data transfer by the electric charge of storage.
In addition, described method also comprises:
After data have shifted, the controller of described mixing internal memory sends preserves settling signal to described PCH, notifies described PCH to complete the operation that data shift;
When described PCH receives after the preservation settling signal that the controller of described mixing internal memory sends, in internal register, write a sign state of powered-off fault shutdown, for example, by a mark position of register, be to represent powered-off fault shutdown at 1 o'clock, be set to 0 and represent normal shutdown, can by BIOS, be selected with which internal register to identify the state of shutdown, the feature of this register maximum is exactly: the value of system power failure late register can not lost, by the button cell power supply on mainboard.
Wherein, described method also comprises:
When again starting shooting, BIOS judges whether powered-off fault shutdown according to described sign state, and for example, sign state is 1 expression powered-off fault shutdown, is 0 expression normal shutdown, if powered-off fault shutdown is selected from described NVM, data to be recovered.
In an application example, as shown in Figure 3, the data save method when computing machine powered-off fault, comprises the following steps:
S101: system power supply module PSU sent power down alerting signal to mainboard CPLD before power down;
S102: mainboard CPLD detects after the power down alerting signal of power module, notifies PCH to carry out internal memory power-down data protection process immediately, sends the request of triggering synchronous to PCH;
S103:PCH receives after this request, carries out power down protection flow process immediately by " synchronous bus " notice CPU, to all CPU, sends synchronizing signal;
S104: each CPU receives after this synchronizing signal, first writes the data in Cache in DRAM, writes complement mark then after Cache data write, to one of the controller transmission that mixes internal memory;
S105: write complement mark once the controller of mixing internal memory detects this, just the data in DRAM are all transferred in NVM;
S106: after data have shifted, the controller that mixes internal memory sends " preservation completes " signal to PCH, what indication internal storage data was preserved completes;
S107:PCH receives and mixes after " preservation completes " signal that the controller of internal memory sends, writes the sign state of a powered-off fault shutdown in internal register.
So far, the flow process of the data save method when computing machine powered-off fault finishes.
Like this, when again starting shooting, BIOS reads this sign state and judges normal shutdown or powered-off fault shutdown.If powered-off fault shutdown, data when BIOS can select from NVM power down before read out.
From above-described embodiment, can find out, with respect to prior art, the data save method when computing machine powered-off fault providing in above-described embodiment, when the unexpected power down of computing machine, the data that computing machine can moved are saved in non-volatile memory medium NVM, when system restart, can from NVM, read the data of these preservations again, thereby realize the reproduction to the scene of the accident, can reduce user's loss.In addition, in another embodiment, can all preserve the service data in Cache and DRAM, the data in the time of can be on-the-spot to powered-off fault when system restart are carried out complete recovery; In another embodiment, in order to improve whole data, preserve the reliability of process, prevent that system power supply PSU continued power deficiency of time, Memory Controller Hub after power down warning is sent from cannot complete the problem that data shift, the present invention proposes the mode that adopts super capacitor power supply in mixing internal memory, super capacitor can allow Memory Controller Hub, DRAM and NVM continue to work until completing of data transfer by the electric charge of storage.
One of ordinary skill in the art will appreciate that all or part of step in said method can come instruction related hardware to complete by program, described program can be stored in computer-readable recording medium, as ROM (read-only memory), disk or CD etc.Alternatively, all or part of step of above-described embodiment also can realize with one or more integrated circuit.Correspondingly, each the module/unit in above-described embodiment can adopt the form of hardware to realize, and also can adopt the form of software function module to realize.The present invention is not restricted to the combination of the hardware and software of any particular form.
The foregoing is only the preferred embodiments of the present invention, be not intended to limit protection scope of the present invention.According to summary of the invention of the present invention; also can there be other various embodiments; in the situation that not deviating from spirit of the present invention and essence thereof; those of ordinary skill in the art are when making according to the present invention various corresponding changes and distortion; within the spirit and principles in the present invention all; any modification of doing, be equal to replacement, improvement etc., within protection scope of the present invention all should be included in.
Claims (8)
1. the data save method when computing machine powered-off fault, comprising:
When sequential logical circuit detects after power supply power-fail alarm signal, the controller that triggers mixing internal memory writes the data in volatile storage medium in non-volatile memory medium.
2. the method for claim 1, is characterized in that:
Described sequential logical circuit is realized by complex programmable logic device (CPLD), and described volatile storage medium comprises: cache memory Cache and dynamic RAM DRAM;
The controller of described triggering mixing internal memory also comprises before the data in volatile storage medium are write in non-volatile memory medium:
When described CPLD detects after power supply power-fail alarm signal, flip chip group PCH notice CPU writes the data in described Cache in DRAM.
3. method as claimed in claim 2, is characterized in that:
The controller of described triggering mixing internal memory writes the data in volatile storage medium in non-volatile memory medium, comprising:
After described CPU completes in the data in described Cache are write to described DRAM, write complement mark to the controller transmission that mixes internal memory;
When the controller of described mixing internal memory detects said write complement mark, the data in described DRAM are transferred in non-volatile memory medium NVM.
4. the method as described in claim 1 or 2 or 3, is characterized in that:
Described CPU comprises one or more, and described mixing internal memory comprises: controller, DRAM and NVM, the corresponding one or more mixing internal memories of CPU.
5. method as claimed in claim 4, is characterized in that:
In described mixing internal memory, adopt the mode of super capacitor power supply, super capacitor supports described controller, DRAM and NVM to continue to work until completing of data transfer by the electric charge of storage.
6. the method as described in claim 1 or 2 or 3, is characterized in that: described method also comprises:
After data have shifted, the controller of described mixing internal memory sends preserves settling signal to described PCH, notifies described PCH to complete the operation that data shift.
7. method as claimed in claim 6, is characterized in that: described method also comprises:
When described PCH receives after the preservation settling signal that the controller of described mixing internal memory sends, in internal register, write the sign state of a powered-off fault shutdown.
8. method as claimed in claim 7, is characterized in that: described method also comprises:
When again starting shooting, basic input/output BIOS judges whether powered-off fault shutdown according to described sign state, if so, selects from described NVM, data to be recovered.
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