CN108334422A - A kind of method and BMC of control isomery mixing memory system cold restart - Google Patents
A kind of method and BMC of control isomery mixing memory system cold restart Download PDFInfo
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- CN108334422A CN108334422A CN201810089557.5A CN201810089557A CN108334422A CN 108334422 A CN108334422 A CN 108334422A CN 201810089557 A CN201810089557 A CN 201810089557A CN 108334422 A CN108334422 A CN 108334422A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1438—Restarting or rejuvenating
Abstract
The invention discloses a kind of methods and BMC of control isomery mixing memory system cold restart; after computer system sends out cold restart signal; data protection signal is generated, in order to which the NVM in computer system carries out data written-back operation after receiving data protection signal；After detecting that NVM completes data written-back operation, control CPLD carries out power on operation again after carrying out power operation to computing board, and is completed after the power is turned in computing board, and guiding BIOS carries out QPI startups；The channel connection that the CPU after QPI starts in control computer system accesses NVM is completed in BIOS, and the memory information between the DRAM in control computer system and NVM interacts, and BIOS is guided to complete remaining Booting sequence, control computer system completes cold restart.Data when the application protects computer system cold restart in isomery mixing memory, the computer system where making isomery mixing memory can be used normally.
Description
Technical field
The present invention relates to technical field of memory, more particularly to a kind of method of control isomery mixing memory system cold restart
And BMC.
Background technology
With the development of memory technology, and a kind of novel storage medium NVM (Non-Volatile Memory, it is non-volatile to deposit
Reservoir) gradually it is widely used.NVM does not lose with data after step-by-step access capability, power-off, storage density is big, quiescent dissipation
Low, the advantages that dynamic power consumption is high and scalability is strong.But the write delay of NVM is than currently used DRAM (Dynamic
Random Access Memory, dynamic random access memory) one or several orders of magnitude, write-in number are also limited slowly
System, so, in order to meet the real-time demand of computer system, DRAM and NVM are connected together and are combined on the system bus
Isomery mixing memory, isomery mixing memory have the advantages that both DRAM and NVM.
But when computer system needs to carry out cold restart (i.e. first power-off shutdown, then be switched on), if will not be in NVM
Data carry out writing back protection just directly to computing board power-off, it will cause the computer system that can not normally make after cold restart
With so the computer system where requiring consideration for how control isomery mixing memory when cold restart is completed cold restart and is realized just
It is often used.
Therefore, how to provide it is a kind of solve above-mentioned technical problem scheme be that those skilled in the art needs to solve at present
The problem of.
Invention content
The object of the present invention is to provide a kind of methods and BMC of control isomery mixing memory system cold restart, protect meter
Data when calculation machine system cold restart in isomery mixing memory, the computer system where alloing isomery mixing memory normally make
With.
In order to solve the above technical problems, the present invention provides a kind of method of control isomery mixing memory system cold restart,
Applied to the baseboard management controller BMC in computer system, including：
After the computer system sends out cold restart signal, data protection signal is generated, in order to the department of computer science
Nonvolatile memory NVM in system carries out data written-back operation after receiving the data protection signal；
After detecting that the NVM completes data written-back operation, control complex programmable logic device (CPLD) to computing board into
Power on operation is carried out after row power operation again, and is completed after the power is turned in the computing board, guiding basic input-output system BIOS
Carry out Quick Path Interconnect QPI startups；
The channel that CPU in controlling the computer system after the BIOS completes QPI startups accesses the NVM connects
It is logical, and the memory information controlled between the dynamic random access memory DRAM in the computer system and the NVM interacts,
And the guiding BIOS completes remaining Booting sequence, controls the computer system and completes cold restart.
Preferably, after control CPLD carries out power operation to computing board, the computing board is carried out in control CPLD
Before power on operation, this method further includes：
Start timing after computing board power-off, when timing time reaches preset time, generate power on operation signal,
In order to which the CPLD carries out power on operation after receiving the power on operation signal to the computing board.
Preferably, the preset time is 5s.
Preferably, the process for the channel connection that the CPU in the control computer system accesses the NVM is specific
For：
NVM described in primary scene programming logic gate array FPGA and the carry in the computer system is respectively configured
2nd FPGA；
The access path controlled between the CPU in the computer system and the first FPGA is connected to, and controls described first
Access path between FPGA and the 2nd FPGA is connected to, in order to which the CPU passes sequentially through the first FPGA and described
2nd FPGA accesses the NVM.
Preferably, the memory information includes memory size and memory address.
Preferably, between the dynamic random access memory DRAM controlled in the computer system the and NVM
Memory information interaction process be specially：
It is sent out from the memory information for obtaining DRAM in the computer system in the CPU, and by the memory information of the DRAM
It send to the 2nd FPGA；
The 2nd FPGA is obtained from the 2nd FPGA according to the memory information of the DRAM and the DRAM and institute
State the memory information of the splicing sequence of NVM correspondingly determining NVM；
The memory information of determining NVM is sent to the BIOS, completes the memory letter between the DRAM and the NVM
The interaction of breath.
Preferably, the primary scene programming logic gate array FPGA and extension being respectively configured in the computer system
The process for carrying the 2nd FPGA of the NVM is specially：
It is said according to the chip of the 2nd two chips of FPGA of NVM described in the first FPGA and carry in the computer system
Bright correspondingly write-in provides data to two chips.
Preferably, the process that the guiding basic input-output system BIOS carries out Quick Path Interconnect QPI startups is specific
For：
BIOS is guided to carry out QPI slow starts；
The BIOS progress is guided after the Restart Signal generated after completing QPI slow starts receiving the BIOS
QPI quickly starts.
Preferably, the first FPGA is specially Virtex7 2000T type FPGA, and the 2nd FPGA is specially
Virtex7 690T types FPGA.
In order to solve the above technical problems, the present invention also provides a kind of BMC of control isomery mixing memory system cold restart,
Including：
Data protection unit, for after computer system sends out cold restart signal, generating data protection signal, in order to
NVM in the computer system carries out data written-back operation after receiving the data protection signal；
Electric unit in power-off, after detecting that the NVM completes data written-back operation, control CPLD carries out computing board
Power on operation is carried out after power operation again, and is completed after the power is turned in the computing board, guiding BIOS carries out QPI startups；
Cold restart unit, for the CPU access institute in completing to control the computer system after QPI starts in the BIOS
The channel connection of NVM is stated, and the memory information controlled between the DRAM in the computer system and the NVM interacts, and drawn
It leads the BIOS and completes remaining Booting sequence, control the computer system and complete cold restart.
The present invention provides a kind of methods of control isomery mixing memory system cold restart, are applied in computer system
Baseboard management controller BMC.The application is sent out after computer system sends out cold restart signal by the BMC in computer system
Send data protection signal to NVM, NVM carries out data written-back operation after receiving data protection signal.When BMC detects NVM
After completing data written-back operation, control CPLD carries out power on operation again after carrying out power operation to computing board.
After computing board completes power on operation, BIOS is guided to carry out QPI startups by BMC, QPI is in computer system
Quick interconnecting channels between CPU and other chips.BMC completes the channel company that control CPU after QPI starts accesses NVM in BIOS
It is logical, and control the memory information between DRAM and NVM and interact, then BMC guides BIOS to complete remaining Booting sequence, until calculating
Machine system operation completes Booting sequence to the operation interface of booting, and isomery mixes when to protect computer system cold restart
Data in memory, the computer system where making isomery mixing memory can be used normally.
The present invention also provides a kind of BMC of control isomery mixing memory system cold restart, have with above-mentioned cold restart method
There is identical advantageous effect.
Description of the drawings
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to institute in the prior art and embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the present invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
Fig. 1 is a kind of flow chart of the method for control isomery mixing memory system cold restart provided by the invention；
Fig. 2 is the structural schematic diagram of the BMC of control isomery mixing memory system cold restart provided by the invention a kind of.
Specific implementation mode
Core of the invention is to provide a kind of method and BMC of control isomery mixing memory system cold restart, protects meter
Data when calculation machine system cold restart in isomery mixing memory, the computer system where alloing isomery mixing memory normally make
With.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
The every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Fig. 1 is please referred to, Fig. 1 is a kind of flow of the method for control isomery mixing memory system cold restart provided by the invention
Figure.
This method is applied to BMC (Baseboard Management Controller, substrate pipe in computer system
Manage controller), including：
Step S1：After computer system sends out cold restart signal, data protection signal is generated, in order to computer system
In nonvolatile memory NVM data written-back operation is carried out after receiving data protection signal；
Specifically, BMC is generally comprised in the mainboard or main circuit board of equipment to be monitored, is often applied to monitor and be managed
The operating status of server is managed, switching on and shutting down, the sensor states of monitoring server, access BIOS are such as carried out by out-band method
(Basic Input Output System, basic input output system) configuration or access operation system control position information etc..
After computer system sends out cold restart signal, the data that NVM does not write back in the computer system in order to prevent are lost
It loses, the application generates data protection signal by the BMC in computer system, and sends it to NVM, and NVM receives data
After protection signal, data written-back operation is carried out.
Step S2：After detecting that NVM completes data written-back operation, control complex programmable logic device (CPLD) is to computing board
Carry out power on operation again after carrying out power operation, and completed after the power is turned in computing board, guiding basic input-output system BIOS into
Row Quick Path Interconnect QPI starts；
Specifically, computer system cold restart, that is, computer system elder generation power-off shutdown is switched on again.When BMC detects that NVM is complete
After data written-back operation, CPLD (Complex Programmable Logic Device, complicated programmable logic device are controlled
Part) power operation first is carried out to computing board, power on operation then is carried out to computing board again, computer system is enable to start fortune
Row.
Computer system can enter BIOS first when starting operation.BIOS is one group and is cured to ROM in computer system
Program on (Read Only Memory, read-only memory) chip, BIOS program include the program of basic input and output, booting
The program of self-test and the program of system self-starting afterwards.
So computer system computing board complete after the power is turned on, the BMC in the computer system guide first BIOS into
Row QPI (Quick Path Interconnect, Quick Path Interconnect) starts, QPI be each chip in computer system (such as
CPU in system and other chips) between the framework that quickly interconnects, be mainly used for data transmission, moreover, passing through what QPI was completed
Data transmission has higher message transmission rate.
Step S3：The CPU after QPI starts in control computer system is completed in BIOS and accesses the channel connection of NVM, and is controlled
The memory information between dynamic random access memory DRAM and NVM in computer system processed interacts, and BIOS is guided to complete
Remaining Booting sequence, control computer system complete cold restart.
Specifically, after BIOS completes QPI startups, the CPU in BMC control computer systems is accessed in the computer system
NVM channel connection, for CPU access NVM lay the first stone.
In addition, the memory in computer system is composed using the DRAM and NVM being connected on computer system bus
Isomery mixing memory.The premise that DRAM is combined into isomery mixing memory with NVM is that DRAM interacts respective memory letter with NVM
Breath.For example, if the memory of NVM splices after DRAM, NVM just can determine that on the basis of NVM learns the memory information of DRAM
Position in memory block.
So in order to build isomery mixing memory, BMC answers the memory between DRAM and NVM in control computer system
Information exchange, so that it is determined that the position of DRAM and NVM in memory block, realizes DRAM and NVM being combined into isomery mixing memory.
Then, BMC guides BIOS to complete remaining Booting sequence, and the mark that remaining Booting sequence is completed is computer system fortune
Row is to the operation interface being switched on, so as to complete the startup of computer system.
The present invention provides a kind of methods of control isomery mixing memory system cold restart, are applied in computer system
Baseboard management controller BMC.The application is sent out after computer system sends out cold restart signal by the BMC in computer system
Send data protection signal to NVM, NVM carries out data written-back operation after receiving data protection signal.When BMC detects NVM
After completing data written-back operation, control CPLD carries out power on operation again after carrying out power operation to computing board.
After computing board completes power on operation, BIOS is guided to carry out QPI startups by BMC, QPI is in computer system
Quick interconnecting channels between CPU and other chips.BMC completes the channel company that control CPU after QPI starts accesses NVM in BIOS
It is logical, and control the memory information between DRAM and NVM and interact, then BMC guides BIOS to complete remaining Booting sequence, until calculating
Machine system operation completes Booting sequence to the operation interface of booting, and isomery mixes when to protect computer system cold restart
Data in memory, the computer system where making isomery mixing memory can be used normally.
On the basis of the above embodiments：
As a kind of preferred embodiment, after control CPLD carries out power operation to computing board, in CPLD pairs of control
Before computing board carries out power on operation, this method further includes：
Start timing after computing board power-off, when timing time reaches preset time, generates power on operation signal, so as to
Power on operation is carried out to computing board after receiving power on operation signal in CPLD.
It should be noted that here default sets in advance, it is only necessary to which setting is primary, unless according to actual conditions
Modification, otherwise need not reset.
Specifically, BMC controls CPLD and carries out power operation and power on operation to computing board.Excessively frequency is operated in order to prevent
It is numerous, start timing after computing board power-off, when timing time reaches the time set, BMC just generates power on operation signal, and
Send it to CPLD.CPLD carries out power on operation after receiving power on operation signal to computing board.
As a kind of preferred embodiment, preset time 5s.
Further, the interval time in the application between the power operation and power on operation of computing board can be but not only
It is limited to 5s, the application is not particularly limited herein.
As a kind of preferred embodiment, the process that the CPU in control computer system accesses the channel connection of NVM is specific
For：
It is respectively configured the second of the primary scene programming logic gate array FPGA in computer system and carry NVM
FPGA；
CPU in control computer system is connected to the access path between the first FPGA, and controls the first FPGA and the
Access path connection between two FPGA accesses NVM in order to which CPU passes sequentially through the first FPGA and the 2nd FPGA.
Further, the first FPGA (Field-Programmable GateArray, scene are included in computer system
Programmable gate array) and the 2nd FPGA, the NVM carries in the computer system are on the 2nd FPGA.The computer system
In CPU to access NVM, need to first pass through the first FPGA, using the 2nd FPGA.So being accessed to establish a CPU
The first FPGA and the 2nd FPGA should be respectively configured in the link of NVM.
The application united by BMC allocating computers in the first FPGA, the purpose of the first FPGA of configuration is connection CPU and the
Access path between one FPGA so that CPU is able to access that the first FPGA.In addition, BMC also configures in computer system
Two FPGA, the purpose for configuring the 2nd FPGA are similar with the configuration purpose of the first FPGA, it is therefore an objective to be connected to the first FPGA and second
Access path between FPGA so that the 2nd FPGA can be accessed in CPU by the first FPGA, and then realizes that CPU accesses NVM.
As a kind of preferred embodiment, memory information includes memory size and memory address.
Specifically, the memory information in the application may include memory size and memory address, and memory size indicates memory
Storage capacity, such as 64MB memories storage capacity be less than 128MB memories storage capacity, the memory of bigger memory size is more
Be conducive to the operation of computer system.
Memory address indicates position of the memory in memory block, and memory address generally refers to the base address of memory namely interior
The first address deposited.So, it is known that the memory address and memory size of memory can determine the tail address of memory.
Certainly, the memory information in the application can also include other information, and the application is not particularly limited herein, root
Depending on actual conditions.
As a kind of preferred embodiment, dynamic random access memory DRAM and NVM in control computer system it
Between memory information interaction process be specially：
It is sent to second from the memory information for obtaining DRAM in the computer system in CPU, and by the memory information of DRAM
FPGA；
The 2nd FPGA is obtained from the 2nd FPGA according to the splicing sequence of the memory information and DRAM of DRAM and NVM correspondingly
The memory information of determining NVM；
The memory information of determining NVM is sent to BIOS, completes the interaction of the memory information between DRAM and NVM.
Further, DRAM is exactly the memory of CPU, so BMC obtains the memory information of DRAM from CPU, i.e. DRAM's
Memory address and memory size.Again due to being mounted with NVM on the 2nd FPGA, so the memory address of DRAM and memory size are sent out
It send to the 2nd FPGA.2nd FPGA is according to the splicing sequence of DRAM and NVM and the memory address and memory size of DRAM, correspondingly
Determine the memory address and memory size of NVM.
Specifically, if NVM splicings are behind DRAM, the memory address and memory size of DRAM known to the 2nd FPGA,
It can determine that the tail address of DRAM, the tail address of DRAM are the first address of NVM, so that it is determined that positions of the NVM in memory block
It sets.If NVM splicings are before DRAM, the first address of DRAM known to the 2nd FPGA, the first address of DRAM is the tail of NVM
Location, also, the 2nd FPGA obtains the memory size of NVM, so that it is determined that the first address of NVM, the i.e. memory address of NVM.
BMC can correspondingly obtain the memory information of determining NVM from the 2nd FPGA, and will be in determining NVM
It deposits information and is sent to BIOS, to complete the interaction of the memory information between DRAM and NVM.
As a kind of preferred embodiment, the primary scene programmable gate array in computer system is respectively configured
The process of the 2nd FPGA of FPGA and carry NVM is specially：
Correspondingly according to the chip of two chips of the 2nd FPGA of the first FPGA and carry NVM in computer system explanation
Write-in provides data to two chips.
Specifically, the process that BMC configures the first FPGA and the 2nd FPGA is exactly that the process of data is written to register, write-in
Data illustrate to determine by the chip of the first FPGA and the 2nd two chips of FPGA.For example, being advised in the chip explanation of the first FPGA
It is fixed, it just can be connected to CPU and the first FPGA to the addresses 0x00 of the first FPGA write-in 0x01, then BMC configures the process of the first FPGA
0x01 as is written to the addresses 0x00 of the first FPGA.
As a kind of preferred embodiment, guiding basic input-output system BIOS carries out Quick Path Interconnect QPI startups
Process be specially：
BIOS is guided to carry out QPI slow starts；
It is quickly opened receiving BIOS after the Restart Signal generated after completing QPI slow starts BIOS being guided to carry out QPI
It is dynamic.
Further, QPI is the framework quickly interconnected between each chip in computer system, is limited by chip itself,
QPI of configuration cannot make up to faster transmission speed.So it includes slow start that BMC guiding BIOS, which carries out QPI startups,
Start with quick.Slow start refers to configuration QPI and promotes its transmission speed to level at a slow speed that it refers at a slow speed quickly to start
QPI is configured on the basis of startup again, so that its transmission speed is promoted horizontal to high speed.
Specifically, BMC guides BIOS to carry out QPI slow starts.BIOS is generated after completing QPI slow starts restarts letter
Number, and Restart Signal is sent to BMC.BMC guides BIOS progress QPI quickly to start after receiving Restart Signal.
As a kind of preferred embodiment, the first FPGA is specially Virtex7 2000T type FPGA, and the 2nd FPGA is specially
Virtex7 690T types FPGA.
Specifically, Virtex72000T can be selected but be not limited only to the model of the first FPGA in the application, and second
The model of FPGA can be selected but be not limited only to Virtex7 690T.As for the concrete model of the first FPGA and the 2nd FPGA, originally
Application is not particularly limited herein.
Fig. 2 is please referred to, Fig. 2 is the structure of the BMC of control isomery mixing memory system cold restart provided by the invention a kind of
Schematic diagram, the BMC include：
Data protection unit 1, for after computer system sends out cold restart signal, generating data protection signal, so as to
NVM in computer system carries out data written-back operation after receiving data protection signal；
Electric unit 2 in power-off, after detecting that NVM completes data written-back operation, control CPLD breaks to computing board
Power on operation is carried out after electrically operated again, and is completed after the power is turned in computing board, guiding BIOS carries out QPI startups；
Cold restart unit 3 accesses the channel of NVM for completing the CPU after QPI starts in control computer system in BIOS
Connection, and the memory information between the DRAM in control computer system and NVM interacts, and BIOS is guided to complete remaining startup stream
Journey, control computer system complete cold restart.
The introduction of BMC provided by the present application please refers to above method embodiment, and details are not described herein by the application.
Each embodiment is described by the way of progressive in this specification, the highlights of each of the examples are with other
The difference of embodiment, just to refer each other for identical similar portion between each embodiment.For device disclosed in embodiment
For, since it is corresponded to the methods disclosed in the examples, so description is fairly simple, related place is said referring to method part
It is bright.
It should also be noted that, in the present specification, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only that
A little elements, but also include other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or apparatus that includes the element.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest range caused.
Claims (10)
1. a kind of method of control isomery mixing memory system cold restart, the baseboard management controller being applied in computer system
BMC, which is characterized in that including：
After the computer system sends out cold restart signal, data protection signal is generated, in order in the computer system
Nonvolatile memory NVM data written-back operation is carried out after receiving the data protection signal；
After detecting that the NVM completes data written-back operation, control complex programmable logic device (CPLD) breaks to computing board
Power on operation is carried out after electrically operated again, and is completed after the power is turned in the computing board, guiding basic input-output system BIOS carries out
Quick Path Interconnect QPI starts；
The channel that CPU in controlling the computer system after the BIOS completes QPI startups accesses the NVM is connected to, and
The memory information controlled between the dynamic random access memory DRAM in the computer system and the NVM interacts, and draws
It leads the BIOS and completes remaining Booting sequence, control the computer system and complete cold restart.
2. the method for control isomery mixing memory system cold restart as described in claim 1, which is characterized in that in control CPLD
After carrying out power operation to computing board, before control CPLD carries out power on operation to the computing board, this method further includes：
Start timing after computing board power-off, when timing time reaches preset time, generates power on operation signal, so as to
Power on operation is carried out to the computing board after receiving the power on operation signal in the CPLD.
3. the method for control isomery mixing memory system cold restart as claimed in claim 2, which is characterized in that when described default
Between be 5s.
4. the method for control isomery mixing memory system cold restart as described in claim 1, which is characterized in that the control institute
State the CPU in computer system access the NVM channel connection process be specially：
It is respectively configured second of NVM described in primary scene programming logic gate array FPGA and the carry in the computer system
FPGA；
The access path controlled between the CPU in the computer system and the first FPGA is connected to, and controls the first FPGA
Access path between the 2nd FPGA is connected to, in order to which the CPU passes sequentially through the first FPGA and described second
FPGA accesses the NVM.
5. the method for control isomery mixing memory system cold restart as claimed in claim 4, which is characterized in that the memory letter
Breath includes memory size and memory address.
6. the method for control isomery mixing memory system cold restart as claimed in claim 5, which is characterized in that the control institute
It is specific to state the process that the memory information between the dynamic random access memory DRAM in computer system and the NVM interacts
For：
It is sent to from the memory information for obtaining DRAM in the computer system in the CPU, and by the memory information of the DRAM
2nd FPGA；
The 2nd FPGA is obtained from the 2nd FPGA according to the memory information of the DRAM and the DRAM and the NVM
Splicing sequence correspondingly determining NVM memory information；
The memory information of determining NVM is sent to the BIOS, completes the memory information between the DRAM and the NVM
Interaction.
7. the method for control isomery mixing memory system cold restart as claimed in claim 4, which is characterized in that described to match respectively
Set the process of the 2nd FPGA of NVM described in primary scene programming logic gate array FPGA and the carry in the computer system
Specially：
Illustrate phase according to the chip of the 2nd two chips of FPGA of NVM described in the first FPGA and carry in the computer system
Regulation data are written with answering to two chips.
8. such as the method for claim 4-7 any one of them control isomery mixing memory system cold restart, which is characterized in that institute
Stating the process for guiding basic input-output system BIOS to carry out Quick Path Interconnect QPI startups is specially：
BIOS is guided to carry out QPI slow starts；
It is fast receiving the BIOS after the Restart Signal generated after completing QPI slow starts the BIOS being guided to carry out QPI
Speed starts.
9. the method for control isomery mixing memory system cold restart as claimed in claim 8, which is characterized in that described first
FPGA is specially Virtex7 2000T types FPGA, and the 2nd FPGA is specially Virtex7 690T types FPGA.
10. a kind of BMC of control isomery mixing memory system cold restart, which is characterized in that including：
Data protection unit, for after computer system sends out cold restart signal, data protection signal being generated, in order to described
NVM in computer system carries out data written-back operation after receiving the data protection signal；
Electric unit in power-off, after detecting that the NVM completes data written-back operation, control CPLD powers off computing board
Power on operation is carried out after operation again, and is completed after the power is turned in the computing board, guiding BIOS carries out QPI startups；
Cold restart unit, described in the CPU access in controlling the computer system after the BIOS completes QPI startups
The channel of NVM is connected to, and the memory information controlled between the DRAM in the computer system and the NVM interacts, and is guided
The BIOS completes remaining Booting sequence, controls the computer system and completes cold restart.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810089557.5A CN108334422B (en) | 2018-01-30 | 2018-01-30 | Method for controlling cold restart of heterogeneous hybrid memory system and BMC |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810089557.5A CN108334422B (en) | 2018-01-30 | 2018-01-30 | Method for controlling cold restart of heterogeneous hybrid memory system and BMC |
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| CN108334422A true CN108334422A (en) | 2018-07-27 |
| CN108334422B CN108334422B (en) | 2022-02-18 |
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| CN201810089557.5A Active CN108334422B (en) | 2018-01-30 | 2018-01-30 | Method for controlling cold restart of heterogeneous hybrid memory system and BMC |
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