CN108287670A - The method and BMC of data are protected when a kind of system closedown - Google Patents
The method and BMC of data are protected when a kind of system closedown Download PDFInfo
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- CN108287670A CN108287670A CN201810088661.2A CN201810088661A CN108287670A CN 108287670 A CN108287670 A CN 108287670A CN 201810088661 A CN201810088661 A CN 201810088661A CN 108287670 A CN108287670 A CN 108287670A
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- nvm
- data
- computer system
- fpga
- memory
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Classifications
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0614—Improving the reliability of storage systems
- G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/14—Error detection or correction of the data by redundancy in operation
- G06F11/1402—Saving, restoring, recovering or retrying
- G06F11/1415—Saving, restoring, recovering or retrying at system level
- G06F11/1438—Restarting or rejuvenating
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/065—Replication mechanisms
Abstract
The invention discloses a kind of method for protecting data when system closedown, the BMC being applied in computer system, including：When detecting the power-off operation of computer system, the CPLD in control computer system continues through power supply and is powered to computing board, and the NVM in control computer system carries out data written-back operation；Control CPLD carries out power operation to computing board after the data for receiving NVM transmissions write back completion signal.The application protects the data in NVM before computer system shutdown, and the computer system is made to can be used normally when being switched on next time.The invention also discloses the BMC that data are protected when a kind of system closedown, with above-mentioned guard method advantageous effect having the same.
Description
Technical field
The present invention relates to technical field of memory, and the method and BMC of data are protected when more particularly to a kind of system closedown.
Background technology
With the development of memory technology, and a kind of novel storage medium NVM (Non-Volatile Memory, it is non-volatile to deposit
Reservoir) gradually it is widely used.(Dynamic Random Access Memory, dynamic random are deposited with currently used DRAM
Access to memory) it compares, NVM is with data are not lost, storage density is big, quiescent dissipation is low after step-by-step access capability, power-off, dynamic
The advantages that power consumption is high and scalability is strong.But when computer system carry out power-off operation when, if not by the data in NVM into
Row protection directly powers off computing board, it will causes the computer system can not normal use when being switched on next time.
Therefore, how to provide it is a kind of solve above-mentioned technical problem scheme be that those skilled in the art needs to solve at present
The problem of.
Invention content
The object of the present invention is to provide methods and BMC that data are protected when a kind of system closedown, shut down in computer system
The preceding data in NVM are protected, and the computer system is made to can be used normally when being switched on next time.
In order to solve the above technical problems, the present invention provides a kind of method for protecting data when system closedown, it is applied to meter
Baseboard management controller BMC in calculation machine system, including：
When detecting the power-off operation of the computer system, the complex programmable controlled in the computer system is patrolled
Volume device CPLD continues through power supply and is powered to computing board, and controls the nonvolatile memory in the computer system
NVM carries out data written-back operation；
The CPLD is controlled after receiving the data that the NVM is sent and writing back completion signal to break to the computing board
It is electrically operated.
Preferably, before controlling the CPLD and carrying out power operation to the computing board, this method further includes：
The data for monitoring the NVM write back state, will be in the NVM when the NVM successfully completes data written-back operation
The storage value that preset memory locations preserve is set to default first value；
The storage value that the preset memory locations preserve is set to when the NVM is not successfully completed data written-back operation pre-
If second value, in order to which user determines that the data of the NVM write back state according to the storage value.
Preferably, this method further includes：
After the NVM is not successfully completed data written-back operation, guided when being switched on the computer system next time basic
Input-output system BIOS carries out Quick Path Interconnect QPI startups, and controls the NVM and empty itself due to being not successfully completed number
The junk data generated according to written-back operation；
The channel that CPU in controlling the computer system after the BIOS completes QPI startups accesses the NVM connects
It is logical；
After the NVM empty litters data, the dynamic random access memory DRAM in the computer system is controlled
Memory information between the NVM interacts, and the BIOS is guided to complete remaining Booting sequence, realizes the computer system
Normal startup.
Preferably, the process that the guiding basic input-output system BIOS carries out Quick Path Interconnect QPI startups is specific
For：
BIOS is guided to carry out QPI slow starts；
The BIOS progress is guided after the Restart Signal generated after completing QPI slow starts receiving the BIOS
QPI quickly starts.
Preferably, the process for the channel connection that the CPU in the control computer system accesses the NVM is specific
For：
NVM described in primary scene programming logic gate array FPGA and the carry in the computer system is respectively configured
2nd FPGA；
The access path controlled between the CPU in the computer system and the first FPGA is connected to, and controls described first
Access path between FPGA and the 2nd FPGA is connected to, in order to which the CPU passes sequentially through the first FPGA and described
2nd FPGA accesses the NVM.
Preferably, the primary scene programming logic gate array FPGA and extension being respectively configured in the computer system
The process for carrying the 2nd FPGA of the NVM is specially：
It is said according to the chip of the 2nd two chips of FPGA of NVM described in the first FPGA and carry in the computer system
Bright correspondingly write-in provides data to two chips.
Preferably, the memory information includes memory size and memory address.
Preferably, between the dynamic random access memory DRAM controlled in the computer system the and NVM
Memory information interaction process be specially：
It is sent out from the memory information for obtaining DRAM in the computer system in the CPU, and by the memory information of the DRAM
It send to the 2nd FPGA；
The 2nd FPGA is obtained from the 2nd FPGA according to the memory information of the DRAM and the DRAM and institute
State the memory information of the splicing sequence of NVM correspondingly determining NVM；
The memory information of determining NVM is sent to the BIOS, completes the memory letter between the DRAM and the NVM
The interaction of breath.
Preferably, the first FPGA is specially Virtex7 2000T type FPGA, and the 2nd FPGA is specially
Virtex7 690T types FPGA.
In order to solve the above technical problems, the present invention also provides the BMC that data are protected when a kind of system closedown, including：
Data protection unit, for when detecting the power-off operation of computer system, controlling in the computer system
CPLD continue through power supply computing board be powered, and control the NVM in the computer system and carry out data and write back behaviour
Make；
Power-off unit, for controlling the CPLD to institute after receiving the data that the NVM is sent and writing back completion signal
It states computing board and carries out power operation.
The present invention provides a kind of method for protecting data when system closedown, the BMC being applied in computer system, packet
It includes：When detecting the power-off operation of computer system, the CPLD in control computer system continues through power supply to computing board
It is powered, and the NVM in control computer system carries out data written-back operation；It has been write back in the data for receiving NVM transmissions
Power operation is carried out to computing board at CPLD is controlled after signal.
The application detects whether computer system carries out power-off operation by BMC, when the shutdown for detecting computer system
When operation, control CPLD continues through power supply and is powered to computing board, to realize that control NVM carries out data written-back operation.
When NVM is when completing data written-back operation, generation data, which write back, to be completed signal and sends it to BMC, and number is being received by BMC
Power operation is carried out to computing board according to control CPLD after writing back completion signal, to preceding in NVM in computer system shutdown
Data are protected, and the computer system is made to can be used normally when being switched on next time.
The present invention also provides the BMC for protecting data when a kind of system closedown, and above-mentioned guard method is having the same has
Beneficial effect.
Description of the drawings
It to describe the technical solutions in the embodiments of the present invention more clearly, below will be to institute in the prior art and embodiment
Attached drawing to be used is needed to be briefly described, it should be apparent that, the accompanying drawings in the following description is only some implementations of the present invention
Example, for those of ordinary skill in the art, without creative efforts, can also obtain according to these attached drawings
Obtain other attached drawings.
The flow chart of the method for protection data when Fig. 1 is a kind of system closedown provided by the invention；
The structural schematic diagram of the BMC of protection data when Fig. 2 is a kind of system closedown provided by the invention.
Specific implementation mode
Core of the invention protects the method and BMC of data when being to provide a kind of system closedown, shut down in computer system
The preceding data in NVM are protected, and the computer system is made to can be used normally when being switched on next time.
In order to make the object, technical scheme and advantages of the embodiment of the invention clearer, below in conjunction with the embodiment of the present invention
In attached drawing, technical scheme in the embodiment of the invention is clearly and completely described, it is clear that described embodiment is
A part of the embodiment of the present invention, instead of all the embodiments.Based on the embodiments of the present invention, those of ordinary skill in the art
The every other embodiment obtained without making creative work, shall fall within the protection scope of the present invention.
Fig. 1 is please referred to, the flow chart of the method for protection data when Fig. 1 is a kind of system closedown provided by the invention.
This method is applied to baseboard management controller BMC (the Baseboard Management in computer system
Controller, baseboard management controller), including：
Step S1：When detecting the power-off operation of computer system, the complex programmable in control computer system is patrolled
Volume device CPLD continues through power supply and is powered to computing board, and the nonvolatile memory NVM in control computer system
Carry out data written-back operation；
Specifically, BMC is generally comprised in the mainboard or main circuit board of equipment to be monitored, is often applied to monitor and be managed
The operating status of server is managed, switching on and shutting down, the sensor states of monitoring server, access BIOS are such as carried out by out-band method
(Basic Input Output System, basic input output system) configuration or access operation system control position information etc..
When BMC detects the power-off operation of computer system, NVM does not write back in the computer system in order to prevent number
According to loss, the application by CPLD in BMC control computer systems (Complex Programmable Logic Device,
Complex Programmable Logic Devices) it continues through power supply computing board is powered, at the same time, in control computer system
NVM carries out data written-back operation.
More specifically, when BMC detects the power-off operation of computer system, BMC generates power supply signal and data protection
Signal, and power supply signal is sent to CPLD, data protection signal is sent to NVM.CPLD is to receive power supply signal subsequent
Continuous control power supply is powered computing board, and NVM carries out data written-back operation after receiving data protection signal.
Step S2：Control CPLD carries out power-off behaviour to computing board after the data for receiving NVM transmissions write back completion signal
Make.
Specifically, generation data write back and complete signal after NVM completes data written-back operation, and send it to BMC.
BMC control CPLD after receiving data and writing back completion signal carry out power operation to computing board.More specifically, when BMC is received
Power-off signal is generated when writing back completion signal to data, and sends it to CPLD.CPLD is after receiving power-off signal to meter
It calculates plate and carries out power operation, to be protected to the data in NVM before computer system shutdown, the computer system is made to exist
It can be used normally when booting next time.
The present invention provides a kind of method for protecting data when system closedown, the BMC being applied in computer system, packet
It includes：When detecting the power-off operation of computer system, the CPLD in control computer system continues through power supply to computing board
It is powered, and the NVM in control computer system carries out data written-back operation；It has been write back in the data for receiving NVM transmissions
Power operation is carried out to computing board at CPLD is controlled after signal.
The application detects whether computer system carries out power-off operation by BMC, when the shutdown for detecting computer system
When operation, control CPLD continues through power supply and is powered to computing board, to realize that control NVM carries out data written-back operation.
When NVM is when completing data written-back operation, generation data, which write back, to be completed signal and sends it to BMC, and number is being received by BMC
Power operation is carried out to computing board according to control CPLD after writing back completion signal, to preceding in NVM in computer system shutdown
Data are protected, and the computer system is made to can be used normally when being switched on next time.
On the basis of the above embodiments：
As a kind of preferred embodiment, before control CPLD carries out power operation to computing board, this method further includes：
The data of monitoring NVM write back state, when NVM successfully completes data written-back operation by preset memory locations in NVM
The storage value of preservation is set to default first value；
The storage value that preset memory locations preserve is set to default second when NVM is not successfully completed data written-back operation
Value, in order to which user determines that the data of NVM write back state according to storage value.
It should be noted that default in the application is set in advance, it is only necessary to which setting is primary, unless according to reality
Situation needs to change, and otherwise need not reset.
Specifically, it is contemplated that NVM is during data written-back operation it is possible that mistake, leads to data written-back operation
Failure.Therefore, it includes successfully writing back state and writing back state not successfully that the data of NVM, which write back state,.The application is monitored by BMC
The data of NVM write back state, and when NVM successfully completes data written-back operation, the storage location being set in advance in NVM is preserved
Storage value be set to the first value set；When NVM is not successfully completed data written-back operation, the storage that will be set in NVM
The storage value that position preserves is set to the second value set.
As it can be seen that when the storage value that the storage location set in NVM preserves is the first value, illustrate that NVM successfully completes number
According to written-back operation；When the storage value that the storage location set in NVM preserves is second value, illustrate that NVM is not successfully completed number
According to written-back operation, so that user determines that the data of NVM write back state according to storage value.
As a kind of preferred embodiment, this method further includes：
After NVM is not successfully completed data written-back operation, basic input and output are guided in computer system booting next time
System bios carry out Quick Path Interconnect QPI startups, and control NVM and empty itself due to being not successfully completed the production of data written-back operation
Raw junk data；
The channel connection that the CPU after QPI starts in control computer system accesses NVM is completed in BIOS；
After NVM empty litter data, between the dynamic random access memory DRAM and NVM in control computer system
Memory information interaction, and BIOS is guided to complete remaining Booting sequence, realizes the normal startup of computer system.
It is known that compared with DRAM, NVM does not lose with data after step-by-step access capability, power-off, storage density is big, static
Low in energy consumption, the advantages that dynamic power consumption is high and scalability is strong.But the slow one or several orders of magnitude of the write delay of NVM ratio DRAM,
It is written number and is also restricted, so, in order to meet the real-time demand of computer system, DRAM and NVM is connected to together
Isomery mixing memory is combined on system bus, isomery mixing memory has the advantages of both DRAM and NVM.
It is understood that if NVM is not successfully completed data written-back operation, the computer system can be caused to occur different
Often, next time be switched on after can not normal use, it is therefore desirable to control the computer system complete abnormal restoring, realization normally make
With.
Specifically, computer system can enter BIOS first in booting operation next time.BIOS is one group and is cured to meter
Program in calculation machine system on ROM (Read Only Memory, read-only memory) chip, BIOS program are defeated including inputting substantially
The program of self-test and the program of system self-starting after the program that goes out, booting.
After computer system power-on, the BMC in the computer system guides BIOS to carry out QPI (Quick Path first
Interconnect, Quick Path Interconnect) start, QPI be each chip in computer system (such as CPU in system and other
Chip) between the framework that quickly interconnects, be mainly used for data transmission, moreover, having by the data transmission that QPI is completed higher
Message transmission rate.
In addition, in computer system power-on, abnormal conditions can also be fed back to user by BMC, be selected by users
Operation, in order to enter computer system abnormal restoring process.
At the same time, it is contemplated that NVM is not successfully completed data written-back operation, and the data not write back can become junk data.
For the normal use of computer system, control NVM empties the junk data of itself generation.It is emptied more specifically, BMC can be generated
Junk data instructs, and sends it to NVM.After NVM receives empty litter data command, the rubbish of itself generation can be emptied
Rubbish data.
After BIOS completes QPI startups, the CPU in BMC meeting control computer systems accesses the NVM in the computer system
Channel connection, for CPU access NVM lay the first stone.
In addition, the memory in computer system is composed using the DRAM and NVM being connected on computer system bus
Isomery mixing memory.The premise that DRAM is combined into isomery mixing memory with NVM is that DRAM interacts respective memory letter with NVM
Breath.For example, if the memory of NVM splices after DRAM, NVM just can determine that on the basis of NVM learns the memory information of DRAM
Position in memory block.
So in order to build isomery mixing memory, after NVM empty litter data, BMC is answered in control computer system
Memory information between DRAM and NVM interacts, so that it is determined that the position of DRAM and NVM in memory block, is realized DRAM and NVM
It is combined into isomery mixing memory.
Then, BMC guides BIOS to complete remaining Booting sequence, and the mark that remaining Booting sequence is completed is computer system fortune
Row is to the operation interface being switched on, so as to complete the normal startup of computer system.
As a kind of preferred embodiment, guiding basic input-output system BIOS carries out Quick Path Interconnect QPI startups
Process be specially：
BIOS is guided to carry out QPI slow starts；
It is quickly opened receiving BIOS after the Restart Signal generated after completing QPI slow starts BIOS being guided to carry out QPI
It is dynamic.
Further, QPI is the framework quickly interconnected between each chip in computer system, is limited by chip itself,
QPI of configuration cannot make up to faster transmission speed.So it includes slow start that BMC guiding BIOS, which carries out QPI startups,
Start with quick.Slow start refers to configuration QPI and promotes its transmission speed to level at a slow speed that it refers at a slow speed quickly to start
QPI is configured on the basis of startup again, so that its transmission speed is promoted horizontal to high speed.
Specifically, BMC guides BIOS to carry out QPI slow starts.BIOS is generated after completing QPI slow starts restarts letter
Number, and Restart Signal is sent to BMC.BMC guides BIOS progress QPI quickly to start after receiving Restart Signal.
As a kind of preferred embodiment, the process that the CPU in control computer system accesses the channel connection of NVM is specific
For：
It is respectively configured the second of the primary scene programming logic gate array FPGA in computer system and carry NVM
FPGA；
CPU in control computer system is connected to the access path between the first FPGA, and controls the first FPGA and the
Access path connection between two FPGA accesses NVM in order to which CPU passes sequentially through the first FPGA and the 2nd FPGA.
Further, the first FPGA (Field-Programmable Gate Array, scene are included in computer system
Programmable gate array) and the 2nd FPGA, the NVM carries in the computer system are on the 2nd FPGA.The computer system
In CPU to access NVM, need to first pass through the first FPGA, using the 2nd FPGA.So being accessed to establish a CPU
The first FPGA and the 2nd FPGA should be respectively configured in the link of NVM.
The application united by BMC allocating computers in the first FPGA, the purpose of the first FPGA of configuration is connection CPU and the
Access path between one FPGA so that CPU is able to access that the first FPGA.In addition, BMC also configures in computer system
Two FPGA, the purpose for configuring the 2nd FPGA are similar with the configuration purpose of the first FPGA, it is therefore an objective to be connected to the first FPGA and second
Access path between FPGA so that the 2nd FPGA can be accessed in CPU by the first FPGA, and then realizes that CPU accesses NVM.
As a kind of preferred embodiment, the primary scene programmable gate array in computer system is respectively configured
The process of the 2nd FPGA of FPGA and carry NVM is specially：
Correspondingly according to the chip of two chips of the 2nd FPGA of the first FPGA and carry NVM in computer system explanation
Write-in provides data to two chips.
Specifically, the process that BMC configures the first FPGA and the 2nd FPGA is exactly that the process of data is written to register, write-in
Data illustrate to determine by the chip of the first FPGA and the 2nd two chips of FPGA.For example, being advised in the chip explanation of the first FPGA
It is fixed, it just can be connected to CPU and the first FPGA to the addresses 0x00 of the first FPGA write-in 0x01, then BMC configures the process of the first FPGA
0x01 as is written to the addresses 0x00 of the first FPGA.
As a kind of preferred embodiment, memory information includes memory size and memory address.
Specifically, the memory information in the application may include memory size and memory address, and memory size indicates memory
Storage capacity, such as 64MB memories storage capacity be less than 128MB memories storage capacity, the memory of bigger memory size is more
Be conducive to the operation of computer system.
Memory address indicates position of the memory in memory block, and memory address generally refers to the base address of memory namely interior
The first address deposited.So, it is known that the memory address and memory size of memory can determine the tail address of memory.
Certainly, the memory information in the application can also include other information, and the application is not particularly limited herein, root
Depending on actual conditions.
As a kind of preferred embodiment, dynamic random access memory DRAM and NVM in control computer system it
Between memory information interaction process be specially：
It is sent to second from the memory information for obtaining DRAM in the computer system in CPU, and by the memory information of DRAM
FPGA；
The 2nd FPGA is obtained from the 2nd FPGA according to the splicing sequence of the memory information and DRAM of DRAM and NVM correspondingly
The memory information of determining NVM；
The memory information of determining NVM is sent to BIOS, completes the interaction of the memory information between DRAM and NVM.
Further, DRAM is exactly the memory of CPU, so BMC obtains the memory information of DRAM from CPU, i.e. DRAM's
Memory address and memory size.Again due to being mounted with NVM on the 2nd FPGA, so the memory address of DRAM and memory size are sent out
It send to the 2nd FPGA.2nd FPGA is according to the splicing sequence of DRAM and NVM and the memory address and memory size of DRAM, correspondingly
Determine the memory address and memory size of NVM.
Specifically, if NVM splicings are behind DRAM, the memory address and memory size of DRAM known to the 2nd FPGA,
It can determine that the tail address of DRAM, the tail address of DRAM are the first address of NVM, so that it is determined that positions of the NVM in memory block
It sets.If NVM splicings are before DRAM, the first address of DRAM known to the 2nd FPGA, the first address of DRAM is the tail of NVM
Location, also, the 2nd FPGA obtains the memory size of NVM, so that it is determined that the first address of NVM, the i.e. memory address of NVM.
BMC can correspondingly obtain the memory information of determining NVM from the 2nd FPGA, and will be in determining NVM
It deposits information and is sent to BIOS, to complete the interaction of the memory information between DRAM and NVM.
As a kind of preferred embodiment, the first FPGA is specially Virtex7 2000T type FPGA, and the 2nd FPGA is specially
Virtex7 690T types FPGA.
Specifically, Virtex7 2000T can be selected but be not limited only to the model of the first FPGA in the application, and second
The model of FPGA can be selected but be not limited only to Virtex7 690T.As for the concrete model of the first FPGA and the 2nd FPGA, originally
Application is not particularly limited herein.
Fig. 2 is please referred to, the structural schematic diagram of the BMC of protection data when Fig. 2 is a kind of system closedown provided by the invention should
BMC includes：
Data protection unit 1, for when detecting the power-off operation of computer system, in control computer system
CPLD continues through power supply and is powered to computing board, and the NVM in control computer system carries out data written-back operation；
Power-off unit 2 carries out computing board for control CPLD after writing back completion signal in the data for receiving NVM transmissions
Power operation.
The introduction of BMC provided by the present application please refers to above method embodiment, and details are not described herein by the application.
It should also be noted that, in the present specification, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only that
A little elements, but also include other elements that are not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or apparatus that includes the element.
The foregoing description of the disclosed embodiments enables those skilled in the art to implement or use the present invention.
Various modifications to these embodiments will be apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the present invention.Therefore, of the invention
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest range caused.
Claims (10)
1. a kind of method for protecting data when system closedown, the baseboard management controller BMC being applied in computer system is special
Sign is, including：
When detecting the power-off operation of the computer system, the complicated programmable logic device in the computer system is controlled
Part CPLD continues through power supply and is powered to computing board, and controls the nonvolatile memory NVM in the computer system
Carry out data written-back operation；
The CPLD is controlled after receiving the data that the NVM is sent and writing back completion signal, and power-off behaviour is carried out to the computing board
Make.
The method for protecting data when 2. the system as claimed in claim 1 is shut down, which is characterized in that controlling the CPLD to institute
Before stating computing board progress power operation, this method further includes：
The data for monitoring the NVM write back state, will be preset in the NVM when the NVM successfully completes data written-back operation
The storage value that storage location preserves is set to default first value；
The storage value that the preset memory locations preserve is set to default when the NVM is not successfully completed data written-back operation
Two-value, in order to which user determines that the data of the NVM write back state according to the storage value.
3. the method for protecting data when system closedown as claimed in claim 2, which is characterized in that this method further includes：
After the NVM is not successfully completed data written-back operation, basic input is guided when being switched on the computer system next time
Output system BIOS carries out Quick Path Interconnect QPI startups, and controls the NVM and empty itself and write due to being not successfully completed data
Return the junk data that operation generates；
The channel that CPU in controlling the computer system after the BIOS completes QPI startups accesses the NVM is connected to；
After the NVM empty litters data, the dynamic random access memory DRAM in the computer system and institute are controlled
The memory information interaction between NVM is stated, and the BIOS is guided to complete remaining Booting sequence, is realizing the computer system just
Often start.
4. the method for protecting data when system closedown as claimed in claim 3, which is characterized in that the guiding inputs defeated substantially
Go out system bios carry out Quick Path Interconnect QPI startups process be specially：
BIOS is guided to carry out QPI slow starts；
It is fast receiving the BIOS after the Restart Signal generated after completing QPI slow starts the BIOS being guided to carry out QPI
Speed starts.
5. the method for protecting data when system closedown as claimed in claim 3, which is characterized in that the control computer
CPU in system access the NVM channel connection process be specially：
It is respectively configured second of NVM described in primary scene programming logic gate array FPGA and the carry in the computer system
FPGA；
The access path controlled between the CPU in the computer system and the first FPGA is connected to, and controls the first FPGA
Access path between the 2nd FPGA is connected to, in order to which the CPU passes sequentially through the first FPGA and described second
FPGA accesses the NVM.
6. the method for protecting data when system closedown as claimed in claim 5, which is characterized in that described that the meter is respectively configured
The process of the 2nd FPGA of NVM described in primary scene programming logic gate array FPGA and carry in calculation machine system is specially：
Illustrate phase according to the chip of the 2nd two chips of FPGA of NVM described in the first FPGA and carry in the computer system
Regulation data are written with answering to two chips.
7. the method for protecting data when system closedown as claimed in claim 5, which is characterized in that the memory information includes interior
Deposit capacity and memory address.
8. the method for protecting data when system closedown as claimed in claim 7, which is characterized in that the control computer
The process that the memory information between dynamic random access memory DRAM and the NVM in system interacts is specially：
It is sent to from the memory information for obtaining DRAM in the computer system in the CPU, and by the memory information of the DRAM
2nd FPGA；
The 2nd FPGA is obtained from the 2nd FPGA according to the memory information of the DRAM and the DRAM and the NVM
Splicing sequence correspondingly determining NVM memory information；
The memory information of determining NVM is sent to the BIOS, completes the memory information between the DRAM and the NVM
Interaction.
9. the method for protecting data when system closedown as claimed in claim 8, which is characterized in that the first FPGA is specially
Virtex7 2000T types FPGA, the 2nd FPGA are specially Virtex7 690T types FPGA.
10. protecting the BMC of data when a kind of system closedown, which is characterized in that including：
Data protection unit, for when detecting the power-off operation of computer system, controlling in the computer system
CPLD continues through power supply and is powered to computing board, and controls the NVM in the computer system and carry out data written-back operation；
Power-off unit, by receive the data that the NVM is sent write back complete signal after control the CPLD to based on described
It calculates plate and carries out power operation.
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