CN108287670B - Method for protecting data during system shutdown and BMC - Google Patents

Method for protecting data during system shutdown and BMC Download PDF

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CN108287670B
CN108287670B CN201810088661.2A CN201810088661A CN108287670B CN 108287670 B CN108287670 B CN 108287670B CN 201810088661 A CN201810088661 A CN 201810088661A CN 108287670 B CN108287670 B CN 108287670B
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nvm
computer system
fpga
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data
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CN108287670A (en
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王龙飞
罗刚
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Zhengzhou Yunhai Information Technology Co Ltd
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Zhengzhou Yunhai Information Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
    • G06F3/0614—Improving the reliability of storage systems
    • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1438—Restarting or rejuvenating
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
    • G06F3/065—Replication mechanisms

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Abstract

The invention discloses a method for protecting data when a system is shut down, which is applied to BMC in a computer system and comprises the following steps: when the shutdown operation of the computer system is detected, controlling a CPLD in the computer system to continue to supply power to the computing board through a power supply, and controlling an NVM in the computer system to perform data write-back operation; and after receiving a data write-back completion signal sent by the NVM, controlling the CPLD to perform power-off operation on the computing board. According to the method and the device, the data in the NVM are protected before the computer system is powered off, so that the computer system can be normally used when being powered on next time. The invention also discloses a BMC for protecting data when the system is shut down, and the BMC has the same beneficial effect as the protection method.

Description

Method for protecting data during system shutdown and BMC
Technical Field
The invention relates to the technical field of storage, in particular to a method for protecting data when a system is shut down and a BMC (baseboard management controller).
Background
With the development of Memory technology, a new type of Memory medium NVM (Non-Volatile Memory) is gradually becoming widely used. Compared with a Dynamic Random Access Memory (DRAM) which is commonly used at present, the NVM has the advantages of bit-wise Access capability, no data loss after power failure, high storage density, low static power consumption, high Dynamic power consumption, strong expandability and the like. However, when the computer system is powered off, the computer board is directly powered off without protecting the data in the NVM, which may cause the computer system to be unable to be used normally when the computer system is powered on next time.
Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a method for protecting data when a system is powered off and a BMC (baseboard management controller), which are used for protecting the data in an NVM (non-volatile memory) before the computer system is powered off so that the computer system can be normally used when being powered on next time.
In order to solve the above technical problem, the present invention provides a method for protecting data when a system is powered off, which is applied to a baseboard management controller BMC in a computer system, and comprises:
when the shutdown operation of the computer system is detected, controlling a Complex Programmable Logic Device (CPLD) in the computer system to continue to supply power to a computing board through a power supply, and controlling a nonvolatile memory (NVM) in the computer system to perform data write-back operation;
and after receiving a data write-back completion signal sent by the NVM, controlling the CPLD to perform power-off operation on the computing board.
Preferably, before controlling the CPLD to perform the power-off operation on the computing board, the method further includes:
monitoring the data write-back state of the NVM, and setting a stored value stored in a preset storage position in the NVM as a preset first value when the NVM successfully completes the data write-back operation;
and when the NVM does not successfully finish the data write-back operation, setting the stored value stored in the preset storage position to be a preset second value so that a user can determine the data write-back state of the NVM according to the stored value.
Preferably, the method further comprises:
after the NVM does not successfully finish the data write-back operation, guiding a Basic Input Output System (BIOS) to carry out quick channel interconnection (QPI) starting when the computer system is started next time, and controlling the NVM to empty garbage data generated by the NVM due to the unsuccessful completion of the data write-back operation;
controlling a channel communication of a CPU in the computer system to access the NVM after the BIOS completes QPI startup;
and after the NVM clears the garbage data, controlling the memory information interaction between a Dynamic Random Access Memory (DRAM) in the computer system and the NVM, and guiding the BIOS to complete the residual starting process so as to realize the normal starting of the computer system.
Preferably, the process of booting the BIOS to perform QPI boot is specifically:
booting the BIOS to perform QPI slow start;
and after a restart signal generated after the BIOS completes QPI slow start is received, the BIOS is guided to carry out QPI fast start.
Preferably, the process of controlling the channel communication of the CPU in the computer system accessing the NVM specifically includes:
respectively configuring a first Field Programmable Gate Array (FPGA) in the computer system and a second FPGA for mounting the NVM;
controlling communication of access channels between a CPU and a first FPGA in the computer system, and controlling communication of the access channels between the first FPGA and a second FPGA so that the CPU accesses the NVM sequentially through the first FPGA and the second FPGA.
Preferably, the process of respectively configuring the first field programmable gate array FPGA in the computer system and the second FPGA mounted on the NVM specifically includes:
and correspondingly writing specified data into the two chips according to the chip descriptions of the first FPGA and the second FPGA mounted on the NVM in the computer system.
Preferably, the memory information includes memory capacity and memory address.
Preferably, the process of controlling the memory information interaction between the DRAM and the NVM in the computer system specifically includes:
acquiring the memory information of a DRAM in the computer system from the CPU, and sending the memory information of the DRAM to the second FPGA;
obtaining the memory information of the NVM correspondingly determined by the second FPGA according to the memory information of the DRAM and the splicing sequence of the DRAM and the NVM from the second FPGA;
and sending the determined memory information of the NVM to the BIOS to complete the interaction of the memory information between the DRAM and the NVM.
Preferably, the first FPGA is a Virtex 72000T type FPGA, and the second FPGA is a Virtex7690T type FPGA.
In order to solve the above technical problem, the present invention further provides a BMC for protecting data when a system is powered off, including:
the data protection unit is used for controlling the CPLD in the computer system to continuously supply power to the computing board through a power supply and controlling the NVM in the computer system to perform data write-back operation when the shutdown operation of the computer system is detected;
and the power-off unit is used for controlling the CPLD to perform power-off operation on the computing board after receiving the data write-back completion signal sent by the NVM.
The invention provides a method for protecting data when a system is shut down, which is applied to BMC in a computer system and comprises the following steps: when the shutdown operation of the computer system is detected, controlling a CPLD in the computer system to continue to supply power to the computing board through a power supply, and controlling an NVM in the computer system to perform data write-back operation; and after receiving a data write-back completion signal sent by the NVM, controlling the CPLD to perform power-off operation on the computing board.
According to the method and the device, whether the computer system is powered off or not is detected through the BMC, and when the computer system is detected to be powered off, the CPLD is controlled to continue to supply power to the computing board through the power supply, so that the NVM is controlled to perform data write-back operation. When the NVM finishes the data write-back operation, generating a data write-back completion signal and sending the data write-back completion signal to the BMC, and controlling the CPLD to perform power-off operation on the computing board by the BMC after receiving the data write-back completion signal, so that the data in the NVM is protected before the computer system is powered off, and the computer system can be normally used when being powered on next time.
The invention also provides a BMC for protecting data when the system is shut down, and the BMC has the same beneficial effect as the protection method.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.
FIG. 1 is a flow chart of a method for protecting data when a system is powered off according to the present invention;
fig. 2 is a schematic structural diagram of a BMC for protecting data when a system is powered off according to the present invention.
Detailed Description
The core of the invention is to provide a method for protecting data when a system is powered off and a BMC, which can protect the data in the NVM before the computer system is powered off, so that the computer system can be normally used when being powered on next time.
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Referring to fig. 1, fig. 1 is a flowchart illustrating a method for protecting data when a system is powered off according to the present invention.
The method is applied to a Baseboard Management Controller (BMC) in a computer system, and comprises the following steps:
step S1: when the shutdown operation of the computer system is detected, controlling a Complex Programmable Logic Device (CPLD) in the computer system to continue to supply power to the computing board through a power supply, and controlling a nonvolatile memory (NVM) in the computer system to perform data write-back operation;
specifically, the BMC is usually included in a main board or a main circuit board of a device to be monitored, and is often used to monitor and manage an operation state of a server, such as turning on and off in an out-of-band manner, monitoring a sensor state of the server, accessing a BIOS (Basic Input Output System) configuration or accessing console information of an operating System, and the like.
When the BMC detects shutdown operation of the computer system, in order to prevent data loss of the non-written-back NVM in the computer system, the BMC controls a Complex Programmable Logic Device (CPLD) in the computer system to continue to supply power to the computing board through a power supply, and at the same time, controls the NVM in the computer system to perform data write-back operation.
More specifically, when the BMC detects a shutdown operation of the computer system, the BMC generates a power supply signal and a data protection signal, and transmits the power supply signal to the CPLD and the data protection signal to the NVM. And the CPLD continues to control the power supply to supply power to the computing board after receiving the power supply signal, and the NVM performs data write-back operation after receiving the data protection signal.
Step S2: and after receiving a data write-back completion signal sent by the NVM, controlling the CPLD to perform power-off operation on the computing board.
Specifically, a data write-back completion signal is generated after the NVM completes the data write-back operation and sent to the BMC. And the BMC controls the CPLD to perform power-off operation on the computing board after receiving the data write-back completion signal. More specifically, the BMC generates a power-down signal when it receives the data write-back completion signal and transmits it to the CPLD. The CPLD performs power-off operation on the computing board after receiving the power-off signal, so that data in the NVM is protected before the computer system is powered off, and the computer system can be normally used when being powered on next time.
The invention provides a method for protecting data when a system is shut down, which is applied to BMC in a computer system and comprises the following steps: when the shutdown operation of the computer system is detected, controlling a CPLD in the computer system to continue to supply power to the computing board through a power supply, and controlling an NVM in the computer system to perform data write-back operation; and after receiving a data write-back completion signal sent by the NVM, controlling the CPLD to perform power-off operation on the computing board.
According to the method and the device, whether the computer system is powered off or not is detected through the BMC, and when the computer system is detected to be powered off, the CPLD is controlled to continue to supply power to the computing board through the power supply, so that the NVM is controlled to perform data write-back operation. When the NVM finishes the data write-back operation, generating a data write-back completion signal and sending the data write-back completion signal to the BMC, and controlling the CPLD to perform power-off operation on the computing board by the BMC after receiving the data write-back completion signal, so that the data in the NVM is protected before the computer system is powered off, and the computer system can be normally used when being powered on next time.
On the basis of the above-described embodiment:
as a preferred embodiment, before controlling the CPLD to perform the power-off operation on the computing board, the method further includes:
monitoring the data write-back state of the NVM, and setting a stored value stored in a preset storage position in the NVM as a preset first value when the NVM successfully completes the data write-back operation;
and setting the stored value stored in the preset storage position as a preset second value when the NVM does not successfully complete the data write-back operation, so that a user can determine the data write-back state of the NVM according to the stored value.
It should be noted that, the preset in the present application is set in advance, and only needs to be set once, and the preset is not required to be reset unless modified according to actual conditions.
In particular, consider that an NVM may experience errors during a data write-back operation, resulting in a data write-back operation failure. Thus, the data write-back state of the NVM includes a successful write-back state and an unsuccessful write-back state. The method comprises the steps that a BMC monitors the data write-back state of an NVM, and when the NVM successfully completes data write-back operation, a stored value stored in a preset storage position in the NVM is set to be a preset first value; and when the NVM does not successfully complete the data write-back operation, setting the stored value stored in the set storage position in the NVM to be the set second value.
Therefore, when the stored value stored in the set storage location in the NVM is the first value, it indicates that the NVM successfully completes the data write-back operation; when the stored value stored in the set storage location in the NVM is a second value, it indicates that the NVM has not successfully completed the data write-back operation, so that the user can determine the data write-back status of the NVM according to the stored value.
As a preferred embodiment, the method further comprises:
after the NVM fails to complete the data write-back operation, the BIOS is guided to perform QPI (quick Path interconnect) starting when the computer system is started next time, and the NVM is controlled to empty garbage data generated by the unsuccessful data write-back operation;
controlling the communication of a channel for accessing the NVM by a CPU in the computer system after the BIOS finishes QPI starting;
after the NVM is emptied of garbage data, the memory information interaction between the DRAM and the NVM in the computer system is controlled, and the BIOS is guided to complete the remaining boot process, so that the normal boot of the computer system is realized.
As known, compared with DRAM, NVM has the advantages of bit-wise access capability, no data loss after power-off, high storage density, low static power consumption, high dynamic power consumption, and strong scalability. However, because the writing latency of NVM is one or several orders of magnitude slower than DRAM and the number of writes is limited, to meet the real-time requirements of a computer system, DRAM and NVM are connected together on a system bus to form a heterogeneous hybrid memory, which has the advantages of both DRAM and NVM.
It can be understood that if the NVM does not complete the data write-back operation successfully, the computer system may be abnormal and cannot be used normally after the next boot, and therefore, the computer system needs to be controlled to complete the abnormal recovery to achieve normal use.
Specifically, the computer system first enters the BIOS when the computer system is powered on next time. The BIOS is a set of programs that are fixed on a ROM (Read Only Memory) chip in a computer system, and the BIOS programs include a basic input/output program, a self-test program after power-on, and a system self-starting program.
After the computer system is powered on, the BMC in the computer system first directs the BIOS to perform QPI (Quick Path Interconnect) start, where QPI is a framework for fast interconnection between chips (such as a CPU and other chips in the system) in the computer system, and is mainly used for data transmission, and data transmission completed through QPI has a higher data transmission rate.
In addition, when the computer system is started, the BMC can also feed back the abnormal condition to the user, and the user performs selection operation so as to enter the abnormal recovery process of the computer system.
Meanwhile, considering that the NVM did not successfully complete the data write-back operation, the data that was not written back may become garbage data. For normal use of the computer system, the NVM is controlled to empty itself of generated garbage data. More specifically, the BMC may generate and send a flush garbage data instruction to the NVM. When the NVM receives the command for clearing the garbage data, the NVM can clear the garbage data generated by itself.
After the BIOS finishes QPI startup, the BMC controls the channel communication of the CPU in the computer system for accessing the NVM in the computer system, and lays a foundation for the CPU to access the NVM.
In addition, the memory in the computer system adopts a heterogeneous hybrid memory formed by combining DRAM and NVM which are connected on a bus of the computer system. The premise of combining the DRAM and the NVM into a heterogeneous hybrid memory is that the DRAM and the NVM interact with each other to obtain respective memory information. For example, if the memory of the NVM is spliced to the DRAM, the location of the NVM in the memory block can only be determined based on the memory information of the DRAM that is known to the NVM.
Therefore, in order to construct the heterogeneous hybrid memory, after the NVM clears the garbage data, the BMC should control the memory information interaction between the DRAM and the NVM in the computer system, so as to determine the locations of the DRAM and the NVM in the memory blocks, thereby implementing the combination of the DRAM and the NVM into the heterogeneous hybrid memory.
Then, the BMC guides the BIOS to complete the remaining boot process, and the mark of the completion of the remaining boot process is an operation interface of the computer system from running to starting up, so that the normal boot of the computer system is completed.
As a preferred embodiment, the process of booting the BIOS to perform QPI boot is specifically as follows:
booting the BIOS to perform QPI slow start;
and after receiving a restart signal generated after the BIOS completes the QPI slow start, booting the BIOS to carry out the QPI fast start.
Further, QPI is a framework for fast interconnection between chips in a computer system, and is limited by the chips themselves, and it cannot achieve a faster transmission speed by configuring QPI once. Therefore, BMC directs BIOS to perform QPI boot including slow boot and fast boot. The slow start refers to configuring the QPI and increasing the transmission speed to a slow level, and the fast start refers to reconfiguring the QPI again on the basis of the slow start to increase the transmission speed to a high level.
Specifically, the BMC directs the BIOS to QPI slow start. And the BIOS generates a restart signal after finishing the QPI slow start and sends the restart signal to the BMC. And the BMC guides the BIOS to carry out QPI quick start after receiving the restart signal.
As a preferred embodiment, the process of controlling the channel connectivity of the CPU accessing the NVM in the computer system specifically includes:
respectively configuring a first Field Programmable Gate Array (FPGA) and a second FPGA for mounting the NVM in the computer system;
and controlling the communication of an access channel between a CPU (central processing unit) and the first FPGA in the computer system and controlling the communication of the access channel between the first FPGA and the second FPGA so that the CPU accesses the NVM sequentially through the first FPGA and the second FPGA.
Further, the computer system includes a first FPGA (Field-Programmable Gate Array) and a second FPGA, and the NVM in the computer system is mounted on the second FPGA. When a CPU in the computer system wants to access the NVM, the CPU needs to pass through a first FPGA and then a second FPGA. Therefore, in order to establish a link for the CPU to access the NVM, a first FPGA and a second FPGA should be configured separately.
According to the method and the system, the BMC configures the first FPGA in the computer system, and the purpose of configuring the first FPGA is to communicate an access channel between the CPU and the first FPGA, so that the CPU can access the first FPGA. In addition, the BMC also configures a second FPGA in the computer system, the purpose of configuring the second FPGA is similar to that of configuring the first FPGA, and the purpose is to communicate an access channel between the first FPGA and the second FPGA, so that the CPU can access the second FPGA through the first FPGA, and further the CPU accesses the NVM.
As a preferred embodiment, the process of respectively configuring the first field programmable gate array FPGA and the second FPGA mounted on the NVM in the computer system specifically includes:
and writing specified data into the two chips correspondingly according to the chip descriptions of the two chips of the first FPGA and the second FPGA mounted with the NVM in the computer system.
Specifically, the process of configuring the first FPGA and the second FPGA by the BMC is a process of writing data into the register, and the written data is determined by chip descriptions of two chips of the first FPGA and the second FPGA. For example, the chip description of the first FPGA specifies that writing 0x01 to the 0x00 address of the first FPGA can communicate the CPU with the first FPGA, and the process of the BMC configuring the first FPGA is to write 0x01 to the 0x00 address of the first FPGA.
In a preferred embodiment, the memory information includes memory capacity and memory address.
Specifically, the memory information in the present application may include a memory capacity and a memory address, where the memory capacity represents a storage capacity of the memory, for example, the storage capacity of the 64MB memory is smaller than that of the 128MB memory, and the larger the memory capacity is, the more favorable the operation of the computer system is.
The memory address indicates the location of the memory in the memory block, and the memory address generally refers to the base address of the memory, i.e., the first address of the memory. Therefore, knowing the memory address and memory capacity of the memory, the tail address of the memory can be determined.
Of course, the memory information in the present application may also include other information, and the present application is not particularly limited herein, depending on the actual situation.
As a preferred embodiment, the process of controlling the memory information interaction between the DRAM and the NVM in the computer system specifically includes:
acquiring the memory information of the DRAM in the computer system from the CPU, and sending the memory information of the DRAM to the second FPGA;
obtaining the memory information of the NVM correspondingly determined by the second FPGA according to the memory information of the DRAM and the splicing sequence of the DRAM and the NVM from the second FPGA;
and sending the determined memory information of the NVM to the BIOS to complete the interaction of the memory information between the DRAM and the NVM.
Further, the DRAM is the memory of the CPU, so the BMC obtains the memory information of the DRAM, i.e., the memory address and the memory capacity of the DRAM, from the CPU. And because the NVM is hung on the second FPGA, the memory address and the memory capacity of the DRAM are sent to the second FPGA. And the second FPGA correspondingly determines the memory address and the memory capacity of the NVM according to the splicing sequence of the DRAM and the NVM and the memory address and the memory capacity of the DRAM.
Specifically, if the NVM is spliced behind the DRAM, the second FPGA, knowing the memory address and memory capacity of the DRAM, can determine the tail address of the DRAM, which is the first address of the NVM, and thus determine the location of the NVM in the memory block. If the NVM is spliced in front of the DRAM, the second FPGA knows the first address of the DRAM, the first address of the DRAM is the tail address of the NVM, and the second FPGA acquires the memory capacity of the NVM so as to determine the first address of the NVM, namely the memory address of the NVM.
The BMC can correspondingly acquire the determined memory information of the NVM from the second FPGA and send the determined memory information of the NVM to the BIOS, so that the interaction of the memory information between the DRAM and the NVM is completed.
As a preferred embodiment, the first FPGA is a Virtex 72000T FPGA, and the second FPGA is a Virtex7690T FPGA.
Specifically, the model of the first FPGA in the present application may be selected from, but not limited to, Virtex 72000T, and the model of the second FPGA may be selected from, but not limited to, Virtex 7690T. As to the specific models of the first FPGA and the second FPGA, the present application is not particularly limited.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a BMC for protecting data when a system is powered off, where the BMC includes:
the data protection unit 1 is used for controlling a CPLD in the computer system to continuously supply power to the computing board through a power supply and controlling an NVM in the computer system to perform data write-back operation when the shutdown operation of the computer system is detected;
and the power-off unit 2 is used for controlling the CPLD to perform power-off operation on the computing board after receiving the data write-back completion signal sent by the NVM.
For the BMC introduction provided in the present application, reference is made to the above method embodiments, which are not repeated herein.
It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims (9)

1. A method for protecting data when a system is shut down is applied to a Baseboard Management Controller (BMC) in a computer system, and is characterized by comprising the following steps:
when the shutdown operation of the computer system is detected, controlling a Complex Programmable Logic Device (CPLD) in the computer system to continue to supply power to a computing board through a power supply, and controlling a nonvolatile memory (NVM) in the computer system to perform data write-back operation;
after receiving a data write-back completion signal sent by the NVM, controlling the CPLD to perform power-off operation on the computing board;
the method further comprises the following steps:
after the NVM does not successfully finish the data write-back operation, guiding a Basic Input Output System (BIOS) to carry out quick channel interconnection (QPI) starting when the computer system is started next time, and controlling the NVM to empty garbage data generated by the NVM due to the unsuccessful completion of the data write-back operation;
controlling a channel communication of a CPU in the computer system to access the NVM after the BIOS completes QPI startup;
and after the NVM clears the garbage data, controlling the memory information interaction between a Dynamic Random Access Memory (DRAM) in the computer system and the NVM, and guiding the BIOS to complete the residual starting process so as to realize the normal starting of the computer system.
2. The method for protecting data when a system is shut down as claimed in claim 1, wherein before controlling the CPLD to perform a power-down operation on the computing board, the method further comprises:
monitoring the data write-back state of the NVM, and setting a stored value stored in a preset storage position in the NVM as a preset first value when the NVM successfully completes the data write-back operation;
and when the NVM does not successfully finish the data write-back operation, setting the stored value stored in the preset storage position to be a preset second value so that a user can determine the data write-back state of the NVM according to the stored value.
3. The method for protecting data during system shutdown according to claim 1, wherein the process of booting the BIOS to perform QPI boot is specifically:
booting the BIOS to perform QPI slow start;
and after a restart signal generated after the BIOS completes QPI slow start is received, the BIOS is guided to carry out QPI fast start.
4. The method for protecting data during system shutdown according to claim 1, wherein the process of controlling the channel connectivity of the CPU in the computer system accessing the NVM specifically comprises:
respectively configuring a first Field Programmable Gate Array (FPGA) in the computer system and a second FPGA for mounting the NVM;
controlling communication of access channels between a CPU and a first FPGA in the computer system, and controlling communication of the access channels between the first FPGA and a second FPGA so that the CPU accesses the NVM sequentially through the first FPGA and the second FPGA.
5. The method for protecting data during system shutdown according to claim 4, wherein the process of respectively configuring the first field programmable gate array FPGA in the computer system and the second FPGA mounted on the NVM specifically comprises:
and correspondingly writing specified data into the two chips according to the chip descriptions of the first FPGA and the second FPGA mounted on the NVM in the computer system.
6. The method for protecting data during shutdown of a system according to claim 4, wherein the memory information includes memory capacity and memory address.
7. The method for protecting data during system shutdown according to claim 6, wherein the process of controlling the memory information interaction between the DRAM and the NVM in the computer system specifically comprises:
acquiring the memory information of a DRAM in the computer system from the CPU, and sending the memory information of the DRAM to the second FPGA;
obtaining the memory information of the NVM correspondingly determined by the second FPGA according to the memory information of the DRAM and the splicing sequence of the DRAM and the NVM from the second FPGA;
and sending the determined memory information of the NVM to the BIOS to complete the interaction of the memory information between the DRAM and the NVM.
8. The method for protecting data during system shutdown according to claim 7, wherein the first FPGA is a Virtex 72000T FPGA, and the second FPGA is a Virtex7690T FPGA.
9. A BMC that protects data when a system is powered off, comprising:
the data protection unit is used for controlling the CPLD in the computer system to continuously supply power to the computing board through a power supply and controlling the NVM in the computer system to perform data write-back operation when the shutdown operation of the computer system is detected;
the power-off unit is used for controlling the CPLD to perform power-off operation on the computing board after receiving a data write-back completion signal sent by the NVM;
the BMC is further configured to:
after the NVM does not successfully finish the data write-back operation, guiding a Basic Input Output System (BIOS) to carry out quick channel interconnection (QPI) starting when the computer system is started next time, and controlling the NVM to empty garbage data generated by the NVM due to the unsuccessful completion of the data write-back operation;
controlling a channel communication of a CPU in the computer system to access the NVM after the BIOS completes QPI startup;
and after the NVM clears the garbage data, controlling the memory information interaction between a Dynamic Random Access Memory (DRAM) in the computer system and the NVM, and guiding the BIOS to complete the residual starting process so as to realize the normal starting of the computer system.
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