WO2022121475A1

WO2022121475A1 - Operating-state switching method and apparatus, and electronic device and storage medium

Info

Publication number: WO2022121475A1
Application number: PCT/CN2021/122291
Authority: WO
Inventors: 伍健
Original assignee: 浪潮电子信息产业股份有限公司
Priority date: 2020-12-11
Filing date: 2021-09-30
Publication date: 2022-06-16
Also published as: CN112506576A

Abstract

Disclosed are an operating-state switching method and apparatus, and an electronic device and a computer-readable storage medium. The method comprises: after acquiring a wake-up signal, a processor executing a start operation; generating a wake-up instruction after the start operation ends; and sending the wake-up instruction to a control component via a target bus, such that the control component keeps a reset signal, corresponding to a memory, unchanged.

Description

Operating state switching method, device, electronic device and storage medium

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims the priority of the Chinese patent application filed on December 11, 2020 with the application number 202011445720.0 and the title of the invention is "operation state switching method, device, electronic device and storage medium", the entire contents of which are by reference Incorporated in this application.

technical field

The present application relates to the field of computer technologies, and in particular, to an operating state switching method, an operating state switching device, an electronic device, and a computer-readable storage medium.

Background technique

The computer has a variety of different operating states according to its energy consumption during operation, such as the normal working state when the device is fully turned on, or the STR (Suspend to RAM, suspend to memory) state, that is, the sleep state, or the STD (Suspend to RAM) state. Disk, suspend to hard disk) state, or shutdown state. When switching in each state, the reset signal corresponding to the memory is different. Sometimes the reset signal needs to be adjusted, and sometimes the reset signal needs to be kept unchanged. For example, when the computer switches from the sleep state to the normal working state, it needs the reset signal to not be triggered. , in order to continue the previous work with the data in memory. In the related art, the reset signal of the memory is directly controlled by the processor. Since the state switching process is often accompanied by the power-on or power-off of the processor, IO jitter often occurs during the power-on process of the processor, which makes the reset signal of the memory unstable. , which can easily lead to the loss of data in the memory, which in turn leads to the failure of running state switching.

Therefore, the related art is prone to the problem of failure to switch the operating state, which is a technical problem to be solved by those skilled in the art.

SUMMARY OF THE INVENTION

Some embodiments of the present application provide an operating state switching method, an operating state switching apparatus, an electronic device, and a computer-readable storage medium, so as to avoid failure of operating state switching.

In some embodiments, the present application provides a method for switching operating states, including:

Get the wake-up signal and perform the start operation;

after the start-up operation is complete, generating a wake-up instruction; and

The wake-up command is sent to the control unit through the target bus, so that the control unit keeps the reset signal corresponding to the memory unchanged.

In some embodiments, before acquiring the wake-up signal, the method further includes: acquiring a sleep signal and generating a sleep instruction; and sending a sleep instruction to the control unit through the target bus, so that the control unit keeps the reset signal from being disabled Change.

In some embodiments, the generating a wake-up instruction includes generating a clock enable signal setting instruction, and generating the wake-up instruction by using the clock enable signal setting instruction.

In some implementation manners, the sending the wake-up command to the control component through the target bus, so that the control component keeps the reset signal unchanged, includes: sending the wake-up command to the single-chip microcomputer through the target bus, so that the single-chip computer keeps all the The reset signal remains unchanged.

In some embodiments, the operating state switching method of the present application further includes:

Acquire the power-on signal and execute the start-up operation;

After the start-up operation is finished, generating a power-on instruction; and

The power-on command is sent to the control unit through the target bus, so that the control unit adjusts the reset signal.

In some embodiments, the sending the power-on command to the control unit through the target bus, so that the control unit adjusts the reset signal, includes sending the power-on command to the control unit through the target bus The instruction causes the control component to send a low-level shock to the target port corresponding to the reset signal.

In some embodiments, after the wake-up command is sent to the control component through the target bus, the method further includes performing data interaction with the memory.

In some embodiments, the present application also provides an operating state switching device, comprising:

The acquisition module is used to perform the startup operation after acquiring the wake-up signal;

an instruction generation module for generating a wake-up instruction after the start-up operation ends; and

The signal holding module is used for sending the wake-up command to the control unit through the target bus, so that the control unit keeps the reset signal corresponding to the memory unchanged.

In some embodiments, the present application also provides an electronic device, including a memory and a processor, wherein:

the memory for storing computer readable instructions; and

The processor is configured to execute the computer-readable instructions to implement the above-mentioned method for switching operating states.

In some embodiments, the present application further provides a computer-readable storage medium for storing computer-readable instructions, wherein, when the computer-readable instructions are executed by a processor, the above-mentioned operating state switching method is implemented.

In some embodiments of the present application, in the operating state switching method provided, the processor executes a start-up operation after obtaining a wake-up signal; after the start-up operation is completed, a wake-up command is generated; the wake-up command is sent to the control unit through the target bus, so that the control unit keeps The reset signal corresponding to the memory remains unchanged.

In some embodiments of the present application, the provided operating state switching method utilizes a control component to relay the reset signal, and does not directly control the reset signal by the processor. When the processor starts after obtaining the wake-up signal, IO jitter may occur during the startup process. Since the processor does not directly control the reset signal corresponding to the memory, the memory will not be reset. After the start-up operation is completed, the processor generates a wake-up command, and sends the wake-up command to the control component, informing the control component how to set the control signal corresponding to the memory during this state switching. Since it is still necessary to use the data stored in the memory before entering the sleep state to work from the sleep state to the normal working state, after sending the wake-up command to the control unit, the control unit will keep the reset signal unchanged, so as to avoid triggering the reset signal and causing the memory data loss, thereby avoiding the failure of the computer's operating state switching. In some embodiments of the present application, by using the control component to isolate the reset signal of the processor and the memory, the control component plays the role of filtering IO jitter, which can avoid the failure of running state switching caused by the IO jitter of the processor, and solves the problem of the related art. It is prone to the failure of running state switching.

In addition, the present application also provides an operating state switching device, an electronic device and a computer-readable storage medium, which also have the above beneficial effects.

Description of drawings

In order to illustrate the technical solutions in the embodiments of the present application or related technologies more clearly, the following briefly introduces the accompanying drawings that are used in the description of the embodiments or related technologies. Obviously, the drawings in the following description are only the For the embodiments of the application, for those of ordinary skill in the art, other drawings can also be obtained according to the provided drawings without any creative effort.

FIG. 1 is a flowchart of a method for switching operating states provided by some embodiments of the present application;

FIG. 2 is a schematic structural diagram of a related art operating state switching system provided by some embodiments of the present application;

FIG. 3 is a schematic structural diagram of an operating state switching system provided by some embodiments of the present application;

FIG. 4 is a waveform diagram of a running state switching signal provided by some embodiments of the present application;

FIG. 5 is a schematic structural diagram of an operating state switching device provided by some embodiments of the present application;

FIG. 6 is a schematic structural diagram of an electronic device according to some embodiments of the present application.

Detailed ways

In order to make the purposes, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments It is only a part of the embodiments of the present application, but not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

Please refer to FIG. 1 , which is a flowchart of a method for switching an operating state provided by an embodiment of the present application.

In some embodiments, the method of the present application includes step S101 : acquiring a wake-up signal and performing a start-up operation.

Some or all of the steps in this embodiment may be executed by a processor in an electronic device, and the electronic device may be a computer, a server, or other devices having a processor and a memory. Advanced Configuration and Power Interface (ACPI for short) is an interface for operating system applications to manage all power management settings. Through this interface, functions such as sleep, hibernation, and wake-up of the computer can be realized. In ACPI, there are 6 states, S0 to S5, and their meanings are:

S0: This is the daily working state of electronic equipment, all components are fully turned on, and the power consumption generally exceeds 80W;

S1: Also known as POS (Power on Suspend), in this state, except that the processor is turned off by the processor (ie CPU) clock controller, other components still work normally, and the power consumption at this time is generally in Below 30W;

S2: At this time, the processor is in a stopped state, and the bus clock is also turned off, but the rest of the components are still running;

S3: STR mode (Suspend to RAM, suspend to memory), that is, sleep mode, the power consumption at this time does not exceed 10W;

S4: STD mode (Suspend to Disk, suspend to hard disk), in this state, the main power of the system is turned off, and the hard disk is used to store the data information before the S4 state, which is more power-saving than S3;

S5: All components including the power supply are turned off, that is, a shutdown state (shutdown), and the power consumption is 0.

It can be seen that except the S0 state, the processor is in the off state in other states, so when switching from the S1, S2 or S3 state to the S0 state in order to restart the work, the processor needs to be restarted. Specifically, a wake-up signal can be sent to the processor. This embodiment does not limit the specific sending method of the wake-up signal. For example, the wake-up signal can be generated by pressing the power-on button; or the wake-up signal can be obtained through a designated component, and the wake-up signal can be sent. To the processor, for example, to obtain wake-up signals sent by other electronic devices. It should be noted that the designated component should be in the open state in the non-S5 state. The processor performs a start-up operation after acquiring the wake-up signal. The specific process and manner of the start-up operation are not limited in this embodiment, and reference may be made to related technologies.

During the startup process of the processor, IO jitter may occur, that is, the input and output of the processor may be uncontrolled. Please refer to FIG. 2 , which is a schematic structural diagram of a related art operating state switching system provided by an embodiment of the present application. The processor 201 is directly connected to the memory 203 through the control circuit 202, and the processor directly controls the control signals for setting the state of the memory, including the reset signal DDRRESET. When the processor is started, IO jitter may cause the control interface signal of the reset signal to be unstable. The reset signal is sent under uncontrolled conditions, and in cooperation with other control signals, the memory is reset, causing data loss. lost. The memory stores the data stored before the processor is turned off. When the operating state is switched to S0, these data are needed to restore the electronic device to the state before sleep. Therefore, resetting the memory will cause the operating state to fail to switch, that is, wake-up failure.

In some implementations, the wake-up signal is acquired by the processor, and the processor performs a start-up operation after acquiring the wake-up signal.

In some embodiments of the present application, the control unit is connected to the processor and the memory is respectively connected, since the processor and the control unit need to transmit signals through the target bus, and IO jitter cannot constitute an effective signal that can be transmitted through the target bus, Therefore, the IO jitter when the processor performs the startup operation cannot affect the control unit, so that the memory control signal controlled by the control unit may not be affected by the IO jitter when the processor starts.

It should be noted that the specific model of the processor in this embodiment is not limited, for example, it may be a Loongson LS3A4000 chip.

In some embodiments, the method of the present application includes step S102: after the start-up operation ends, generating a wake-up instruction.

After the startup operation is completed, the memory state needs to be set so that the data can be interacted with the memory normally and the running state switching can be completed. Therefore, the wake-up command is generated. This embodiment does not limit the specific content of the wake-up command. It can notify the control component to control, and set the control signal of the memory through the control component, while keeping the reset signal corresponding to the memory unchanged to prevent the memory from being reset.

In some implementations, the wake-up instruction is generated by the processor.

In some embodiments, the step of generating the wake-up command may include step 11: generating a clock enable signal setting command, and generating the wake-up command by using the clock enable signal setting command.

The clock enable signal is the CKE signal, which is an input signal and is active high. There are two purposes of the CKE signal: first, to turn off the clock to enter the power saving mode; second, to enter the self-refresh state. When the CKE signal is invalid, all input-related functional modules in the memory stop working. At the same time, enter self-refresh to keep internal data valid. Before the electronic device enters the sleep state, in order to ensure the security of the data in the memory, the CKE signal of the memory is usually set to be invalid, so as to ensure that the data in it will not be rewritten. In order to work normally in the future, the clock enable signal setting instruction may be generated first when the wake-up instruction is generated, and the wake-up instruction may be generated based on the clock enable signal setting instruction. The control unit sets the CKE signal to be valid after obtaining the wake-up command. This embodiment does not limit whether other contents are included in the wake-up instruction, which can be set according to actual needs.

In some embodiments, the wake-up command may only be a signal instructing the control unit to keep the reset signal corresponding to the memory unchanged, so as to ensure that the reset signal remains unchanged.

In some embodiments, the method of the present application includes step S103 : sending a wake-up command to the control unit through the target bus, so that the control unit keeps the reset signal corresponding to the memory unchanged.

After the wake-up command is generated, the wake-up command is sent to the control unit through the target bus with the control unit. The target bus is connected to the control part, so that the influence of IO jitter on the control part can be avoided. The target bus may specifically be an I2C bus, or may be other signal buses. After sending the wake-up command to the control unit, the control unit can set the control signal corresponding to the memory according to the wake-up command, the setting process will not cause the reset signal of the memory to change, and the reset signal corresponding to the memory can be kept unchanged. In some embodiments, the control component is a single-chip microcomputer, and step S103 is to send a wake-up command to the single-chip microcomputer through the target bus, so that the single-chip computer keeps the reset signal unchanged. The specific model of the microcontroller is not limited, for example, it can be an STM32 microcontroller. After the control signal corresponding to the memory is set, the switching of the running state can be completed. In this embodiment, the switching of the running state is switching from the sleep state to the running state. Further, data interaction with the memory can also be performed, so that the electronic device can work normally.

In some embodiments, a wake-up command is sent by the processor to the control unit via the target bus.

By applying the operating state switching method provided by some embodiments of the present application, the reset signal is relayed by the control component, and the reset signal is not directly controlled by the processor. When the processor starts after obtaining the wake-up signal, IO jitter may occur during the startup process. Since the processor does not directly control the reset signal corresponding to the memory, the memory will not be reset. After the start-up operation is completed, the processor generates a wake-up command, and sends the wake-up command to the control component, informing the control component how to set the control signal corresponding to the memory during this state switching. Since it is still necessary to use the data stored in the memory before entering the sleep state to work from the sleep state to the normal working state, after sending a wake-up command to the control unit, the control unit will keep the reset signal unchanged, so as to avoid triggering the reset signal and causing the memory data loss, thereby avoiding the failure of the computer's operating state switching. By using the control part to isolate the reset signal of the processor and the memory, the control part plays the role of filtering IO jitter, which can avoid the failure of operating state switching caused by the IO jitter of the processor, and solve the problem that the related technology is prone to failure of operating state switching.

Based on the above embodiment, before switching the electronic device from the S1, S2 or S3 state to the S0 state, it needs to be switched from the S0 state to the S1, S2 or S3 state first. Therefore, before acquiring the wake-up signal, the method may further include:

Step 21: Acquire a sleep signal and generate a sleep instruction; and/or

Step 22: Send a sleep command to the control unit through the target bus, so that the control unit keeps the reset signal unchanged.

In this embodiment, the sleep signal is used to indicate entering the S1, S2 or S3 state, and the specific acquisition method thereof is not limited in this embodiment, for example, the acquisition method may be the same as that of the wake-up signal. After acquiring the sleep signal, a corresponding sleep command is generated, and the sleep command is sent to the control unit through the target bus, so that the control unit sets the control signal corresponding to the memory. It can be understood that since the electronic device has not entered the shutdown state (ie, the S5 state), no matter how the control component sets the control signal corresponding to the memory, the reset signal will remain unchanged.

In some implementations, the sleep signal is obtained by the processor, and the sleep instruction is generated by the processor after obtaining the sleep signal. In some implementations, a sleep instruction is sent by the processor to the control unit over the target bus.

Based on the above embodiment, in another case, the reset signal may be adjusted when the electronic device is switched from the S5 state to the S0 state, so as to enable the electronic device to be powered on normally. In some embodiments, the method can also include:

Step 31: Obtain a power-on signal and perform a boot-up operation; and/or

Step 32: After the start-up operation is completed, generate a boot command; and/or

Step 33: Send a power-on command to the control unit through the target bus, so that the control unit adjusts the reset signal.

The specific detection method of the power-on signal is similar to the acquisition method of the wake-up signal or the sleep signal, which is not repeated in this embodiment. After the power-on signal is detected, a start-up operation is performed, and the specific process of the start-up operation is not limited. After the start-up operation is completed, a power-on command is generated and sent to the control unit. Since the memory needs to be left blank when the electronic device is powered on, the control component can adjust the reset signal after obtaining the boot command, so that the memory can be reset. This embodiment does not limit the specific manner in which the control unit adjusts the reset signal. For example, in some embodiments, sending a power-on command to the control unit through the target bus so that the control unit adjusts the reset signal may include:

Step 41: Send a power-on command to the control unit through the target bus, so that the control unit sends a low-level shock to the target port corresponding to the reset signal.

In this embodiment, the DDRRESET signal can be temporarily set to a low-level state by sending a low-level shock to the port corresponding to the reset signal, that is, the target port. After detecting that the reset signal is a low-level signal, the memory can perform an initialization operation to complete the initialization of the memory.

In some implementations, the start-up operation is performed by a processor. In some implementations, the power-on instruction is generated by the processor. In some implementations, a power-on command is sent by the processor to the control unit via the target bus.

Please refer to FIG. 3. FIG. 3 is a schematic structural diagram of an operating state switching system provided by some embodiments of the present application. In the operating state switching system, the processor 201 is connected to the memory 203 through the control unit 204, and the control unit itself is powered by the S3 power supply. 205 powered. The S3 power supply 205 is a power supply that still supplies power to the outside in the S3 state. Please refer to FIG. 4 , FIG. 4 is a waveform diagram of an operating state switching signal provided by some embodiments of the present application. SLP_S3# is the S3 state flag signal, and when it is at a low level, it indicates that the electronic device enters the S3 state. SLP_S4# and SLP_S5# are the S4 state flag signal and the S5 state flag signal respectively, MC0&MC1_DDR_DIMM_RESET_N is the DDRRESET signal, and the low level is the enable state, that is, when the low level is low, the memory will be initialized, that is, reset. BIOS Command is the BIOS control signal, and the MC0_CKE and MC1_CKE signals are the CKE signals corresponding to the two memories respectively. When the electronic device transitions from the S0 state to the S3 state, SLP_S3# changes to a low level state, and at this time, the processor generates a sleep command and sends it to the control unit 204 . After acquiring the sleep instruction, the control unit 204 sets the CKE signal to a low level state to ensure data security in the memory 203 and to ensure that the MC0 & MC1_DDR_DIMM_RESET_N signals are at a high level state. When the electronic device transitions from the S3 state to the S0 state, the processor obtains the wake-up signal and executes the start-up operation. During the start-up process, since the control unit does not receive the wake-up command, the memory control signal will not be set. After the processor generates a wake-up command (the BIOS Command is in a valid state), it sends it to the control unit. After the control unit receives the wake-up command, it restores the CKE signal to a high level, so that the processor and the memory can exchange data. During this process, the MC0&MC1_DDR_DIMM_RESET_N signals can also be kept at a high level. The methods of some embodiments of the present application can solve the problem that the switching of the operating state of the electronic device fails due to the IO jitter when the processor is started.

The following describes the operating state switching device provided by the embodiments of the present application. The operating state switching device described below and the operating state switching method described above may refer to each other correspondingly.

Please refer to FIG. 5. FIG. 5 is a schematic structural diagram of an operating state switching apparatus provided by some embodiments of the present application, including:

an acquisition module 110, configured to perform a startup operation after acquiring the wake-up signal;

an instruction generation module 120 for generating a wake-up instruction after the start-up operation is completed; and

The signal holding module 130 is configured to send a wake-up command to the control unit through the target bus, so that the control unit keeps the reset signal corresponding to the memory unchanged.

In some embodiments, the apparatus further includes:

a sleep instruction generation module, configured to generate a sleep instruction after acquiring the sleep signal; and

The sleep instruction sending module is used for sending the sleep instruction to the control unit through the target bus, so that the control unit keeps the reset signal unchanged.

In some embodiments, the instruction generating module 120 includes a generating unit for generating a clock enable signal setting instruction, and generating a wake-up instruction using the clock enable signal setting instruction.

In some embodiments, the signal holding module 130 includes a microcontroller control unit, configured to send a wake-up command to the microcontroller through the target bus, so that the microcontroller keeps the reset signal unchanged.

In some embodiments, the apparatus further includes:

The startup module is used to perform the startup operation after detecting the startup signal;

a power-on instruction generation module, used for generating a power-on instruction after the start-up operation is completed; and

The power-on command sending module is used for sending a power-on command to the control unit through the target bus, so that the control unit adjusts the reset signal.

In some embodiments, the power-on command sending module includes a low-level shock unit, configured to send a power-on command to the control component through the target bus, so that the control component sends a low-level shock to the target port corresponding to the reset signal.

In some embodiments, the apparatus further includes a data interaction module for performing data interaction with the memory.

The electronic device provided by the embodiments of the present application will be introduced below, and the electronic device described below and the operating state switching method described above may refer to each other correspondingly.

Please refer to FIG. 6 , which is a schematic structural diagram of an electronic device according to some embodiments of the present application. The electronic device 100 may include a processor 101 and a memory 102 , and may further include one or more of a multimedia component 103 , an information input/information output (I/O) interface 104 and a communication component 105 .

Wherein, the processor 101 is used to control the overall operation of the electronic device 100 to complete all or part of the steps in the above-mentioned operating state switching method; the memory 102 is used to store various types of data to support the operation of the electronic device 100, these Data may include, for example, instructions for any application or method to operate on the electronic device 100, as well as application-related data. The memory 102 may be implemented by any type of volatile or non-volatile memory device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (Electrically Erasable Programmable Read-Only Memory) Erasable Programmable Read-Only Memory, EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (Read- One or more of Only Memory, ROM), magnetic memory, flash memory, magnetic disk or optical disk.

Multimedia components 103 may include screen and audio components. Wherein the screen can be, for example, a touch screen, and the audio component is used for outputting and/or inputting audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signal may be further stored in the memory 102 or transmitted through the communication component 105 . The audio assembly also includes at least one speaker for outputting audio signals. The I/O interface 104 provides an interface between the processor 101 and other interface modules, and the above-mentioned other interface modules may be a keyboard, a mouse, a button, and the like. These buttons can be virtual buttons or physical buttons. The communication component 105 is used for wired or wireless communication between the electronic device 100 and other devices. Wireless communication, such as Wi-Fi, Bluetooth, Near Field Communication (NFC for short), 2G, 3G or 4G, or one or a combination of them, so the corresponding communication component 105 may include: Wi-Fi parts, Bluetooth parts, NFC parts.

The electronic device 100 may be implemented by one or more Application Specific Integrated Circuit (ASIC for short), Digital Signal Processor (DSP for short), Digital Signal Processing Device (DSPD for short), Programmable logic device (Programmable Logic Device, PLD for short), Field Programmable Gate Array (Field Programmable Gate Array, FPGA for short), controller, microcontroller, microprocessor or other electronic components are implemented for implementing the above embodiments The given operation state switching method.

The following describes the computer-readable storage medium provided by some embodiments of the present application, and the computer-readable storage medium described below and the operating state switching method described above may refer to each other correspondingly.

The present application also provides a computer-readable storage medium, such as a non-volatile computer-readable storage medium, where computer-readable instructions are stored on the computer-readable storage medium, and when the computer-readable instructions are executed by a processor, the above-mentioned operating state is realized The steps to switch the method.

The computer-readable storage medium may include: a USB flash drive, a removable hard disk, a read-only memory (Read-Only Memory, ROM), a random access memory (Random Access Memory, RAM), a magnetic disk or an optical disk, etc. that can store program codes medium.

The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments may be referred to each other. As for the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant part can be referred to the description of the method.

Those skilled in the art may further realize that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two, in order to clearly illustrate the hardware and software In the above description, the components and steps of each example have been generally described according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Skilled artisans may use different approaches to implement the described functionality for each particular application, but such implementations should not be considered beyond the scope of this application.

The steps of a method or algorithm described in conjunction with the embodiments disclosed herein may be directly implemented in hardware, a software module executed by a processor, or a combination of the two. A software module can be placed in random access memory (RAM), internal memory, read only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other in the technical field. in any other known form of storage medium.

Finally, it should also be noted that, in this context, relationships such as first and second, etc., are used only to distinguish one entity or operation from another, and do not necessarily require or imply these entities or that there is any such actual relationship or sequence between operations. Furthermore, the terms including, comprising, or any other variation are intended to cover non-exclusive inclusion such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or Yes also includes elements inherent to such a process, method, article or apparatus.

The principles and implementations of the present application are described herein by using specific examples. The descriptions of the above embodiments are only used to help understand the methods and core ideas of the present application. There will be changes in the specific implementation and application scope. To sum up, the content of this specification should not be construed as a limitation to the application.

Claims

A running state switching method, comprising:

Get the wake-up signal and perform the CPU startup operation;

after the start-up operation is complete, generating a wake-up instruction; and

Send the wake-up command to the control unit through the target bus, so that the control unit sends a control signal required for the memory wake-up to the memory, wherein the control unit keeps the wake-up command from the target bus before receiving the wake-up command The control signal required for the memory sleep.
The operating state switching method according to claim 1, before the processor acquires the wake-up signal, further comprising:

acquire sleep signals and generate sleep instructions; and

The sleep command is sent to the control unit through the target bus, so that the control unit keeps the reset signal unchanged.
The operating state switching method according to claim 1 or 2, wherein the generating a wake-up instruction comprises:

A clock enable signal setting instruction is generated, and the wake-up instruction is generated using the clock enable signal setting instruction.
The operating state switching method according to any one of claims 1 to 3, wherein the sending the wake-up command to the control unit through the target bus so that the control unit keeps the reset signal unchanged, comprising:

The wake-up command is sent to the single-chip microcomputer through the target bus, so that the single-chip computer keeps the reset signal unchanged.
The operating state switching method according to any one of claims 1 to 4, further comprising:

obtaining a power-on signal and executing the CPU start-up operation;

After the start-up operation is completed, a boot-up instruction is generated;

The power-on command is sent to the control unit through the target bus, so that the control unit adjusts the reset signal.
The operating state switching method according to claim 5, wherein the sending the power-on command to the control component through the target bus, so that the control component adjusts the reset signal, comprises:

The power-on command is sent to the control unit through the target bus, so that the control unit sends a low-level shock to the target port corresponding to the reset signal.
The operating state switching method according to any one of claims 1 to 6, after sending the wake-up command to the control component through the target bus, further comprising:

Data interaction with the memory.
An operating state switching device, comprising:

The acquisition module is used to perform the startup operation after acquiring the wake-up signal;

an instruction generation module for generating a wake-up instruction after the start-up operation ends; and

The signal holding module is configured to send the wake-up command to the control unit through the target bus, so that the control unit keeps the reset signal corresponding to the memory unchanged.
An electronic device comprising:

memory for storing computer readable instructions; and

The processor is configured to execute the computer-readable instructions to implement the operating state switching method according to any one of claims 1 to 7.
A non-volatile computer-readable storage medium storing computer-readable instructions, wherein when the computer-readable instructions are executed by a processor, the operating state switching method according to any one of claims 1 to 7 is implemented.