CN112506576A - Operation state switching method and device, electronic equipment and storage medium - Google Patents
Operation state switching method and device, electronic equipment and storage medium Download PDFInfo
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
- G06F9/4401—Bootstrapping
- G06F9/4418—Suspend and resume; Hibernate and awake
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Abstract
The application discloses a method and a device for switching operation states, electronic equipment and a computer readable storage medium, wherein the method comprises the following steps: the processor executes a starting operation after acquiring the wake-up signal; after the starting operation is finished, a wake-up instruction is generated; sending a wake-up instruction to the control component through the target bus so that the control component keeps a reset signal corresponding to the memory unchanged; according to the method, the control component is used for transferring the reset signal, the processor does not directly control the reset signal, and after the processor sends a wake-up instruction to the control component, the control component can keep the reset signal unchanged, so that data loss in an internal memory caused by triggering of the reset signal is avoided, and further operation state switching failure of the computer is avoided. The reset signals of the processor and the memory are isolated by the control component, the control component plays a role in filtering IO jitter, and operation state switching failure caused by IO jitter when the processor is started can be avoided.
Description
Technical Field
The present disclosure relates to the field of computer technologies, and in particular, to an operating state switching method, an operating state switching apparatus, an electronic device, and a computer-readable storage medium.
Background
The computer has a plurality of different operation states during operation, for example, a normal operation state in which the device is fully opened, or an STR (Suspend to RAM) state, i.e., a sleep state, or an STD (Suspend to Disk) state, or a power-off state, according to different energy consumption of the computer. When switching among various states, the reset signals corresponding to the memories are different, the reset signals sometimes need to be adjusted, and sometimes the reset signals need to be kept unchanged. In the related art, a reset signal of a memory is directly controlled by a processor, and because a state switching process is usually accompanied with power-on or power-off of the processor, IO jitter often occurs in the power-on process of the processor, so that the reset signal of the memory is unstable, data in the memory is easily lost, and further operation state switching failure is caused.
Therefore, the related art is prone to the problem of failure in switching the operating state, which is a technical problem to be solved by those skilled in the art.
Disclosure of Invention
In view of the above, an object of the present application is to provide an operation state switching method, an operation state switching apparatus, an electronic device, and a computer-readable storage medium, which avoid failure of operation state switching.
In order to solve the above technical problem, the present application provides an operation state switching method, including:
the processor executes a starting operation after acquiring the wake-up signal;
after the starting operation is finished, generating a wake-up instruction;
and sending the awakening instruction to the control component through the target bus so that the control component keeps the reset signal corresponding to the memory unchanged.
Optionally, before the processor acquires the wake-up signal, the method further includes:
after a sleep signal is acquired, a sleep instruction is generated;
sending a sleep instruction to the control component through the target bus so that the control component keeps the reset signal unchanged.
Optionally, the generating the wake-up instruction includes:
and generating a clock enable signal setting instruction, and generating the awakening instruction by using the clock enable signal setting instruction.
Optionally, the sending the wake-up instruction to the control unit through the target bus so that the control unit keeps the reset signal unchanged includes:
and sending the awakening instruction to a single chip microcomputer through a target bus so that the single chip microcomputer can keep the reset signal unchanged.
Optionally, the method further comprises:
executing the starting operation after detecting a starting signal;
after the starting operation is finished, generating a starting instruction;
and sending the starting-up instruction to the control component through the target bus so that the control component adjusts the reset signal.
Optionally, the sending the power-on command to the control unit through the target bus so that the control unit adjusts the reset signal includes:
and sending the starting-up instruction to the control component through the target bus so that the control component sends low-level impact to a target port corresponding to the reset signal.
Optionally, after sending the wake-up instruction to the control unit through the target bus, the method further includes:
and carrying out data interaction with the memory.
The present application further provides an operating state switching device, including:
the acquisition module is used for executing starting operation after the processor acquires the wake-up signal;
the instruction generation module is used for generating a wake-up instruction after the start operation is finished;
and the signal holding module is used for sending the awakening instruction to the control component through the target bus so that the control component can keep the reset signal corresponding to the memory unchanged.
The present application further provides an electronic device comprising a memory and a processor, wherein:
the memory is used for storing a computer program;
the processor is configured to execute the computer program to implement the above operation state switching method.
The present application further provides a computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the above-mentioned operation state switching method.
According to the operation state switching method, the processor executes starting operation after acquiring the wake-up signal; after the starting operation is finished, a wake-up instruction is generated; and sending a wake-up instruction to the control unit through the target bus so that the control unit keeps the reset signal corresponding to the memory unchanged.
Therefore, the method utilizes the control component to transfer the reset signal, and the processor does not directly control the reset signal. When the processor is started after acquiring the wake-up signal, IO jitter may occur in the starting process, and the processor does not directly control the reset signal corresponding to the memory, so that the memory is not reset. After the starting operation is finished, the processor generates a wake-up instruction, sends the wake-up instruction to the control component and informs the control component how to set a control signal corresponding to the memory when the state is switched. Because the data stored in the memory before entering the sleep state is still needed to be used for working when the sleep state is changed to the normal working state, after the awakening instruction is sent to the control component, the control component can keep the reset signal unchanged, the data in the memory is prevented from being lost due to triggering of the reset signal, and further the failure of switching the running state of the computer is avoided. By utilizing the control component to isolate the reset signals of the processor and the memory, the control component plays a role in filtering IO jitter, operation state switching failure caused by IO jitter of the processor can be avoided, and the problem that operation state switching failure easily occurs in the related technology is solved.
In addition, the application also provides an operation state switching device, electronic equipment and a computer readable storage medium, and the beneficial effects are also achieved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments or related technologies of the present application, the drawings needed to be used in the description of the embodiments or related technologies are briefly introduced below, it is obvious that the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained according to the provided drawings without creative efforts.
Fig. 1 is a flowchart of an operation state switching method according to an embodiment of the present disclosure;
fig. 2 is a schematic structural diagram of an operation state switching system according to the related art provided in the embodiment of the present application;
fig. 3 is a schematic structural diagram of an operation state switching system according to an embodiment of the present disclosure;
fig. 4 is a waveform diagram of an operation state switching signal according to an embodiment of the present application;
fig. 5 is a schematic structural diagram of an operation state switching device according to an embodiment of the present disclosure;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are only a part of the embodiments of the present application, and not all the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Referring to fig. 1, fig. 1 is a flowchart of an operation state switching method according to an embodiment of the present disclosure. The method comprises the following steps:
s101: and the processor executes starting operation after acquiring the wake-up signal.
Some or all of the steps in this embodiment may be performed by a processor in an electronic device, which may be a computer, a server, or other devices having a processor and a memory. Advanced Configuration and Power Interface (ACPI), for short, is an Interface for operating system applications to manage all Power management settings, and through this Interface, functions of the computer such as sleep, hibernate, wake-up, etc. can be implemented. In ACPI there are 6 states, S0 to S5, which represent the following meanings:
s0: the power consumption is generally over 80W when all components are fully opened;
s1: also called pos (power on suspend), in this state, except that the CPU is turned off by a CPU (i.e. processor) clock controller, other parts still work normally, and the power consumption is generally below 30W;
s2: at this time, the CPU is in a stop operation state, the bus clock is also closed, but the rest parts still run;
s3: STR mode (Suspend to RAM), i.e. sleep mode, where power consumption does not exceed 10W;
s4: an STD mode (Suspend to Disk), in which the system main power is off, and the data information before the S4 state is stored by the hard Disk, which saves more power than S3;
s5: all parts including the power supply are turned off, namely, in a shutdown state (shutdown), and the power consumption is 0.
It can be seen that the processors are in the off state in all but the S0 state, and therefore need to be restarted when switching from the S1, S2, or S3 state to the S0 state to resume operation. Specifically, the wake-up signal may be sent to the processor, and the embodiment does not limit the specific sending manner of the wake-up signal, for example, the wake-up signal may be generated by pressing a power-on key; or the wake-up signal may be obtained by a designated component and sent to the processor, for example, a wake-up signal sent by other electronic devices. Note that the designating means should be in the on state in the state other than S5. The processor executes the start operation after acquiring the wake-up signal, and the specific process and manner of the start operation are not limited in this embodiment, and reference may be made to related technologies.
During the starting process of the processor, the phenomenon of IO jitter may occur, that is, the input and output of the processor may not be controlled. Referring to fig. 2, fig. 2 is a schematic structural diagram of an operation state switching system according to the related art provided in the embodiment of the present application. The CPU is directly connected with the memory through a control circuit, and directly controls a control signal for setting the state of the memory, wherein the control signal comprises a reset signal DDRRESET. When a CPU is started, IO jitter may cause the control interface signal of a reset signal to be unstable, the reset signal is sent under the uncontrolled condition, and the memory is reset under the coordination of other control signals, so that data loss is caused. The memory stores data stored before the CPU is turned off, and when the operating state is switched to S0, the electronic device needs to be restored to the state before the sleep state by using the data, and thus the reset of the memory may cause a failure in switching the operating state, that is, a failure in waking up.
In order to solve the problems, the control component is connected with the CPU and the memory respectively, and because the CPU and the control component need to transmit signals through a target bus and IO jitter cannot form effective signals which can be transmitted through the target bus, the IO jitter of the processor during the execution of the starting operation cannot affect the control component, so that the memory control signals controlled by the control component cannot be affected by the IO jitter of the CPU during the starting.
It should be noted that, the specific type of the processor in this embodiment is not limited, and may be, for example, a loongson LS3a4000 chip.
S102: and after the starting operation is finished, generating a wake-up instruction.
After the start operation is finished, the state of the memory needs to be set so as to perform data interaction with the memory normally and complete the switching of the running state. Therefore, the wake-up instruction is generated, and the embodiment does not limit the specific content of the wake-up instruction, and may notify the control unit to control, and set the control signal of the memory through the control unit, and meanwhile, keep the reset signal corresponding to the memory unchanged, so as to prevent the memory from being reset. Specifically, in a possible implementation, the step of generating the wake-up instruction may include:
step 11: and generating a clock enable signal setting instruction, and generating a wake-up instruction by using the clock enable signal setting instruction.
The clock enable signal is the CKE signal, which is the input signal and active high. The use of CKE signals is two: firstly, closing a clock to enter a power saving mode; and secondly, entering a self-refresh state. When the CKE signal is invalid, all functional modules related to the input in the memory stop working. While entering self-refresh keeps the internal data valid. Before the electronic device enters the sleep state, in order to ensure the security of the data in the memory, the CKE signal of the memory is usually set to be invalid, so as to ensure that the data therein is not overwritten. For subsequent normal operation, the clock enable signal setting instruction may be generated first when the wake-up instruction is generated, and the wake-up instruction may be generated based on the clock enable signal setting instruction. So that the control component sets the CKE signal active after acquiring the wake-up instruction. In this embodiment, it is not limited whether the wake-up instruction further includes other content, and the setting may be performed according to actual needs.
In another embodiment, the wake-up instruction may simply be a signal instructing the control unit to leave the memory corresponding reset signal unchanged, so as to ensure that the reset signal is unchanged.
S103: and sending a wake-up instruction to the control unit through the target bus so that the control unit keeps the reset signal corresponding to the memory unchanged.
And after the wake-up command is generated, sending the wake-up command to the control unit through a target bus between the control unit and the wake-up command. The target bus is connected with the control component, so that the influence of IO jitter on the control component can be avoided. The target bus may specifically be the I2C bus, or may be another signaling bus. After the wake-up instruction is sent to the control component, the control component can set the control signal corresponding to the memory according to the wake-up instruction, the reset signal change of the memory cannot be caused in the setting process, and the reset signal corresponding to the memory can be kept unchanged. In a possible implementation manner, the control unit is a single chip, and step S103 is to send a wake-up command to the single chip through the target bus, so that the single chip keeps the reset signal unchanged. The specific type of the single chip microcomputer is not limited, and for example, the single chip microcomputer can be an STM32 single chip microcomputer. After the control signal corresponding to the memory is set, the operation state switching may be completed, and in this embodiment, the operation state switching is switching from the sleep state to the operation state. Furthermore, data interaction can be carried out with the memory, so that the electronic equipment can work normally.
By applying the operation state switching method provided by the embodiment of the application, the reset signal is transferred by using the control component, and the processor does not directly control the reset signal. When the processor is started after acquiring the wake-up signal, IO jitter may occur in the starting process, and the processor does not directly control the reset signal corresponding to the memory, so that the memory is not reset. After the starting operation is finished, the processor generates a wake-up instruction, sends the wake-up instruction to the control component and informs the control component how to set a control signal corresponding to the memory when the state is switched. Because the data stored in the memory before entering the sleep state is still needed to be used for working when the sleep state is changed to the normal working state, after the awakening instruction is sent to the control component, the control component can keep the reset signal unchanged, the data in the memory is prevented from being lost due to triggering of the reset signal, and further the failure of switching the running state of the computer is avoided. By utilizing the control component to isolate the reset signals of the processor and the memory, the control component plays a role in filtering IO jitter, operation state switching failure caused by IO jitter of the processor can be avoided, and the problem that operation state switching failure easily occurs in the related technology is solved.
Based on the above embodiments, before switching the electronic device from the S1, S2, or S3 state to the S0 state, it needs to be switched from the S0 state to the S1, S2, or S3 state. Therefore, before the processor acquires the wake-up signal, the method may further include:
step 21: and after the sleep signal is acquired, a sleep instruction is generated.
Step 22: a sleep instruction is sent to the control unit through the target bus so that the control unit keeps the reset signal unchanged.
In this embodiment, the sleep signal is used to indicate to enter the S1, S2, or S3 state, and the specific obtaining manner of the sleep signal is not limited in this embodiment, and may be the same as the obtaining manner of the wake-up signal. After the sleep signal is acquired, a corresponding sleep instruction is generated, and the sleep instruction is sent to the control component through the target bus, so that the control component can set a control signal corresponding to the memory. It is understood that, since the electronic device does not enter the power-off state (i.e., the S5 state), the control unit keeps the reset signal unchanged regardless of how the control signal corresponding to the memory is set.
Based on the above embodiment, in another case, the reset signal may be adjusted when the electronic device switches from the S5 state to the S0 state, so as to normally turn on the electronic device. Specifically, the method may further include:
step 31: and executing starting operation after the starting signal is detected.
Step 32: and after the starting operation is finished, generating a starting instruction.
Step 33: a power-on command is sent to the control unit via the target bus so that the control unit adjusts the reset signal.
The specific detection mode of the power-on signal is similar to the acquisition mode of the wake-up signal or the sleep signal, and this embodiment is not described herein again. And after the starting signal is detected, executing the starting operation, wherein the specific process of the starting operation is not limited. And after the starting operation is finished, generating a starting instruction and sending the starting instruction to the control component. Because the memory needs to be blank when the electronic device is started, the control component can adjust the reset signal after acquiring the starting instruction, so that the memory can be reset. For example, in a possible implementation, the step of sending a power-on command to the control unit through the target bus so that the control unit adjusts the reset signal may include:
step 41: and sending a starting-up command to the control part through the target bus so that the control part sends low-level impact to a target port corresponding to the reset signal.
In this embodiment, the DDRRESET signal may be temporarily set to a low state by sending a low impact to the port corresponding to the reset signal, i.e., the destination port. And after the memory detects that the reset signal is a low-level signal, initializing operation can be carried out to finish initialization of the memory.
Referring to fig. 3, fig. 3 is a schematic structural diagram of an operating state switching system according to an embodiment of the present disclosure, in which a CPU is connected to a memory through a control unit, and the control unit is powered by a power supply of S3. The S3 power source is the power source still supplying power to the outside in the S3 state. Referring to fig. 4, fig. 4 is a waveform diagram of an operation state switching signal according to an embodiment of the present disclosure. Where SLP _ S3# is an S3 state flag signal, which indicates that the electronic device enters an S3 state when it is at a low level. The SLP _ S4# and SLP _ S5# are an S4 state flag signal and an S5 state flag signal, respectively, MC0& MC1_ DDR _ DIMM _ RESET _ N are DDRRESET signals, and the low level is an enable state, that is, when the low level is in the low level, the memory is initialized, that is, RESET is performed. The BIOS Command is a BIOS control signal, and the MC0_ CKE and MC1_ CKE signals are CKE signals corresponding to two memories respectively. When the electronic apparatus transitions from the S0 state to the S3 state, SLP _ S3# changes to a low level state, at which time the processor generates a sleep instruction and issues it to the control section. After the control component acquires the sleep command, the CKE signal is set to be in a low level state, so that the safety of data in the memory is ensured, and meanwhile, the MC0 and MC1_ DDR _ DIMM _ RESET _ N signals are ensured to be in a high level state. When the electronic device is switched from the state of S3 to the state of S0, the processor acquires the wake-up signal and executes a starting operation, and in the starting process, the control signal of the memory is not set because the control part does not receive the wake-up instruction. After the processor generates a wake-up Command (the BIOS Command is in valid state), the wake-up Command is sent to the control unit, and after receiving the wake-up Command, the control unit restores the CKE signal to high level, so that the processor and the memory perform data interaction. In this process, the MC0& MC1_ DDR _ DIMM _ RESET _ N signal may also be held high. The method can solve the problem that the switching of the operation state of the electronic equipment fails due to IO jitter when the CPU is started.
In the following, the operation state switching device provided in the embodiment of the present application is introduced, and the operation state switching device described below and the operation state switching method described above may be referred to correspondingly.
Referring to fig. 5, fig. 5 is a schematic structural diagram of an operation state switching device according to an embodiment of the present application, including:
an obtaining module 110, configured to execute a start operation after the processor obtains the wake-up signal;
the instruction generating module 120 is configured to generate a wake-up instruction after the start operation is finished;
and the signal holding module 130 is configured to send a wake-up instruction to the control unit through the target bus, so that the control unit keeps the reset signal corresponding to the memory unchanged.
Optionally, the method further comprises:
the sleep instruction generating module is used for generating a sleep instruction after acquiring the sleep signal;
and the sleep instruction sending module is used for sending a sleep instruction to the control component through the target bus so that the control component keeps the reset signal unchanged.
Optionally, the instruction generating module 120 includes:
and the generating unit is used for generating a clock enable signal setting instruction and generating a wake-up instruction by using the clock enable signal setting instruction.
Optionally, the signal holding module 130 includes:
and the singlechip control unit is used for sending a wake-up instruction to the singlechip through the target bus so that the singlechip keeps the reset signal unchanged.
Optionally, the method further comprises:
the starting module is used for executing starting operation after detecting a starting signal;
the starting instruction generating module is used for generating a starting instruction after the starting operation is finished;
and the starting instruction sending module is used for sending a starting instruction to the control component through the target bus so that the control component can adjust the reset signal.
Optionally, the power-on instruction sending module includes:
and the low-level impact unit is used for sending a starting-up instruction to the control component through the target bus so that the control component sends low-level impact to a target port corresponding to the reset signal.
Optionally, the method further comprises:
and the data interaction module is used for carrying out data interaction with the memory.
In the following, the electronic device provided by the embodiment of the present application is introduced, and the electronic device described below and the operation state switching method described above may be referred to correspondingly.
Referring to fig. 6, fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present disclosure. Wherein the electronic device 100 may include a processor 101 and a memory 102, and may further include one or more of a multimedia component 103, an information input/information output (I/O) interface 104, and a communication component 105.
The processor 101 is configured to control the overall operation of the electronic device 100 to complete all or part of the steps in the operation state switching method; the memory 102 is used to store various types of data to support operation at the electronic device 100, such data may include, for example, instructions for any application or method operating on the electronic device 100, as well as application-related data. The Memory 102 may be implemented by any type or combination of volatile and non-volatile Memory devices, such as one or more of Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read-Only Memory (EPROM), Programmable Read-Only Memory (PROM), Read-Only Memory (ROM), magnetic Memory, flash Memory, magnetic or optical disk.
The multimedia component 103 may include a screen and an audio component. Wherein the screen may be, for example, a touch screen and the audio component is used for outputting and/or inputting audio signals. For example, the audio component may include a microphone for receiving external audio signals. The received audio signal may further be stored in the memory 102 or transmitted through the communication component 105. The audio assembly also includes at least one speaker for outputting audio signals. The I/O interface 104 provides an interface between the processor 101 and other interface modules, such as a keyboard, mouse, buttons, etc. These buttons may be virtual buttons or physical buttons. The communication component 105 is used for wired or wireless communication between the electronic device 100 and other devices. Wireless Communication, such as Wi-Fi, bluetooth, Near Field Communication (NFC), 2G, 3G, or 4G, or a combination of one or more of them, so that the corresponding Communication component 105 may include: Wi-Fi part, Bluetooth part, NFC part.
The electronic Device 100 may be implemented by one or more Application Specific Integrated Circuits (ASICs), Digital Signal Processors (DSPs), Digital Signal Processing Devices (DSPDs), Programmable Logic Devices (PLDs), Field Programmable Gate Arrays (FPGAs), controllers, microcontrollers, microprocessors or other electronic components, and is configured to perform the operation state switching method according to the above embodiments.
In the following, a computer-readable storage medium provided by the embodiments of the present application is introduced, and the computer-readable storage medium described below and the operation state switching method described above may be referred to correspondingly.
The present application further provides a computer-readable storage medium, on which a computer program is stored, and when being executed by a processor, the computer program implements the steps of the above-mentioned operation state switching method.
The computer-readable storage medium may include: various media capable of storing program codes, such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk, or an optical disk.
The embodiments are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same or similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.
Those of skill would further appreciate that the various illustrative components and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative components and steps have been described above generally in terms of their functionality in order to clearly illustrate this interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the implementation. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present application.
The steps of a method or algorithm described in connection with the embodiments disclosed herein may be embodied directly in hardware, in a software module executed by a processor, or in a combination of the two. A software module may reside in Random Access Memory (RAM), memory, Read Only Memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
Finally, it should also be noted that, herein, relationships such as first and second, etc., are intended only to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms include, or any other variation is intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The principle and the implementation of the present application are explained herein by applying specific examples, and the above description of the embodiments is only used to help understand the method and the core idea of the present application; meanwhile, for a person skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. An operation state switching method, comprising:
the processor executes a starting operation after acquiring the wake-up signal;
after the starting operation is finished, generating a wake-up instruction;
and sending the awakening instruction to the control component through the target bus so that the control component keeps the reset signal corresponding to the memory unchanged.
2. The method according to claim 1, further comprising, before the processor acquires the wake-up signal:
after a sleep signal is acquired, a sleep instruction is generated;
sending the sleep instruction to the control component through the target bus so that the control component keeps the reset signal unchanged.
3. The operating state switching method according to claim 1, wherein the generating of the wake-up instruction includes:
and generating a clock enable signal setting instruction, and generating the awakening instruction by using the clock enable signal setting instruction.
4. The operation state switching method according to claim 1, wherein the sending the wake-up command to the control unit through the target bus so that the control unit keeps the reset signal unchanged comprises:
and sending the awakening instruction to a single chip microcomputer through a target bus so that the single chip microcomputer can keep the reset signal unchanged.
5. The operation state switching method according to any one of claims 1 to 4, characterized by further comprising:
executing the starting operation after detecting a starting signal;
after the starting operation is finished, generating a starting instruction;
and sending the starting-up instruction to the control component through the target bus so that the control component adjusts the reset signal.
6. The operating state switching method according to claim 5, wherein the sending the boot instruction to the control unit through the target bus so that the control unit adjusts the reset signal comprises:
and sending the starting-up instruction to the control component through the target bus so that the control component sends low-level impact to a target port corresponding to the reset signal.
7. The operation state switching method according to claim 1, further comprising, after sending the wake-up command to the control unit through the target bus:
and carrying out data interaction with the memory.
8. An operation state switching apparatus, comprising:
the acquisition module is used for executing starting operation after the processor acquires the wake-up signal;
the instruction generation module is used for generating a wake-up instruction after the start operation is finished;
and the signal holding module is used for sending the awakening instruction to the control component through the target bus so that the control component can keep the reset signal corresponding to the memory unchanged.
9. An electronic device comprising a memory and a processor, wherein:
the memory is used for storing a computer program;
the processor is configured to execute the computer program to implement the operation state switching method according to any one of claims 1 to 7.
10. A computer-readable storage medium for storing a computer program, wherein the computer program, when executed by a processor, implements the operating state switching method according to any one of claims 1 to 7.
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| CN115118534B (en) * | 2022-06-07 | 2023-11-17 | 合肥移瑞通信技术有限公司 | Low-power-consumption state control method, device, terminal and storage medium of MBB equipment |
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| WO2022121475A1 (en) | 2022-06-16 |
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