TW541453B - Power saving device for computer and method thereof - Google Patents

Abstract

The present invention relates to a type of computer power saving system and a method thereof. The event controller controls the system controller to make the central processing unit (CPU) run the first power management procedure so that the state of the CPU and the state of the system controller at the time are stored into the memory. Then, the system controller and the CPU are left idle before lowering the host clock frequency. Finally, the CPU and the system controller are activated again and the second power management procedure is run. By changing the host clock frequency, the bus operating frequency is changed and, as a result, the power loss of the whole computer system, including CPU, memory, system controller, and video circuitry, is changed.

Description

541453 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a computer system, and more particularly, to a power-saving device and method for a portable computer. [Background of the Invention] For computer users, portable computers are an increasingly popular choice. The portable computer has the advantage of being convenient to carry, and thus foreshadows the consumer demand for extending the life of the operating battery used in the portable computer. Regardless of whether this need is achieved through improved battery manufacturing technology or the use of more power-efficient components. A conventional method for extending the battery life of a portable computer is to set a sleep mode on the portable computer system. In this sleep mode, if the user has not used the portable computer for a period of time, the Central Processing Unit (CPU) will store the current state of the computer into the memory. After that, the central processing unit enters a waiting state (s u s p e n d s t a t e). The central processing unit consumes only a small amount of power while waiting to be installed. In the waiting state, the display panel of the notebook computer will be closed, the speed of the disk drive will slow down, and the system bus (bu s) will enter the idle state (丨 d 丨 estat ^). The Dynamic Random Acess Memory (DRAM) is also in self-refresh mode. Any external action ’, such as a command from a keyboard or pointing device (po i n t i ng device), will, wake up, computer, randomize the bus and dynamics

541453 V. Description of the invention (2) Access the memory to restore the original working state, and make the central processing unit leave the waiting state. After that, the central processing unit opens the display panel, increases the speed of the disk drive, and restores the state before the central processing unit, and continues to perform actions that were not completed when the sleep mode was entered.

Computer manufacturers consider the central processing unit to be the most power-hungry component of the entire computer system. The manufacturer of the central processing unit also provides many methods to save the power consumed by the central processing unit. For example: By changing the built-in multiplier of the internal phase-lock loop (PLL) circuit in the central processing unit, the operating clock frequency is adjusted. In addition, The operating voltage of the central processing unit can also be changed. When the central processing unit is operating at a lower clock speed or a lower operating voltage, it will reduce the power it consumes. For the average user, the central processing unit performs tasks at a slower speed without any inconvenience.

However, the central processing unit is just one of many components of a portable computer. System buses, dynamic random access memory, and video chips also consume power. When the internal operating frequency of the central processing unit is slowed down, if these components can also be slowed down, excess power can be saved. However, in the existing personal computer, if the operating frequency of these components is changed without changing the clock of the bus in advance, the central processing unit will fail, and the operation of the components using the system bus such as the image chip and chip will be caused. [Objective and Summary of the Invention]

Page 5 541453 V. Description of the invention (3) In view of this, the object of the present invention is to provide a device and method capable of changing the operating frequency of a bus in a computer system, and used to save Power consumed by components. According to the purpose of the present invention, a computer power-saving system and method are provided. The system includes: a system controller for controlling a bus, a central processing unit, a memory, a first power management program, a second power management program, Clock generator and event controller. The system controller uses the host clock signal to determine the operating frequency of the bus. The clock generator is used to generate the master clock signal. The first power management program has a computer code for storing state data of the computer system in the memory at the time, and placing the system controller in an idle state. The second power management program can use the status data stored in the memory to restore the status of the computer system. The event controller sends an interrupt signal to the system controller, so that the central processing unit executes the first power management program, and stores the state of the central processing unit and the system controller at the time to a location reserved in the memory in advance. After that, the system controller and the central processing unit are placed in an idle state. The event controller operates the clock generator to change the frequency of the host clock signal. When the frequency of the host clock signal changes, the central processing unit and the system controller are started. After that, the central processing unit is caused to execute a second power management program. When the central processing unit and the system controller are idle, changing the frequency of the host clock signal can prevent the operation of the system controller and the central processing unit from failing. In addition, by changing the frequency of the host clock, the operating frequency of the bus will also change. The entire computer system, including the central processing unit, memory, system controller, and video circuit

541453 V. Description of the invention (4) The power loss also changes accordingly. The advantage of the present invention is that the event controller can change the operating frequency of all components in the computer system when the components are in an idle state. In this way, components can be prevented from failing by changing the operating clock. When components operate at lower frequencies, computer systems consume less power. In addition, when the components work at full speed, the computer system will regain full power. Moreover, if the core voltage of a component in a computer system is allowed to be adjusted, the event controller will reduce the core voltage of the component when the component is operating at a lower frequency. In this way, the power loss of the component will be further reduced. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail with reference to the accompanying drawings. [Preferred Embodiment] Please refer to FIG. 1, which shows a functional block diagram of a computer system 10 proposed by the present invention. In a preferred embodiment, the computer system 10 is a portable computer that can execute the power saving method proposed by the present invention. The computer system 10 includes the following components: a central processing unit (CPU) 20, a system controller 30, a clock generator 40, a memory 50, and an image circuit ( video circuitry) 6 0 and event controller (eventcontr ο 1 1 er) 7 0. The system controller controls each bus (bu s) in the computer system so that the computer system

541453 V. Description of the invention (5) Each component in the (5) can be used as the interface between the system controller 3 〇 such as: the front side bus of the central processing unit 20 (fr 00nt side l 32, the memory bus of the memory 50 (Memory bus) 35. Video bus 36 (route 60). These buses 32 3 6 enable each component 20, 50, and 60 in the computer system to be controlled by the system to communicate with each other. Among them, The system controller 3 is usually a commercial chip dedicated to the central processing unit 20. The clock generator 40 is used to generate various clock signals to the computer system for different components. For example: the central processing unit clock signal 2 4, clock The clock signal 54, the host clock signal 34, and the image clock signal 64. The processing unit clock signal 24 determines the internal rate of the central processing unit 20. The higher the frequency of the central processing unit clock signal 24, the more it can execute every second at the center. The greater the number of instructions. However, this will lead to power consumption. On the contrary, if the frequency of the clock of the central processing unit is reduced, then the central processing unit 20 will consume less power. Memory time The frequency of the clock signal 54 will also change the speed consumption of the memory 50, and the frequency of the image clock signal 64 will also change the video circuit power and power consumption. In addition, the frequency of the host clock signal 34 will also be controlled uniformly. The working speed and power consumption of the device 30. Because the system control system is used to control the bus 3 2, 3 5 and 36, changing the frequency of the main clock will change the working frequency of the bus 32, 35 and 36 . 'Decrease clock signal 34 will slow down the speed of buses 32, 35 and 36 and the brain system 10 will work, and will reduce the power of the computer system. Increasing the host clock signal 34 will increase the bus 32 , 35, and 36. For example) US) Video, 35 and controller 30 are designed for each memory in the system. The central working frequency unit sends more signals 24 for the same reason, and the speed of the power changes the controller 30 signals 34 slower the host reduces the power consumption. degree. Also 541453 V. Description of the invention (6) Therefore, the working power of the computer system 10 is increased. The power consumption of computer systems will also increase. The memory 50 includes a dynamic random access memory (DRAM) 5 Oa and a read only memory (ROM) 50b. The dynamic random access memory 50a can be operated in a normal mode for performing reading or writing operations from the bus 35. The dynamic random access memory 50a also has a self-refresh mode (sel f-re fresh mode), which periodically performs an update operation 'to maintain the correctness of its stored content. When the dynamic random access memory 50a is interposed, it will still perform the update operation, which has ensured that its stored content is not lost. The read-only memory 50b is used to permanently protect the power management program of the computer system 10, and includes a Basic Input / Output System (BIOS) 52b. The basic input-output system 52b includes a save t0 memory computer code 5 5b and a self-memory rest (recommendation) computer code 56b. * When the central processing unit 2 〇 executes the memory computer code 5 5 b, it will cause the central processing unit 2 0 to store the current state of the central processing unit 2 0 and the system controller 30 and the image circuit 60 in the dynamic state. In the random access memory 50a, the system controller 30 is instructed to perform a power wait (suspend) operation. After that, the system controller 30 puts the central processing unit 20 into a suspend state, puts the dynamic random access memory 50a into a self-refresh mode (seif_refresh mode), and leaves the video circuit 60 idle. After that, the system controller 3 〇 enters the idle state (丨 d i e

Page 9 541453 V. Description of the invention (7) state). When the central processing unit 20 is in a waiting state, its work must be suspended. When the central processing unit 20 is not performing work, it only consumes a small amount of power. In the same way, the video circuit 60 and the system controller 30 in the idle state are basically turned off. They both consume only a small amount of power and simply wait for the "wake π" signal. When the central processing unit 20 executes the self-memory recovery computer code 5 6 b, it uses the data previously stored in the dynamic random access memory 5 0 a to restore the data of the central processing unit 20, the system controller 30, and the image circuit 60. Previous state. After that, the central processing unit 20 will resume execution of the tasks that were not completed when the computer code 5 6 b was stored in the memory. When the stored memory computer code 5 5 b is used to execute the stored memory program and the self-memory restored computer code 5 6 b is used to execute the self-memory restored program, it is not only the central processing unit 2 0, which can be stored and read. Status data of the system controller 30, the dynamic random access memory 50a, and the video circuit 60. If necessary, the state of other components in the computer system 10 may also be stored. In short, these two programs can execute reading and writing any state data required when the computer system 10 enters the waiting state or resumes the work. After that, the system controller 30 enters the idle state (i d 1 e s t a t e). The functions of saving programs and restoring programs from memory are well known to those skilled in the art. The event controller 70 is used to execute the method of the present invention, and includes a processing circuit 72, a timer 74, a state indicator 76, and a switch 78. The processing circuit 72 is used to perform various tasks required by the power saving method of the present invention (the details will be disclosed below). The processing circuit 72 may be a process

541453 V. Description of the invention (8) Programmable Logic Array (PLA), — micro-controller or even a relatively simple processor (command), such as: 8051 processor. 5 自 忆 体 7 5 is used to store program code and program data of the processing circuit 7 2 'for example, p0wer state variable, 7 5a, to restore the current power storage state of the computer system 10. The timer 7 4 provides a clock signal required for the processing circuit 7 2 to operate. In this way, the operation of the processing circuit 72 can be independent of the clock generator 40. The status indicator 76 is used to indicate the current power saving status of the computer system 10, for example, it may be a light emitting diode (LED). For example, when the status indicator 76 is illuminated, it indicates that the computer system is in the power saving mode and uses the slower clock frequency provided by the clock generator 40 to work. Conversely, if the status indicator 76 is off, it means that the computer system is using the clock generation = the maximum clock frequency provided to work. The event controller 70 controls the indication state of the controller 76. Finally, the user triggers the power saving state of the computer system 10 with the switch 78. Please refer to FIG. 2 and FIG. 2 for a flowchart of the operation of the computer system 10. As mentioned above, the system controller is used for the proposed power saving method. The method includes the following steps: Control the current month 100: Start, turn on the computer system 10. Set the power state variable 75a as the initial state, for example: Off (0FF). According to the power state indicator 76, the clock generator 40 generates the maximum frequency: the clock signals 2 4 '3 4 and 6 4. The dynamic random access memory is in the normal state 20, 30 and 60 all work normally. Then proceed to step 102. 'All where

Page 11 541453 V. Description of the invention (9) 1 0 2: If the user presses the switch, the switch 7 8 sends a switch press signal to the processing circuit 72. When the switch presses the signal, it goes to step 104 ° 1 0 4: change the value of the power state variable 7 5 a. For example: power state variable 75a = NOT (power state variable 75a). Then proceed to step 106. 106 ·· The event controller 70 outputs an interrupt request (interrupt r e q u e s t) 3 7 to the system controller 30. This is a System Control Interrupt (SCI), so it has very low priority. Then proceed to step 108. 1 0 8: When the system control interrupt has low priority, the system controller 30 continues to execute other wait interrupts until the system is no longer busy. At this time, the event controller 70 simply waits for a wait signal 73 from the system controller 30. This signal indicates that the system controller 30 has completed the power standby procedure. When the system is no longer busy, skip to step 1 10. 1 1 ◦: The system controller 30 sends an interrupt request 2 3 to the central processing unit 20, and this central processing unit interrupt request 23 is a system management interrupt (System

Management Interrupt (SMI), which is quickly executed by the central processing unit 20. This system management interruption 23 will cause the central processing unit 2 0 to execute the storage of the computer code 5 5 b. Then, the states of the central processing unit 20, the smart circuit 60, and the system controller 30 will be simultaneously stored in the dynamic random access memory 50a. The system controller 30 causes the video circuit 60 to enter the sub-state, and the dynamic random access memory 50a enters the self-resetting state, and notifies the event controller 70 that the power waiting process has been completed. Of course

541453 V. After the description of the invention (ίο), the event controller 70 makes the system controller 30 idle. Proceed to step 112. · 1 1 2 ·· If the power state variable 7 5 a indicates whether the power saving mode should be used, if yes, skip to step 1 1 4 1; otherwise, skip to step 1 1 4 h.

1 1 4 1 · Use power saving mode. The event controller 70 sets the clock signals 24, 34, 54 and 64 to a lower frequency with a clock control signal 47. Example ^: If the clock generator 40 generates a 1 3 3 Μ Η z signal to the memory clock signal 5 4 and the host clock signal 34, the event controller 70 will use the clock control signal 47 to make the clock The generator 40 generates a clock signal of 60 MHz to set the clock signals 24, 34, and 54. These lower frequency clock signals 24, 34 and 54 will reduce the total power consumption of the computer system 10. It should be noted that reducing the frequency of the host clock h 3 34 will reduce the operating frequency of the corresponding front bus 3 2, memory bus 3 5 and image bus 36. The event controller 7 q can choose to adjust only one, a few of the clock signals 24, 34, 54 and 64 or all the clock signals. The event controller 70 decides how to adjust the clock signals 24, 34, 54 and 64 according to the capabilities of the hardware and the limitations of the components 20, 30, 40, 50, and 60. When the central processing unit 20 is put into a waiting state, and the image circuit 60 and the system controller 30 are both in an idle state, changing their relative clock signals 24, 64, and 34 does not cause these components Failure. Similarly, when the dynamic random access memory 50a is in the update self-renewing mode, the memory clock signal 54 used by it can also be safely changed. Skip to steps 1 1 6. 1 1 4 h: Use the maximum computer system power. Turn off power saving mode. The event controller 70 uses the clock control signal 4 7 to set the clock signal 2 4, 3 4, 5 4 and

Page 13 541453 V. Description of the invention (11) 6 4 to their respective highest possible frequencies. Go to step 1 丨 6. 116: The event controller 70 outputs an interrupt request 37 to the system controller 30 'to take the system controller 30 out of the idle state. The system controller 3 executes the recovery procedure from the standby state, and returns the dynamic random access memory 5a to the normal mode operation ', wakes the image circuit 6o, and causes the central processing unit 2o to leave the standby state. When the central processing unit 20 leaves the waiting state, it executes a reply code 56b from the memory. Unless the computer system 10 is operating at a lower or higher speed, the computer system 10 will return to the state before step 1-6. Go to step 1 1 8. ~ 1 1 8: Use the power state variable 7 5 a to set the state of the status indicator 7 6. Skip to step 102. Shown in Figure 1 is a Thunderbolt system that supports asynchronous system clocks between the system controller 30 and the central processing unit 20, smemory body 50, and image circuit 60 !. . In theory, all the computer systems i " :: work at the same frequency, so the computer system 10 designed as shown in Figure 1 is the most common example. Actually. Computer systems that use synchronized clock signals will be easier to design. Please refer to FIG. 3 for a functional block diagram of f, 卞, OX ΓΊI A7F * 1 ^ jy _ computer system 2 1 〇. The second computer system 2 and 0 are all the same as 1: except that the clock generator 2 40 only generates the host system $$ ## 2 3 4 of the electric system \ 电 control system 2 30. After that, the system controller 2 〇 uses the host clock signal 2 3 4 to generate the central processing unit 22 clock used by the central household 1 unit clock signal 2 24, the memory clock used by the memory 2 50 0 = 254 And the image clock signal "^. Event.

Page 14 541453 V. Description of the invention (12) The generator 2 7 0 can only use the clock control signal 24 7 to adjust the frequency of the host clock signal 2 3 4. Changing the frequency of the host clock signal 2 3 4 will not only change the frequency of the front side bus 2 3 2, the memory bus 2 3 5 and the image bus 2 3 6 but also the central processing unit 220, memory 250 and The internal operating frequency of the image circuit 260.

Although the above-disclosed embodiment only uses a portable computer as an example, for anyone skilled in the art, the device and method proposed by the present invention can be easily applied to a desktop computer. The device and method provided by the present invention are applicable to any computer system that can achieve the purpose of saving power by changing the operating frequency of a bus or a component without causing the entire system to fail. And, if the components in the system allow it, the event controllers 70 and 2 0 of the present invention can also be used to control the core operating voltage of the components to further manage the power consumption of the system. [Effect of the invention]

A power-saving device and method for a computer disclosed in the above embodiments of the present invention sets an event controller in a computer system. Contrary to conventional techniques, the event controller has its own timer. It can also generate a clock signal by the clock generator without affecting itself. The event controller waits for the central processing unit to wait for other related chips to enter the idle state and the dynamic random access memory enters the update self-renewing mode. The event controller will change the clock signals of the central processing unit and related chips to adjust the components. electricity demand. When these components are idle, changing the frequency of their clock signals will not invalidate them. Event control

Page 15 541453 V. Description of the invention (13) The controller will start the central processing unit and related chips, and the computer system restarts from the state where it stopped before. The entire process is almost instantaneous ^, so it is quite convenient for users to use. In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications without departing from the spirit and scope of the present invention. Changes and retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.

Page 16 541453 Brief description of the drawings [Simplified description of the drawings] Figure 1 shows a functional block diagram of the computer system proposed by the present invention. Figure 2 shows a flowchart of the operation of the computer system. FIG. 3 is a functional block diagram of a second computer system according to the present invention. [Illustration of figure number] 10: Computer system 20, 220: Central processing unit

23: Central processing unit interrupt request 24, 224: Central processing unit clock signal 3 0, 2 3 0: System controller 3 2, 2 3 2: Front side bus 3 4, 2, 3 4: Host clock signal 3 5 , 2 3 5: memory bus 3 6, 2 3 6: video bus 3 7: interrupt request 4 0, 2 4 0: clock generator 4 7, 2 4 7: clock control signal 5 0, 2 5 0Memory

5 0 a: dynamic random processing memory 5 0 b: read-only memory 52 b: basic input-output system 5 4, 2 5 4: memory clock signal

Page 17 541453 Brief description of the diagram 5 5 b · Store in computer code 5 6 b: Restore computer code from memory

60, 260 video circuit 64, 264 video clock signal 70, 270 event controller 7 2: processing circuit 73: wait signal 74: timer 75: memory 75a: power state variable 76: status indicator 78: switch 2 1 0: Second computer system 第 18 页

Claims (1)

541453 VI. Patent application: The system controller works at a lower frequency, which saves power. Before the system controller is idle, the host clock signal is changed to the second frequency to avoid the system controller. Failure. 2. The power-saving method described in item 1 of the scope of patent application, wherein the system controller operates at the lower frequency, which will cause the group of buses to operate at a lower operating frequency, thereby saving power . 3. The power saving method described in item 1 of the scope of patent application, further comprising: before the central processing unit is idle, causing the clock generator to change the master The machine clock signal is the second frequency; and when the clock generator changes the host clock signal to the second frequency, the central processing unit is started; wherein, before the central processing unit is idle, the host is changed first. The pulse signal at the second frequency can prevent the central processing unit from failing. 4. The power saving method according to item 3 of the scope of patent application, wherein the group of buses includes a front side bus (fr ο ntsidebus), the central processing unit is electrically coupled to the front side bus, and the central processing The unit uses a central processing unit clock signal, the central processing unit clock signal has a third frequency, the clock generator generates the central processing unit clock signal, and before starting the central processing unit, the clock generator Change the clock signal of the central processing unit to a fourth frequency, the fourth frequency being lower than the third frequency; wherein the frequency of the clock signal of the central processing unit is changed before the central processing unit is idle to avoid the The central processing unit fails. By using a lower frequency of the central processing unit's clock signal, it can save Page 20 541453 6. Scope of patent application Power saving. 5. The power-saving method according to item 1 of the scope of patent application, wherein the group of buses includes a memory bus, and the memory system and the memory bus are electrically connected to each other when the memory uses a memory Clock signal 'The clock signal of the memory has a fifth frequency. The clock generator generates the clock signal of the memory. Before starting the system controller, the clock generator changes the clock signal of the memory to a A sixth frequency, which is lower than the fifth frequency; wherein, by using a lower frequency of the memory clock signal, power can be saved. 6. The power saving method according to item 5 of the scope of patent application, wherein the memory system is a dynamic random access memory (Dynamic R and OM Access Memory, DRAM), and the power saving method further includes: Before the clock generator changes the clock signal of the memory to the sixth frequency, put the dynamic random access memory in a self-refresh mode; and the clock generator changes the clock of the memory After the signal is at the sixth frequency, the dynamic random access memory is restored to a normal mode operation. 7. The power saving method as described in item 1 of the scope of patent application, wherein the computer system further includes a video circuit, and the group of buses includes an image bus, and the image circuit uses the image bus Electrically coupled to the system controller, the image circuit uses an image clock signal, the image clock signal has a seventh frequency, and the clock generator generates the image clock signal before starting the system controller , The clock is generated Page 21 541453 VI. Patent application scope The system controller is placed in an idle mode (id 1 em ode); > A second power management program is stored in the memory. The second power management program is It includes a second computer code for recovering the state of the computer system by using the status data previously stored in the memory; The system controller is electrically coupled; and An event controller is electrically coupled to the system controller and the clock generator. The event controller performs the following functions: Sends a first interrupt signal to the system controller to make the system controller The central processing unit executes the first power management program; when the system controller is in the idle mode, the clock generator changes the host clock signal to a second frequency; the clock generator changes the host clock After the signal reaches the second frequency, the system controller is started; and the central processing unit executes the second power management program; wherein when the system controller is in the idle mode, the host clock signal is changed to The second frequency, the event controller can prevent the system controller from failing; Among them, by changing the frequency of the clock signal of the host, the operating frequency of one system controller of the system controller will also change, and the total power consumption of the computer system will also change accordingly. 10. The computer system described in item 9 of the scope of patent application, in which Page 23 541453 6. Scope of patent application When the operating frequency of the system controller of the system controller is changed, one of the buses will also change its operating frequency, and the total power consumption of the computer system will also change accordingly. 11. The computer system according to item 9 of the scope of the patent application, wherein the first power management program further includes a third computer code for placing the central processing unit in a suspended state and placing the host After the clock signal is changed to the second frequency, the event controller starts the central processing unit; wherein, when the central processing unit is in the waiting state, the event controller changes the host clock signal to the second frequency. Avoid failure of this central processing unit. 12. The computer system according to item 9 of the scope of patent application, wherein the group of buses includes a front side bus, the central processing unit is electrically coupled to the front side bus, and the central processing unit uses a central processing unit Clock signal. The clock signal of the central processing unit has a third frequency. The clock signal of the central processing unit determines an internal operating frequency of the central processing unit. The clock generator generates the clock signal of the central processing unit. Before starting the central processing unit, the event controller causes the clock generator to change the frequency of the central processing unit's clock signal to a fourth frequency; wherein, before placing the central processing unit in a waiting state, the first The frequency of the central processing unit clock signal can prevent the central processing unit from failing. By changing the built-in operating frequency of the central processing unit, the total power consumption of the central processing unit can be changed. 13. The computer system according to item 9 of the scope of patent application, wherein the set of buses includes a memory bus, and the memory system and the memory bus Page 24 541453 6. Patent application: The current is electrically coupled. The memory uses a memory clock signal. The memory clock signal has a fifth frequency. The clock generator generates the memory clock. Signal, before starting the system controller, the clock generator changes the clock signal of the memory to a sixth frequency; wherein the total power consumption of the memory can be changed by the frequency of the clock signal of the memory . 14. The computer system according to item 13 of the scope of patent application, wherein the memory includes a dynamic random access memory, and the first power management program further includes a fourth computer code for storing the dynamic random storage. Taking the memory into a self-renewing mode. After changing the memory clock signal to the sixth frequency, the event controller returns the dynamic random access memory to a normal mode operation. 15. The computer system according to item 9 of the scope of patent application, wherein the computer system further includes an image circuit, the group of buses includes an image bus, and the image circuit is connected to the system controller by the image bus Electrically coupled, the image circuit uses an image clock signal, the image clock signal has a seventh frequency, the clock generator generates the image clock signal, and before the system controller is activated, the event controller The clock generator is caused to change the frequency of the image clock signal to an eighth frequency; wherein, by changing the frequency of the image clock signal, the total power consumption of the image circuit can be changed. 16. The computer system according to item 15 of the scope of patent application, wherein the first power management program further includes a fifth computer code for placing the image circuit in an idle mode, and when the image clock signal is changed After the eighth frequency, the event controller activates the image circuit; Page 25 541453 6. Scope of patent application When the road is in the idle mode, change the video clock signal to the eighth frequency to avoid the video circuit failure. 17. The computer system according to item 9 of the scope of patent application, wherein the event controller includes a processing circuit and a timer, and the timer is used to provide a timing signal. To the processing circuit. Page 26