TW541453B - Power saving device for computer and method thereof - Google Patents
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541453 五、發明說明(1) 【發明領域】 本發明是有關於一種電腦系統,且特別是有關於一種 用於可攜式電腦之省電裝置及方法。 【發明背景】 對電腦使用者而言,可攜式電腦(portable computer )是個越來越受歡迎的選擇。可攜式電腦具有攜 帶方便的優點,也因此預示著消費者對延長可攜式電腦所 使用之工作電池(operational battery)的壽命的需 求。而不論此項需求是藉由改進電池製造技術或是使用更 省電的元件來達成的。 一個習知用以延長可攜式電腦電池壽命的方法是,於 可攜式電腦系統設定一睡眠模式(sleep mode )。在此睡 眠模式下,如果使用者在一段時間内未使用可攜式電腦的 話,中央處理單元(Central Processing Unit, CPU)會 將電腦當時的狀態儲存至記憶體中。之後,中央處理單元 就進入等待狀態(s u s p e n d s t a t e )。在等待裝態時,中 央處理單元只會消耗很少量的電力。在等待狀態時,筆記 型電腦的顯示面板會被關閉、磁碟機的轉速會變慢,系統 匯流排(bu s )會進入閒置狀態(丨d丨e s t a t ^ ),動態隨 機存取 °己憶體(Dynamic Random Acess Memory,DRAM) 也處於自我更新模式(self-refresh mode)。任何一個 外來的動作’例如··來自鍵盤或是指向元件(po i n t i ng device )的指令,就會,,喚醒,,電腦,使匯流排跟動態隨機541453 V. Description of the Invention (1) [Field of the Invention] The present invention relates to a computer system, and more particularly, to a power-saving device and method for a portable computer. [Background of the Invention] For computer users, portable computers are an increasingly popular choice. The portable computer has the advantage of being convenient to carry, and thus foreshadows the consumer demand for extending the life of the operating battery used in the portable computer. Regardless of whether this need is achieved through improved battery manufacturing technology or the use of more power-efficient components. A conventional method for extending the battery life of a portable computer is to set a sleep mode on the portable computer system. In this sleep mode, if the user has not used the portable computer for a period of time, the Central Processing Unit (CPU) will store the current state of the computer into the memory. After that, the central processing unit enters a waiting state (s u s p e n d s t a t e). The central processing unit consumes only a small amount of power while waiting to be installed. In the waiting state, the display panel of the notebook computer will be closed, the speed of the disk drive will slow down, and the system bus (bu s) will enter the idle state (丨 d 丨 estat ^). The Dynamic Random Acess Memory (DRAM) is also in self-refresh mode. Any external action ’, such as a command from a keyboard or pointing device (po i n t i ng device), will, wake up, computer, randomize the bus and dynamics
541453 五、發明說明(2) 存取記憶體回復原來的工作狀態,以及使中央處理單元離 開等待狀態。之後,中央處理單元會打開顯示面板,增加 磁碟機的轉速以及回復中央處理單元之前的狀態,並且繼 續執行之前進入睡眠模式時尚未執行完畢的動作。541453 V. Description of the invention (2) Access the memory to restore the original working state, and make the central processing unit leave the waiting state. After that, the central processing unit opens the display panel, increases the speed of the disk drive, and restores the state before the central processing unit, and continues to perform actions that were not completed when the sleep mode was entered.
電腦製造廠商認為中央處理單元是整個電腦系統中最 耗電的元件。而中央處理單元的製造廠商也提供了許多方 法來節省中央處理單元所消耗的電力。例如:藉由改變中 央處理單元中之内部鎖相迴路(Phase-Lock Loop, PLL) 電路之内建倍頻器(multiplier),來調整操作時脈頻率 (operating clock frequency ) 0 除此之外,也可改變 中央處理單元之工作電壓。當中央處理單元以較低之時脈 速度或是較低之工作電壓工作時,便會減少它所消耗的電 力。對一般的使用者而言,中央處理單元以較慢的速度來 執行工作並不會造成任何的不便。Computer manufacturers consider the central processing unit to be the most power-hungry component of the entire computer system. The manufacturer of the central processing unit also provides many methods to save the power consumed by the central processing unit. For example: By changing the built-in multiplier of the internal phase-lock loop (PLL) circuit in the central processing unit, the operating clock frequency is adjusted. In addition, The operating voltage of the central processing unit can also be changed. When the central processing unit is operating at a lower clock speed or a lower operating voltage, it will reduce the power it consumes. For the average user, the central processing unit performs tasks at a slower speed without any inconvenience.
然而,中央處理單元只是可攜式電腦眾多元件之一。 系統匯流排、動態隨機存取記憶體以及影像晶片也都會消 耗電力。當中央處理單元的内部工作頻率減慢時,如果這 些元件的工作速度也可以減慢的話,就可以省下多餘的電 力。但是,在現有的個人電腦中,如果沒有預先改變匯流 排的時脈就改變這些元件的工作頻率的話,會使中央處理 單元當機失效、影像晶片以及晶片這些使用系統匯流排的 元件的運作。 【發明目的及概述】However, the central processing unit is just one of many components of a portable computer. System buses, dynamic random access memory, and video chips also consume power. When the internal operating frequency of the central processing unit is slowed down, if these components can also be slowed down, excess power can be saved. However, in the existing personal computer, if the operating frequency of these components is changed without changing the clock of the bus in advance, the central processing unit will fail, and the operation of the components using the system bus such as the image chip and chip will be caused. [Objective and Summary of the Invention]
第5頁 541453 五、發明說明(3) 有鑑於此,本發明的目的就是在提供一種可以改變電 腦系統中的匯流排的工作頻率的裝置及其方法,用以節省 電腦系統中使用匯流排的元件所消耗的電力。 根據本發明的目的,提出一種電腦的省電系統及其方 法,此系統包括:用以控制匯流排之系統控制器、中央處 理單元、記憶體、第一電力管理程序、第二電力管理程 式、時脈產生器以及事件控制器。系統控制器藉由主機時 脈信號來決定匯流排的工作頻率。時脈產生器則用以產生 主機時脈信號。 第一電力管理程序具有電腦碼,用以將當時電腦系統 的狀態資料儲存至記憶體中,以及將系統控制器置於閒置 狀態。第二電力管理程序可使用儲存於記憶體中的狀態資 料回復電腦系統的狀態。事件控制器發送中斷信號至系統 控制器,使中央處理單元執行第一電力管理程序,將當時 中央處理單元以及系統控制器之狀態儲存至記憶體預先保 留的位置。之後,將系統控制器及中央處理單元置於閒置 狀態。事件控制器操縱時脈產生器,用以改變主機時脈信 號的頻率。當主機時脈信號的頻率改變之後,啟動中央處 理單元以及系統控制器。之後,使中央處理單元執行第二 電力管理程序。在中央處理單元以及系統控制器處於閒置 狀態時改變主機時脈信號的頻率,如此可防止系統控制器 以及中央處理單元的運作失效。此外,藉由改變主機時脈 之頻率,匯流排之工作頻率也隨之改變,整個電腦系統, 包括中央處理單元、記憶體、系統控制器以及影像電路的Page 5 541453 V. Description of the invention (3) In view of this, the object of the present invention is to provide a device and method capable of changing the operating frequency of a bus in a computer system, and used to save Power consumed by components. According to the purpose of the present invention, a computer power-saving system and method are provided. The system includes: a system controller for controlling a bus, a central processing unit, a memory, a first power management program, a second power management program, Clock generator and event controller. The system controller uses the host clock signal to determine the operating frequency of the bus. The clock generator is used to generate the master clock signal. The first power management program has a computer code for storing state data of the computer system in the memory at the time, and placing the system controller in an idle state. The second power management program can use the status data stored in the memory to restore the status of the computer system. The event controller sends an interrupt signal to the system controller, so that the central processing unit executes the first power management program, and stores the state of the central processing unit and the system controller at the time to a location reserved in the memory in advance. After that, the system controller and the central processing unit are placed in an idle state. The event controller operates the clock generator to change the frequency of the host clock signal. When the frequency of the host clock signal changes, the central processing unit and the system controller are started. After that, the central processing unit is caused to execute a second power management program. When the central processing unit and the system controller are idle, changing the frequency of the host clock signal can prevent the operation of the system controller and the central processing unit from failing. In addition, by changing the frequency of the host clock, the operating frequency of the bus will also change. The entire computer system, including the central processing unit, memory, system controller, and video circuit
541453 五、發明說明(4) 電力損耗亦隨之改變。 本發明的優點在於事件控制器能夠在元件處於閒置狀 態時,改變電腦系統中所有元件的工作頻率。如此,可防 止元件因為改變工作時脈而失效。當元件以較低頻率工作 時,電腦系統會消耗較少的電力。除此之外,當構成元件 以全速工作的話,電腦系統將會回復全部的電力。而且, 如果電腦系統中,某元件的核心電壓是允許被調整的話, 事件控制器會在該元件以較低的頻率工作時,減低元件的 核心電壓(core voltage)。如此,將更加減少該元件的 電力損耗。 為讓本發明之上述目的、特徵、和優點能更明顯易 懂,下文特舉一較佳實施例,並配合所附圖式,作詳細說 明如下。 【較佳實施例】 請參照第1圖,其所繪示乃本發明所提出之電腦系統 1 0的功能方塊圖。在一較佳實施例中,此電腦系統1 0係為 一可執行本發明所提出之省電方法的可攜式電腦 (portable computer )。此電腦系統10包括以下元件·· 中央處理單元(Central Processing Unit, CPU) 20、系 統控帝J器(system controller ) 30 、日寺脈產生器(clock generator) 40、記憶體50、影像電路(video circuitry )6 0以及事件控制器(e v e n t c o n t r ο 1 1 e r ) 7 0。系統控制 器控制電腦系統中之各個匯流排(bu s ),使得電腦系統541453 V. Description of the invention (4) The power loss also changes accordingly. The advantage of the present invention is that the event controller can change the operating frequency of all components in the computer system when the components are in an idle state. In this way, components can be prevented from failing by changing the operating clock. When components operate at lower frequencies, computer systems consume less power. In addition, when the components work at full speed, the computer system will regain full power. Moreover, if the core voltage of a component in a computer system is allowed to be adjusted, the event controller will reduce the core voltage of the component when the component is operating at a lower frequency. In this way, the power loss of the component will be further reduced. In order to make the above-mentioned objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is exemplified below and described in detail with reference to the accompanying drawings. [Preferred Embodiment] Please refer to FIG. 1, which shows a functional block diagram of a computer system 10 proposed by the present invention. In a preferred embodiment, the computer system 10 is a portable computer that can execute the power saving method proposed by the present invention. The computer system 10 includes the following components: a central processing unit (CPU) 20, a system controller 30, a clock generator 40, a memory 50, and an image circuit ( video circuitry) 6 0 and event controller (eventcontr ο 1 1 er) 7 0. The system controller controls each bus (bu s) in the computer system so that the computer system
541453 五、發明說明(5) 中各個元件能夠藉由系統控制器3 〇當作介面彼此溝 如:中央處理單元20之前側匯流排(fr〇nt side l 32、記憶體50之記憶體匯流排(mem〇ry bus ) 35、 路60之影像匯流排(video bus)36。這些匯流排32 3 6使得電腦系統中各個元件2 〇、5 0及6 0可以系統控 為界面相互溝通。其中,系統控制器3 〇通常是專門 中央處理單元20的商業用晶片。 時脈產生器4 0用以產生各種時脈信號給電腦系 個不同的元件。例如:中央處理單元時脈信號2 4、 時脈信號54、主機時脈信號34以及影像時脈信號64 處理單元時脈信號24可決定中央處理單元2〇之内部 率。中央處理單元時脈信號24的頻率越高,中央處 每秒能夠執行的指令數目就越多。然而,如此會導 的電力消耗。相反的,如果降低中央處理單元時脈 的的頻率’則中央處理單元2 0會消耗較少的電力。 記憶體時脈信號5 4的頻率也會改變記憶體5 〇的速度 消耗,影像時脈信號6 4的頻率也會改變影像電路已〇 以及電力消耗,而且,主機時脈信號3 4的頻率也會 統控制器3 0的工作速度以及電力消耗。因為系統控 係用來控制匯流排3 2、3 5及3 6,所以改變主^ ’時脈 的頻率將會改變匯流排32、35及36的工作頻率。'減 時脈信號34將會因減慢匯流排32、35及36的速度而 腦系統1 0的工作電力,亦會減少電腦系統丨〇的電力 增加主機時脈信號34將增加匯流排32、35及36的速 通。例 )US ) 影像電 、35及 制器30 設計給 統中各 記憶體 。中央 工作頻 理單元 致更多 信號24 同理, 及電力 的速度 改變系 制器30 信號34 慢主機 減少電 消耗。 度。也 541453 五、發明說明(6) 因此增加電腦系統1 〇的工作電力。電腦系統丨〇的電力消 亦會隨之增加。 記憶體5 0包括了動態隨機存取記憶體(D y n a m i c Random Access Memory, DRAM ) 5 Oa 以及唯讀記憶體(Read Only Memory, R〇M)50b。動態隨機存取記憶體5〇a可以3 常模式(normal mode )工作,用以自匯流排35執行讀出 或寫入的工作。動態隨機存取記憶體5 〇 a也具有自我更新 更新模式(sel f-re fresh mode ),週期性地進行更新的 動作’以維持其所儲存的内容的正確性。當動態隨機存取 記憶體5 0 a間置時,它依然會進行更新的動作,已確保其 所儲存的内容沒有遺失。唯讀記憶體5 〇 b用以永久地保^ 電腦系統1 0的電力管理程序,且包括基本輸入輸出系統 (Basic Input/Output System,BIOS) 52b。此基本輸入 輸出系統52b包括存入記憶體(save t〇 memory)電腦碼 5 5b以及自記憶體回復(rest〇re f r〇m mem〇ry )電腦碼 56b。 * 當中央處理單元2 〇執行存入記憶體電腦碼5 5 b時,會 使中央處理單元2 0將中央處理單元2 〇本身以及系統控制器 3 0、影像電路6 0目前的狀態存入動態隨機存取記憶體5 〇 a 中’並指示下系統控制器3〇執行電力等待(p〇wer 〇n suspend )工作。之後,系統控制器3〇使中央處理單元2〇 進入等待狀態(suspend state ),使動態隨機存取記憶 體50a進入自我更新模式(seif_refresh mode)並使影像 電路6 0閒置。之後,系統控制器3 〇進入閒置狀態(丨d i e541453 V. Description of the invention (5) Each component in the (5) can be used as the interface between the system controller 3 〇 such as: the front side bus of the central processing unit 20 (fr 00nt side l 32, the memory bus of the memory 50 (Memory bus) 35. Video bus 36 (route 60). These buses 32 3 6 enable each component 20, 50, and 60 in the computer system to be controlled by the system to communicate with each other. Among them, The system controller 3 is usually a commercial chip dedicated to the central processing unit 20. The clock generator 40 is used to generate various clock signals to the computer system for different components. For example: the central processing unit clock signal 2 4, clock The clock signal 54, the host clock signal 34, and the image clock signal 64. The processing unit clock signal 24 determines the internal rate of the central processing unit 20. The higher the frequency of the central processing unit clock signal 24, the more it can execute every second at the center. The greater the number of instructions. However, this will lead to power consumption. On the contrary, if the frequency of the clock of the central processing unit is reduced, then the central processing unit 20 will consume less power. Memory time The frequency of the clock signal 54 will also change the speed consumption of the memory 50, and the frequency of the image clock signal 64 will also change the video circuit power and power consumption. In addition, the frequency of the host clock signal 34 will also be controlled uniformly. The working speed and power consumption of the device 30. Because the system control system is used to control the bus 3 2, 3 5 and 36, changing the frequency of the main clock will change the working frequency of the bus 32, 35 and 36 . 'Decrease clock signal 34 will slow down the speed of buses 32, 35 and 36 and the brain system 10 will work, and will reduce the power of the computer system. Increasing the host clock signal 34 will increase the bus 32 , 35, and 36. For example) US) Video, 35 and controller 30 are designed for each memory in the system. The central working frequency unit sends more signals 24 for the same reason, and the speed of the power changes the controller 30 signals 34 slower the host reduces the power consumption. degree. Also 541453 V. Description of the invention (6) Therefore, the working power of the computer system 10 is increased. The power consumption of computer systems will also increase. The memory 50 includes a dynamic random access memory (DRAM) 5 Oa and a read only memory (ROM) 50b. The dynamic random access memory 50a can be operated in a normal mode for performing reading or writing operations from the bus 35. The dynamic random access memory 50a also has a self-refresh mode (sel f-re fresh mode), which periodically performs an update operation 'to maintain the correctness of its stored content. When the dynamic random access memory 50a is interposed, it will still perform the update operation, which has ensured that its stored content is not lost. The read-only memory 50b is used to permanently protect the power management program of the computer system 10, and includes a Basic Input / Output System (BIOS) 52b. The basic input-output system 52b includes a save t0 memory computer code 5 5b and a self-memory rest (recommendation) computer code 56b. * When the central processing unit 2 〇 executes the memory computer code 5 5 b, it will cause the central processing unit 2 0 to store the current state of the central processing unit 2 0 and the system controller 30 and the image circuit 60 in the dynamic state. In the random access memory 50a, the system controller 30 is instructed to perform a power wait (suspend) operation. After that, the system controller 30 puts the central processing unit 20 into a suspend state, puts the dynamic random access memory 50a into a self-refresh mode (seif_refresh mode), and leaves the video circuit 60 idle. After that, the system controller 3 〇 enters the idle state (丨 d i e
第9頁 541453 五、發明說明(7) state )。當中央處理單元20處於等待狀態時,其工作必 須中止。當中央處理單元2 0沒有執行工作時,它只有消耗 很少量的電力。 同理,處於閒置狀態的影像電路6 0以及系統控制器3 0 基本上都被關閉,它們都只消耗很少量的電力並單純地等 待"喚醒π信號。當中央處理單元20執行自記憶體回復電腦 碼5 6 b時會使用之前存於動態隨機存取記憶體5 0 a中的資 料,以回復中央處理單元20、系統控制器30及影像電路60 的先前狀態。之後,中央處理單元2 0會重新開始執行在執 行存入記憶體電腦碼5 6 b時尚未完成的作業。利用存入記 憶體電腦碼5 5 b執行存入記憶體程序以及利用自記憶體回 復電腦碼5 6 b執行自記憶體回復程序時,能夠存入並讀取 的不只是中央處理單元2 0、系統控制器3 0、動態隨機存取 記憶體50a以及影像電路60的狀態資料。如果需要的話, 電腦系統1 0中其他元件的狀態也可以被儲存。簡言之,這 兩個程序可以執行讀取及寫入任何當電腦系統1 0進入等待 狀態或是重新執行工作時所需要的狀態資料。之後,系統 控制器3 0進入閒置狀態(i d 1 e s t a t e )。存入記憶體程序 以及自記憶體回復程序的功能皆為熟悉此技藝者所熟知。 事件控制器7 0係用以執行本發明之方法,其包括處理 電路(processing circuit)72 、計時器(timer)74 、狀態 指示器(state indicator)76 以及開關(switch)78。 處理電路7 2係用以執行本發明之省電方法所需的各項工作 (詳細内容將於下文中加以揭露)。處理電路72可為一可程Page 9 541453 V. Description of the invention (7) state). When the central processing unit 20 is in a waiting state, its work must be suspended. When the central processing unit 20 is not performing work, it only consumes a small amount of power. In the same way, the video circuit 60 and the system controller 30 in the idle state are basically turned off. They both consume only a small amount of power and simply wait for the "wake π" signal. When the central processing unit 20 executes the self-memory recovery computer code 5 6 b, it uses the data previously stored in the dynamic random access memory 5 0 a to restore the data of the central processing unit 20, the system controller 30, and the image circuit 60. Previous state. After that, the central processing unit 20 will resume execution of the tasks that were not completed when the computer code 5 6 b was stored in the memory. When the stored memory computer code 5 5 b is used to execute the stored memory program and the self-memory restored computer code 5 6 b is used to execute the self-memory restored program, it is not only the central processing unit 2 0, which can be stored and read. Status data of the system controller 30, the dynamic random access memory 50a, and the video circuit 60. If necessary, the state of other components in the computer system 10 may also be stored. In short, these two programs can execute reading and writing any state data required when the computer system 10 enters the waiting state or resumes the work. After that, the system controller 30 enters the idle state (i d 1 e s t a t e). The functions of saving programs and restoring programs from memory are well known to those skilled in the art. The event controller 70 is used to execute the method of the present invention, and includes a processing circuit 72, a timer 74, a state indicator 76, and a switch 78. The processing circuit 72 is used to perform various tasks required by the power saving method of the present invention (the details will be disclosed below). The processing circuit 72 may be a process
541453 五、發明說明(8) 式化邏輯陣列(Programmable Logic Array, PLA)、— 微控制器(micro-controller)或甚至是一個相對簡單的 處理器(processor),命j如:8051處理器。 5己憶體7 5係用以儲存程式碼以及處理電路7 2的程式資 料’例如.電力狀態變數(p0wer state variable) 、 7 5a,用以回復電腦系統1〇目前之電力儲存狀態。計時器 7 4提供處理電路7 2工作所需之時脈信號。如此,處理電路 7 2的運作可獨立於時脈產生器4 〇之外。狀態指示器7 6用以 指示用者目前電腦系統1 〇之省電狀態,例如其可為發光二 極體(Light Emitting Diode, LED )。例如,當狀態指 示器7 6發光時表示電腦系統丨〇正處於省電模式,並使用時 脈產生器4 0所提供之較慢的時脈頻率進行工作。相反地, 如果狀態指示器7 6關閉,表示電腦系統丨〇正使用時脈產生 =提供之最大時脈頻率進行工作。事件控制器70控制 扣不器76的指示狀態。最後,使用者以開關78觸發電 腦系統1 0的省電狀態。 請同時參照第2圖以及,第2圖繪示電腦系統1〇 運作之流程圖。由前文所述,系統控制器用以 所提出之省電方法,該方法包括下列步驟:徑制本發月 100 :開始,開啟電腦系統10。設定電力狀態變數75a 為初始狀態,例如:關閉(0FF)。依據電力狀能 指示器76、時脈產生器40產生最大頻率:時脈信號 2 4 ' 3 4和6 4、動態隨機存取記憶體處於正常 件20、30和60都正常工作。然後進入步驟1〇2、。'所有凡541453 V. Description of the invention (8) Programmable Logic Array (PLA), — micro-controller or even a relatively simple processor (command), such as: 8051 processor. 5 自 忆 体 7 5 is used to store program code and program data of the processing circuit 7 2 'for example, p0wer state variable, 7 5a, to restore the current power storage state of the computer system 10. The timer 7 4 provides a clock signal required for the processing circuit 7 2 to operate. In this way, the operation of the processing circuit 72 can be independent of the clock generator 40. The status indicator 76 is used to indicate the current power saving status of the computer system 10, for example, it may be a light emitting diode (LED). For example, when the status indicator 76 is illuminated, it indicates that the computer system is in the power saving mode and uses the slower clock frequency provided by the clock generator 40 to work. Conversely, if the status indicator 76 is off, it means that the computer system is using the clock generation = the maximum clock frequency provided to work. The event controller 70 controls the indication state of the controller 76. Finally, the user triggers the power saving state of the computer system 10 with the switch 78. Please refer to FIG. 2 and FIG. 2 for a flowchart of the operation of the computer system 10. As mentioned above, the system controller is used for the proposed power saving method. The method includes the following steps: Control the current month 100: Start, turn on the computer system 10. Set the power state variable 75a as the initial state, for example: Off (0FF). According to the power state indicator 76, the clock generator 40 generates the maximum frequency: the clock signals 2 4 '3 4 and 6 4. The dynamic random access memory is in the normal state 20, 30 and 60 all work normally. Then proceed to step 102. 'All where
第11頁 541453 五、發明說明(9) 1 0 2 :若使用者按上開關時,開關7 8發出開關按上信 號至處理電路7 2。當收到開關按上信號時,進入步驟 104 ° 1 0 4 :改變電力狀態變數7 5 a的值。例如:電力狀態變 數75a= NOT(電力狀態變數75a)。然後進入步驟106。 106 ··事件控制器70輸出中斷請求(interrupt r e q u e s t ) 3 7至系統控制器3 0。此為一系統控制中斷 (System Control Interrupt, SCI),因此具有非常低 的優先性。接著進入步驟1 0 8。 1 0 8 :當系統控制中斷具有低優先性時,系統控制器 3 0繼續執行其他的等待中斷,直到系統不再忙碌為止。此 時,事件控制器7 0只單純地等待系統控制器3 〇所發出之等 待信號7 3。該信號表示系統控制器3 〇已經完成電力等待程 序。當系統不再忙碌時,跳到步驟1 1 〇。 1 1 ◦:系統控制器3 0傳送中斷請求2 3給中央處理單元 20 ,此中央處理單元中斷請求23是系統管理中斷(SystemPage 11 541453 V. Description of the invention (9) 1 0 2: If the user presses the switch, the switch 7 8 sends a switch press signal to the processing circuit 72. When the switch presses the signal, it goes to step 104 ° 1 0 4: change the value of the power state variable 7 5 a. For example: power state variable 75a = NOT (power state variable 75a). Then proceed to step 106. 106 ·· The event controller 70 outputs an interrupt request (interrupt r e q u e s t) 3 7 to the system controller 30. This is a System Control Interrupt (SCI), so it has very low priority. Then proceed to step 108. 1 0 8: When the system control interrupt has low priority, the system controller 30 continues to execute other wait interrupts until the system is no longer busy. At this time, the event controller 70 simply waits for a wait signal 73 from the system controller 30. This signal indicates that the system controller 30 has completed the power standby procedure. When the system is no longer busy, skip to step 1 10. 1 1 ◦: The system controller 30 sends an interrupt request 2 3 to the central processing unit 20, and this central processing unit interrupt request 23 is a system management interrupt (System
Management Interrupt, SMI ),它會被中央處理單元2〇 快速地執行。此系統管理中斷2 3會使中央處理單元2 〇執 吕己憶體電腦碼5 5 b之儲存。然後,中央處理單元2 〇、巧 電路6 0以及系統控制器3 〇的狀態會同時被存入動態隨v 取記憶體5〇a中。系統控制器3〇會讓影像電路6〇進^入 子 狀態、動態隨機存取記憶體5 〇a進入自我更 ^ ),通知事件控制器70電力等待程序已經執行完畢。然Management Interrupt (SMI), which is quickly executed by the central processing unit 20. This system management interruption 23 will cause the central processing unit 2 0 to execute the storage of the computer code 5 5 b. Then, the states of the central processing unit 20, the smart circuit 60, and the system controller 30 will be simultaneously stored in the dynamic random access memory 50a. The system controller 30 causes the video circuit 60 to enter the sub-state, and the dynamic random access memory 50a enters the self-resetting state, and notifies the event controller 70 that the power waiting process has been completed. Of course
541453 五、發明說明(ίο) 後,事件控制器7 0使系統控制器3 0閒置。接著進入步驟 112。 · 1 1 2 ··若電力狀態變數7 5 a指示是否該使用省電模式, 若是則跳到步驟1 1 4 1,若否則跳到步驟1 1 4 h。541453 V. After the description of the invention (ίο), the event controller 70 makes the system controller 30 idle. Proceed to step 112. · 1 1 2 ·· If the power state variable 7 5 a indicates whether the power saving mode should be used, if yes, skip to step 1 1 4 1; otherwise, skip to step 1 1 4 h.
1 1 4 1 ·使用省電模式。事件控制器7 〇以時脈控制信號 47將時脈信號24、34、54和64設定成較低的頻率。例^ : 若時脈產生器4 0產生一 1 3 3 Μ Η z的信號給記憶體時脈信號5 4 和主機時脈信號34的話,事件控制器70會使用時脈控制信 號47使得時脈產生器40產生60MHz的時脈信號來設定時脈 信號24、34和54。這些較低頻率的時脈信號24、34和54會 減少電腦系統1 0之總電力消耗。需注意的是,降低主機時 脈h號3 4的頻率會使得相對應的前側匯流排3 2、記憶體匯 流排3 5和影像匯流排3 6的工作頻率降低。事件控制器7 q可 選擇只調整時脈信號24、34、54和64中一個、幾個或是調 整全部的時脈信號。事件控制器70會依據硬體的能力和元 件2 0、3 0、4 0、5 0和6 0的限制來決定該如何調整時脈信號 24、34、54和64。在使中央處理單元2〇進入等待狀態,且 影像電路6 0和系統控制器3 0都處於閒置狀態時,改變它們 相對的時脈信號2 4、6 4和3 4,並不會使這些元件失效。同 樣的,當動態隨機存取記憶體5 0 a處於更新自我更新模式 時,其所使用的記憶體時脈信號5 4也能夠安全地被改變。 跳到步驟1 1 6。 1 1 4 h :使用最大電腦系統電力。關閉省電模式。事件 控制器7 0利用時脈控制信號4 7設定時脈信號2 4、3 4、5 4和1 1 4 1 · Use power saving mode. The event controller 70 sets the clock signals 24, 34, 54 and 64 to a lower frequency with a clock control signal 47. Example ^: If the clock generator 40 generates a 1 3 3 Μ Η z signal to the memory clock signal 5 4 and the host clock signal 34, the event controller 70 will use the clock control signal 47 to make the clock The generator 40 generates a clock signal of 60 MHz to set the clock signals 24, 34, and 54. These lower frequency clock signals 24, 34 and 54 will reduce the total power consumption of the computer system 10. It should be noted that reducing the frequency of the host clock h 3 34 will reduce the operating frequency of the corresponding front bus 3 2, memory bus 3 5 and image bus 36. The event controller 7 q can choose to adjust only one, a few of the clock signals 24, 34, 54 and 64 or all the clock signals. The event controller 70 decides how to adjust the clock signals 24, 34, 54 and 64 according to the capabilities of the hardware and the limitations of the components 20, 30, 40, 50, and 60. When the central processing unit 20 is put into a waiting state, and the image circuit 60 and the system controller 30 are both in an idle state, changing their relative clock signals 24, 64, and 34 does not cause these components Failure. Similarly, when the dynamic random access memory 50a is in the update self-renewing mode, the memory clock signal 54 used by it can also be safely changed. Skip to steps 1 1 6. 1 1 4 h: Use the maximum computer system power. Turn off power saving mode. The event controller 70 uses the clock control signal 4 7 to set the clock signal 2 4, 3 4, 5 4 and
第13頁 541453 五、發明說明(11) 6 4到它們各自可能的最高頻率。跳到步驟1丨6。 116 :事件控制器70輸出中斷請求37至系統控制器 3 0 ’使系統控制器3 〇離開閒置狀態。系統控制器3 〇執行從 等待狀態回復程序,使動態隨機存取記憶體5 〇 a回復正常 模式工作’喚醒影像電路6 〇,使中央處理單元2 〇離開等待 狀態。當中央處理單元20離開等待狀態後,會執行從記憶 體回復碼56b。除非電腦系統1〇以較低或以較高的速度工 作,否則電腦系統1 〇會回復為步驟丨0 6之前的狀態。進入 步驟1 1 8。 〜 1 1 8 :利用電力狀態變數7 5 a設定狀態指示器7 6的狀 態。跳到步驟1 〇 2。 第1圖所示係一支援於系統控制器3 〇與中央處理單元 2 〇、s己憶體5 0和影像電路6 〇間使用非同步時脈作號之雷腦 系統!。。理論上這個電腦系統i"的所有::㈡以 同的頻率工作,故如第1圖設計之電腦系統1 〇是最普遍的 例子。實際上。使用同步時脈信號的電腦系統,在設計上 會比較容易。 不 请參照第3圖,其所 f ,卞、 OX ΓΊI A7F *1^ jy _ 電腦系統2 1 〇之功能方塊圖。第二電腦系統2丨〇與 1:,元件都完全相同,除了時脈產生器2 4 0只產生電系\糸控統 器2 3 0所系之主機日$脈#號2 3 4。之後,系統控制器2 3 〇 利用主機時脈信號2 3 4產生中央處理單元22〇使用之^央户 1單元時脈信號2 24、記憶體2 5 0所使用之記憶體時脈作= 254以及影像電路26〇所使用之影像時脈信號“^。事件。產^Page 13 541453 V. Description of the invention (11) 6 4 to their respective highest possible frequencies. Go to step 1 丨 6. 116: The event controller 70 outputs an interrupt request 37 to the system controller 30 'to take the system controller 30 out of the idle state. The system controller 3 executes the recovery procedure from the standby state, and returns the dynamic random access memory 5a to the normal mode operation ', wakes the image circuit 6o, and causes the central processing unit 2o to leave the standby state. When the central processing unit 20 leaves the waiting state, it executes a reply code 56b from the memory. Unless the computer system 10 is operating at a lower or higher speed, the computer system 10 will return to the state before step 1-6. Go to step 1 1 8. ~ 1 1 8: Use the power state variable 7 5 a to set the state of the status indicator 7 6. Skip to step 102. Shown in Figure 1 is a Thunderbolt system that supports asynchronous system clocks between the system controller 30 and the central processing unit 20, smemory body 50, and image circuit 60 !. . In theory, all the computer systems i " :: work at the same frequency, so the computer system 10 designed as shown in Figure 1 is the most common example. Actually. Computer systems that use synchronized clock signals will be easier to design. Please refer to FIG. 3 for a functional block diagram of f, 卞, OX ΓΊI A7F * 1 ^ jy _ computer system 2 1 〇. The second computer system 2 and 0 are all the same as 1: except that the clock generator 2 40 only generates the host system $$ ## 2 3 4 of the electric system \ 电 control system 2 30. After that, the system controller 2 〇 uses the host clock signal 2 3 4 to generate the central processing unit 22 clock used by the central household 1 unit clock signal 2 24, the memory clock used by the memory 2 50 0 = 254 And the image clock signal "^. Event.
第14頁 541453 五、發明說明(12) 生器2 7 0僅能使用時脈控制信號24 7去調整主機時脈信號 2 3 4的頻率。改變主機時脈信號2 3 4的頻率不只會改變前側 匯流排2 3 2、記憶體匯流排2 3 5和影像匯流排2 3 6的頻率, 也會改變甲央處理單元220、記憶體250和影像電路260的 内部工作頻率。Page 14 541453 V. Description of the invention (12) The generator 2 7 0 can only use the clock control signal 24 7 to adjust the frequency of the host clock signal 2 3 4. Changing the frequency of the host clock signal 2 3 4 will not only change the frequency of the front side bus 2 3 2, the memory bus 2 3 5 and the image bus 2 3 6 but also the central processing unit 220, memory 250 and The internal operating frequency of the image circuit 260.
雖然上述揭露之實施例僅以可攜式電腦為例,但對任 何熟悉此技藝者而言,本發明所提出之裝置與方法皆可輕 易地應用於桌上型電腦。本發明所提出之裝置與方法適用 於任何可藉由改變匯流排或是元件的工作頻率又不至於使 整個系統失效,來達到節省電力的目的的計算機系統。並 且,如果系統中的元件允許的話,本發明之事件控制器 7 0、2 7 0也可用以控制元件的核心工作電壓的升降,以更 進一步地管理系統電力的消耗。 【發明效果】Although the above-disclosed embodiment only uses a portable computer as an example, for anyone skilled in the art, the device and method proposed by the present invention can be easily applied to a desktop computer. The device and method provided by the present invention are applicable to any computer system that can achieve the purpose of saving power by changing the operating frequency of a bus or a component without causing the entire system to fail. And, if the components in the system allow it, the event controllers 70 and 2 0 of the present invention can also be used to control the core operating voltage of the components to further manage the power consumption of the system. [Effect of the invention]
本發明上述實施例所揭露之一種用於電腦的省電裝置 及方法在電腦系統中設置一事件控制器。與習知技術相反 的是,該事件控制器具有它自己的計時器。它也能夠藉由 時脈產生器產生時脈信號而不影響它本身。事件控制器等 待中央處理單元以期其他相關的晶片進入閒置狀態、動態 隨機存取記憶體進入更新自我更新模式之後,事件控制器 會改變中央處理單元以及相關晶片的時脈信號,藉以調整 這些元件的電力需求。當這些元件處於閒置狀態時,改變 它們的時脈信號的頻率將不會使它們失效。之後,事件控A power-saving device and method for a computer disclosed in the above embodiments of the present invention sets an event controller in a computer system. Contrary to conventional techniques, the event controller has its own timer. It can also generate a clock signal by the clock generator without affecting itself. The event controller waits for the central processing unit to wait for other related chips to enter the idle state and the dynamic random access memory enters the update self-renewing mode. The event controller will change the clock signals of the central processing unit and related chips to adjust the components. electricity demand. When these components are idle, changing the frequency of their clock signals will not invalidate them. Event control
第15頁 541453 五、發明說明(13) 制器會啟動中央處理單元以及相關晶片,電腦系統自它之 前停止的狀態下重新開始工作。整個過程幾乎是瞬間完成 ^ 的,所以對使用者而言在使用上相當方便。 , 綜上所述,雖然本發明已以一較佳實施例揭露如上, 然其並非用以限定本發明,任何熟習此技藝者,在不脫離 本發明之精神和範圍内,當可作各種之更動與潤飾,因此 本發明之保護範圍當視後附之申請專利範圍所界定者為 準〇 着Page 15 541453 V. Description of the invention (13) The controller will start the central processing unit and related chips, and the computer system restarts from the state where it stopped before. The entire process is almost instantaneous ^, so it is quite convenient for users to use. In summary, although the present invention has been disclosed as above with a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art can make various modifications without departing from the spirit and scope of the present invention. Changes and retouching, so the scope of protection of the present invention shall be determined by the scope of the attached patent application.
第16頁 541453 圖式簡單說明 【圖式之簡單說明】 第1圖繪示本發明所提出之電腦系統的功能方塊圖。 第2圖繪示電腦系統運作的流程圖。 第3圖繪示依據本發明所提出之第二電腦系統之功能 方塊圖。 【圖式標號說明】 10 :電腦系統 20、220 :中央處理單元Page 16 541453 Brief description of the drawings [Simplified description of the drawings] Figure 1 shows a functional block diagram of the computer system proposed by the present invention. Figure 2 shows a flowchart of the operation of the computer system. FIG. 3 is a functional block diagram of a second computer system according to the present invention. [Illustration of figure number] 10: Computer system 20, 220: Central processing unit
23 :中央處理單元中斷請求 24、224 :中央處理單元時脈信號 3 0、2 3 0 :系統控制器 3 2、2 3 2 :前側匯流排 3 4、2 3 4 :主機時脈信號 3 5、2 3 5 :記憶體匯流排 3 6、2 3 6 :影像匯流排 3 7 :中斷請求 4 0、2 4 0 :時脈產生器 4 7、2 4 7 :時脈控制信號 5 0、2 5 0 ·記憶體23: Central processing unit interrupt request 24, 224: Central processing unit clock signal 3 0, 2 3 0: System controller 3 2, 2 3 2: Front side bus 3 4, 2, 3 4: Host clock signal 3 5 , 2 3 5: memory bus 3 6, 2 3 6: video bus 3 7: interrupt request 4 0, 2 4 0: clock generator 4 7, 2 4 7: clock control signal 5 0, 2 5 0Memory
5 0 a :動態隨機處理記憶體 5 0 b :唯讀記憶體 52b :基本輸入輸出系統 5 4、2 5 4 :記憶體時脈信號5 0 a: dynamic random processing memory 5 0 b: read-only memory 52 b: basic input-output system 5 4, 2 5 4: memory clock signal
第17頁 541453 圖式簡單說明 5 5 b ·存入記憶體電腦碼 5 6 b :自記憶體回復電腦碼Page 17 541453 Brief description of the diagram 5 5 b · Store in computer code 5 6 b: Restore computer code from memory
60、 260 影像 電 路 64、 264 影像 時 脈 信號 70、 270 事件 控 制 器 7 2 : 處理 電路 73 : 等待 信號 74 : 計時 器 75 : 記憶 體 75a :電力狀態 變 數 76 : 狀態 指示器 78 : 開關 2 1 0 :第二電腦系統 第18頁60, 260 video circuit 64, 264 video clock signal 70, 270 event controller 7 2: processing circuit 73: wait signal 74: timer 75: memory 75a: power state variable 76: status indicator 78: switch 2 1 0: Second computer system 第 18 页
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8281171B2 (en) | 2005-11-17 | 2012-10-02 | Via Technologies, Inc. | Adjustment of power-saving strategy depending on working state of CPU |
TWI405076B (en) * | 2008-07-29 | 2013-08-11 | Nvidia Corp | Platform-based idle-time processing |
TWI405077B (en) * | 2009-08-14 | 2013-08-11 | Via Tech Inc | Power-saving computer system, graphics processing module, and the power saving method thereof |
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Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8281171B2 (en) | 2005-11-17 | 2012-10-02 | Via Technologies, Inc. | Adjustment of power-saving strategy depending on working state of CPU |
TWI405076B (en) * | 2008-07-29 | 2013-08-11 | Nvidia Corp | Platform-based idle-time processing |
TWI405077B (en) * | 2009-08-14 | 2013-08-11 | Via Tech Inc | Power-saving computer system, graphics processing module, and the power saving method thereof |
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