CN105608023A - Method and system for protecting DRAM stored data of embedded system software - Google Patents
Method and system for protecting DRAM stored data of embedded system software Download PDFInfo
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Abstract
A method for protecting DRAM (Dynamic Random Access Memory) stored data of embedded system software can ensure security of stored data when the system software undergoes an exception. According to the method, an MCU is used to take charge of hardware resetting of an entire embedded system, to monitor software resetting of the embedded system, and to communicate with a main system CPU of the embedded system, so as to learn a current working status of the embedded system; when a system reset signal is detected, the MCU takes over control of a DRAM, and sending a self-refresh command to the DRAM, to enable the DRAM to enter a self-refresh mode, so as to ensure security of DRAM data during an entire resetting period of the embedded system; and after completion of resetting of the embedded system and before a boot program of the embedded system runs and prepares to initialize the DRAM, the MCU sends a quit self-refresh command to the DRAM, and releases and returns the control of the DRAM to the main system CPU, so that after the main CPU takes over the DRAM, the data stored in the DRAM is still valid.
Description
Technical field
The present invention relates to DRAM (dynamic random access memory) the storage number of built-in system software when abnormalAccording to the method and system of protection.
Background technology
A lot of Embedded Application occasions need to be to user data, field data, various configuration information, parameter, programRunning statuses etc. are carried out data preservation, so that system restoring scene easily after restarting, or before reloadingThe data of preserving. The method of safety is that data are saved in various non-volatile memory mediums. But at data quiltSafety be saved in non-volatile memory medium before, also there is various risks and the possibility of makeing mistakes: program is deadLock, systems soft ware makes mistakes, external interference, other software anomaly etc. In the time that systems soft ware occurs that these are abnormal, absolutelyMost systems can utilize the function of house dog to allow system again reset to restart system, under a few cases, also mustMust start hardware reset. But in the time that system hardware and software resets, the Memory controller of system processor can stopPendulum, the data that are stored in DRAM also can be lost.
For user data, field data, various configuration data and parameter are protected, existing embedded systemSystem adopts following two kinds of methods mostly.
1. adopt static SRAM as Installed System Memory and data storage and adopt battery backup, this sideAfter the advantage of formula is system power failure or shutdown, all data can be preserved temporarily, and when system reset, data alsoCan not lose; But the disadvantage of this mode is: the capacity of SRAM is limited, lacks in the market great RongAmount, SRAM cheaply, if use jumbo SRAM, system cost will significantly rise, difficultyTo meet the cost demand of mill run.
2. adopt dynamic dram as Installed System Memory and data storage, use nonvolatile memory conductPermanent data preserve medium, adopt soft switch as system switching, before system soft-off exits by DRAMMiddle data are saved in nonvolatile memory; In the time of System Sudden power down by reserce cell supporting core system workDo, data in DRAM are saved in nonvolatile memory. This mode looks that data can be by fineGround protection, but also there is a fatal shortcoming in it: be exactly by the non-volatile memories that is saved in of safety in dataBefore device, various software deadlocks, software are made mistakes, external interference etc. all can cause software anomaly, once there are theseSoftware anomaly, systems soft ware just can not backup to data in nonvolatile memory safely, at this moment just needsAdopt hand-reset or adopt software reset to restart system. But DRAM data in the process of restarting in systemCan not ensure safety.
Summary of the invention
The object of the present invention is to provide a kind of DRAM storage data guard method of built-in system software and beSystem, even if make mistakes at software deadlock, software, external interference etc. is while causing software anomaly, also can ensure DRAMThe safety of storage data.
For realizing the DRAM storage data guard method of built-in system software of described object, be characterized in adoptingBe responsible for the hardware reset of whole embedded system with a MCU, monitor the software reset of embedded system simultaneously,And carry out communication with the main system CPU of embedded system, to understand the state of current embedded system work,In the time systematic reset signal being detected, MCU is responsible for taking over the control of DRAM, and sends certainly to DRAMRefresh command, makes it enter a kind of self-refresh mode, to ensure at whole embedded system reseting period DRAMThe safety of data, has resetted in embedded system, and Bootloader operation and the preparation of embedded system are initialBefore changing DRAM, MCU sends and exits self-refresh order to DRAM, then discharges and return DRAM to controlSystem power is to main system CPU, and host CPU is taken over after DRAM, and it is effective that the data of preserving in DRAM remain.
The DRAM storage data guard method of described built-in system software, its further feature is, profitWith the manual hardware reset signal of MCU monitoring embedded system and carry out anti-shake, then produce one fixing wideThe hardware reset pulse signal main system CPU that goes to reset of degree, main system CPU internal circuit can produce when resetA raw reset output signal, for the whole embedded system that resets.
The DRAM storage data guard method of described built-in system software, its further feature is, MCUAccording to the trailing edge of the reset output signal for the whole embedded system that resets of main system CPU output or leadingSystem CPU resets and while beginning, synchronously produces the control signal of DRAM bus, so that by the control of DRAMSignal switches to MCU, and the control of taking over control signal by MCU, is then sent to DRAM by MCUSelf-refresh order, makes DRAM enter self-refresh mode, the DRAM data of protection embedded system reseting period.
The DRAM storage data guard method of described built-in system software, its further feature is,After the rising edge of reset output signal or main system cpu reset finish, main system CPU brings into operation to start and drawsHelical pitch order, and before enabling DRAM, produce a synchronizing signal to MCU, MCU receives this synchronously to be believedAfter number, instruction DRAM exits self-refresh mode at once, then the control signal of DRAM bus is switched to masterSystem CPU, and the control of DRAM is given back to main system CPU.
The DRAM storage data guard method of described built-in system software, its further feature is, instituteStating reset output signal is software reset's signal that MCU detects, or MCU is according to hardware reset signal,Produce a reset signal to main system CPU, main system CPU is according to the reset signal of this reset signal output.
For realizing the DRAM storage data protection system of built-in system software of described object, comprise MCU,The control electricity of main system CPU, the DRAM of embedded system and associated MCU, main system CPU, DRAMRoad, is characterized according to aforesaid guard method operation.
Adopt data guard method of the present invention and system, can effectively protect user data, field data, various joiningPut data and parameter, software operation state etc. and do not lose the in the situation that of any software anomaly, and at system soft-offDuring with AC dump, can in time data be saved in nonvolatile memory, thereby reach employing cheaplyMethod is accomplished the safe and reliable backup of data.
Brief description of the drawings
The above and other features of the present invention, character and advantage are by by below in conjunction with drawings and ExamplesDescribe and become more obvious, wherein:
Fig. 1 is the square frame of the DRAM storage data protection system of built-in system software in one embodiment of the inventionFigure.
Detailed description of the invention
Below in conjunction with specific embodiments and the drawings, the invention will be further described, set forth in the following description moreMany details are so that fully understand the present invention, but the present invention obviously can be with multiple other of this description of being different fromMode is implemented, and those skilled in the art can be according to practical situations without prejudice to intension of the present invention in the situation thatDo similar popularization, deduction, therefore should be with content constraints protection scope of the present invention of this specific embodiment.
It should be noted that Fig. 1 is all only as example, it is not to draw according to the condition of equal proportion, andAnd should not be construed as limiting as the protection domain to actual requirement of the present invention using this.
The DRAM storage data protection system of built-in system software comprises the main system CPU of embedded systemAnd DRAM, also comprise a MCU (microprocessor or microprocessing unit, preferably low-power consumption), mainBetween system CPU and MCU, set up three communication lines, main system CPU and MCU select by switches set 4Be couple to selecting property the pin CKE of DRAM, pin CLOCK, pin nCS, pin nRAS, pinNCAS and pin nWE. The corresponding clock of pin CKE allows lead-in wire. The corresponding clock signal of pin CLOCKInput lead. Pin nCS counterpiece selects signal lead. Pin nRAS corresponding row address gating signal line. DrawPin nCAS respective column address gating signal line. Pin nWE correspondence is write enable signal line.
At the pin DIR of MCU, during in the first state, switches set 4 is by main system CPU and DRAM couplingConnect, control DRAM by main system CPU. At the pin DIR of MCU during in the second state, switches set 4Just switch to MCU and DRAM are coupled, control DRAM by MCU.
In the time that main system CPU controls DRAM, the pin C-CTR output signal C-CKE of main system CPU,The pin CKE of C-CLOCK, C-nCS, C-nRAS, C-nCAS, C-nWE to DRAM, drawsPin CLOCK, pin nCS, pin nRAS, pin nCAS and pin nWE.
In the time that MCU controls DRAM, pin M-CTR output control signal M-CKE, the M-of MCUThe pin CKE of CLOCK, M-nCS, M-nRAS, M-nCAS, M-nWE to DRAM, pinCLOCK, pin nCS, pin nRAS, pin nCAS and pin nWE.
MCU monitoring hand-reset signal in addition, hand-reset signal can be that hand triggers a button generation, simultaneouslyMCU also can monitoring software reset signal, and this software reset's signal can be produced by the watchdog circuit of main system CPURaw.
MCU, after hand-reset signal being detected, produces a reset signal to main by pin nRST0System CPU, the internal circuit of main system CPU produces reset signal nReset by pin nRST_0, multipleThe whole embedded system in position. Signal nReset is also access in the pin Detector of MCU, signal nResetTrailing edge trigger MCU external interrupt, the interrupt service routine of MCU was taken over the control of DRAMCome. The same software reset who is produced by software watchdog also can produce by the pin nRST_0 of main system CPUReset signal nReset, MCU processes identical to the processing of software reset's signal with above-mentioned hardware reset signal. ?After the rising edge of reset signal nReset finishes, main system CPU enters Bootloader (boot program),Before preparing to use DRAM, Bootloader sends a synchronizing signal Sync notice MCU, thenMCU will discharge DRAM control.
DRAM has a kind of self-refresh function, in the situation that DRAM has power supply, sends out to DRAM in outsideSend after a self-refresh order, can start the self-refreshing circuit of DRAM inside, this self-refreshing circuit can be certainlyMoving by certain time interval, refresh inner all memory cell, thereby ensure to be stored in data in DRAMCan not lose.
This function of DRAM is generally only used to the low power dissipation design of main system, enters low-power consumption in systemBefore, software by configuration register, makes system can enter a kind of stopped status, enters shutdown in systemBefore, sending a kind of self-refresh order to DRAM, the at this moment power consumption of whole system is minimum, like this when system needsWhile finishing stopped status, can trigger the order of exiting self-refresh to DRAM, then system can continue in the same old wayOperation is gone down and unaffected, and this kind of mode is generally used to the low-power consumption handheld device of the long-term power supply of battery.
Method of the present invention is utilized this self-refresh function of DRAM dexterously, solves in the time of software anomaly numberAccording to can not get the effectively problem of protection.
According to the circuit shown in Fig. 1, method of the present invention adopts low-power consumption MCU (microprocessor or a monolithicMachine) as system monitoring, be responsible for the hardware reset of whole embedded system, the software reset of monitoring embedded system,And carry out certain communication with main system CPU, to understand the state of current system work. When system being detectedWhen reset signal, MCU is responsible for taking over the control of DRAM, and sends self-refresh order to DRAM, makesIt enters a kind of self-refresh mode, to ensure the safety in whole system reseting period DRAM data, is embeddingFormula system reset completes, program operation and prepare to initialize DRAM before, MCU sends and exits self-refresh lifeOrder, to DRAM, then discharges and returns DRAM control to main system CPU, and host CPU is taken over DRAMAfter, it is effective that the data of preserving in DRAM remain.
In one embodiment of the invention, when software deadlock, software are made mistakes, external interference etc. causes software anomaly,User may adopt hand-reset, produces a hand-reset signal, MCU monitoring hand-reset signal (hardwareReset signal) and carry out anti-shakely, then produce the hardware reset letter of a fixed width (for example 150mS)Number to main system CPU, be responsible for taking over the control of DRAM simultaneously, can effectively prevent that user is long-time, manyThe hand-reset of the frequency, because hand-reset long-time, that multifrequency is inferior is unfavorable to the data security protecting of system.
In one embodiment of the invention, MCU monitoring transmission (can to the reset signal of main system CPUHardware reset signal, software reset's signal), in the reset synchronous DRAM of generation bus while starting of main systemControl signal (DIR sends by pin), switches several control signals of DRAM to MCU, by MCUTake over the control of these signals, then send self-refresh order by MCU to DRAM, DRAM is enteredSelf-refresh mode, the DRAM data of protection system reseting period.
In one embodiment of the invention, MCU monitoring transmission (can to the reset signal of main system CPUHardware reset signal, software reset's signal), after main system reset finishes, main system CPU brings into operationBootloader (Root program), and before enabling DRAM, produce a synchronizing signal to MCU,MCU at once instruction DRAM exits self-refresh mode, then the control signal of DRAM bus is switched to masterSystem CPU, and the control of DRAM is given back to main system CPU, now in DRAM, originally storedData are still effective.
Although the present invention with preferred embodiment openly as above, it is not for limiting the present invention, any this areaTechnical staff without departing from the spirit and scope of the present invention, can make possible variation and amendment. Therefore,Every content that does not depart from technical solution of the present invention, that according to technical spirit of the present invention, above embodiment is done appointsWhat amendment, equivalent variations and modification, within all falling into the protection domain that the claims in the present invention define.
Claims (6)
1. the DRAM storage data guard method of built-in system software, is characterized in that adopting a MCUBe responsible for the hardware reset of whole embedded system, monitor the software reset of embedded system simultaneously, and with embedded systemThe main system CPU of system carries out communication, to understand the state of current embedded system work, when system being detectedWhen reset signal, MCU is responsible for taking over the control of DRAM, and sends self-refresh order to DRAM, makesIt enters a kind of self-refresh mode, to ensure the safety in whole embedded system reseting period DRAM data,Resetted in embedded system, the operation of the Bootloader of embedded system and prepare to initialize DRAM itBefore, MCU sends and exits self-refresh order to DRAM, then discharges and returns DRAM control to principal seriesSystem CPU, host CPU is taken over after DRAM, and it is effective that the data of preserving in DRAM remain.
2. the DRAM storage data guard method of built-in system software as claimed in claim 1, its spyLevy and be, utilize the manual hardware reset signal of MCU monitoring embedded system and carry out anti-shakely, then produceThe hardware reset pulse signal of the fixed width main system CPU that goes to reset, main system CPU internal circuit resetsTime can produce a reset output signal, for the whole embedded system that resets.
3. the DRAM storage data guard method of built-in system software as claimed in claim 1, its spyLevy and be, MCU is according to the reset output signal for the whole embedded system that resets of main system CPU outputTrailing edge or in the time that main system cpu reset starts the synchronous control signal that produces DRAM bus so thatThe control signal of DRAM is switched to MCU, taken over the control of control signal by MCU, then by MCUSend self-refresh order to DRAM, make DRAM enter self-refresh mode, protection embedded system reseting periodDRAM data.
4. the DRAM storage data guard method of built-in system software as claimed in claim 3, its spyLevy and be, after the rising edge of reset output signal or main system cpu reset finish, main system CPU startsOperation Bootloader, and before enabling DRAM, produce a synchronizing signal to MCU, MCU receivesAfter this synchronizing signal, instruction DRAM exits self-refresh mode at once, then by the control letter of DRAM busNumber switch to main system CPU, and the control of DRAM is given back to main system CPU.
5. the DRAM storage data guard method of built-in system software as claimed in claim 3, its spyLevy and be, described reset output signal is software reset's signal that MCU detects, or MCU is according to hardPart reset signal, produces a reset signal to main system CPU, and main system CPU is according to this reset signal outputReset signal.
6. the DRAM storage data protection system of built-in system software, comprises MCU, embedded systemThe control circuit of main system CPU, DRAM and associated MCU, main system CPU, DRAM, its feature existsAccording to if claim 1 is to the guard method operation as described in any one in claim 4.
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Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN110825421A (en) * | 2019-11-29 | 2020-02-21 | 湖南国科微电子股份有限公司 | Firmware upgrading method and system and readable storage medium |
| CN111208893A (en) * | 2020-01-13 | 2020-05-29 | 深圳震有科技股份有限公司 | CPU reset control method, system and storage medium |
| CN113535248A (en) * | 2021-06-24 | 2021-10-22 | 合肥松豪电子科技有限公司 | TP chip power-on starting method for reducing SRAM space |
| TWI748081B (en) * | 2017-04-14 | 2021-12-01 | 仁寶電腦工業股份有限公司 | Computer device and data protection method therefore |
| CN114200874A (en) * | 2022-02-17 | 2022-03-18 | 四川创智联恒科技有限公司 | Device and method for detecting equipment reset event |
| WO2022121475A1 (en) * | 2020-12-11 | 2022-06-16 | 浪潮电子信息产业股份有限公司 | Operating-state switching method and apparatus, and electronic device and storage medium |
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Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
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| TWI748081B (en) * | 2017-04-14 | 2021-12-01 | 仁寶電腦工業股份有限公司 | Computer device and data protection method therefore |
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| CN113535248A (en) * | 2021-06-24 | 2021-10-22 | 合肥松豪电子科技有限公司 | TP chip power-on starting method for reducing SRAM space |
| CN113535248B (en) * | 2021-06-24 | 2024-05-28 | 合肥松豪电子科技有限公司 | TP chip power-on starting method for reducing SRAM space |
| CN114200874A (en) * | 2022-02-17 | 2022-03-18 | 四川创智联恒科技有限公司 | Device and method for detecting equipment reset event |
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Application publication date: 20160525 |