CN113535248A - TP chip power-on starting method for reducing SRAM space - Google Patents

TP chip power-on starting method for reducing SRAM space Download PDF

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CN113535248A
CN113535248A CN202110707107.XA CN202110707107A CN113535248A CN 113535248 A CN113535248 A CN 113535248A CN 202110707107 A CN202110707107 A CN 202110707107A CN 113535248 A CN113535248 A CN 113535248A
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cpu
dramb
remap
space
boot
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CN113535248B (en
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张金磊
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Hefei Pinetech Electronics Co ltd
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Hefei Pinetech Electronics Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/4401—Bootstrapping
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/24—Resetting means
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0877—Cache access modes
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0893—Caches characterised by their organisation or structure
    • G06F12/0895—Caches characterised by their organisation or structure of parts of caches, e.g. directory or tag array
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807—System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/781—On-chip cache; Off-chip memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7839—Architectures of general purpose stored program computers comprising a single central processing unit with memory
    • G06F15/7842—Architectures of general purpose stored program computers comprising a single central processing unit with memory on one IC chip (single chip microcontrollers)
    • G06F15/7846—On-chip cache and off-chip main memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1028—Power efficiency
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/10—Providing a specific technical effect
    • G06F2212/1041—Resource optimization
    • G06F2212/1044—Space efficiency improvement
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Computer Security & Cryptography (AREA)
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  • Microelectronics & Electronic Packaging (AREA)
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Abstract

A TP chip power-on starting method for reducing SRAM space comprises the following steps: s1, defining a register bit REMAP, and performing address mapping control by this bit, where REMAP is 0 at the beginning of power-on; s2, resetting the CPU by the IC internal module, stopping the CPU from running, simultaneously carrying the Boot program stored by the Eflash to Dramb by the Eflash _ Ctrl module, and releasing the CPU reset after the carrying is finished; s3, the CPU starts to run Boot, the running space is Dramb at the moment, and the data cache space of the CPU is Drama; s4, when the Boot function is completed, configuring the register to make REMAP 1; when REMAP is 1, CPU resets to make CPU run again, at this time, CPU running space is mapped to Eflash, both Drama and Dramb are used as data buffer area, and routing distribution is carried out according to IC invented address division to access Drama or Dramb. The invention achieves the aims of reducing the area of the SRAM and reducing the power consumption.

Description

TP chip power-on starting method for reducing SRAM space
Technical Field
The invention relates to the technical field of chips, in particular to a TP chip power-on starting method for reducing SRAM space.
Background
In globalization today, the development of electronic products is also a day-to-day change, and electronic products which are creative and closely related to human life are continuously emerging. Along with the requirement of people on the quality of life is gradually improved, the wearable product can detect health indexes such as heart rate and blood pressure, so the wearable market is a huge potential market, and both a terminal manufacturer and a touch display IC company can be dedicated to the development of the wearable market product.
The TP IC is an essential component of the smart wearable device, and the area and power consumption of the TP IC are required to be higher by the smart wearable device.
For a small embedded application SOC chip, an SRAM, a plug-in SPI FLASH and an Eflash are generally used as the operation space of the APP.
When the SRAM is used as the APP space, an additional read-only memory device Rom is needed as the operation space of the Boot, and the Boot has the main functions of communicating with an external host to download the APP file into the SRAM storage area through an external interface and check the APP; or the Boot reads the APP file into the SRAM storage area by reading the storage space of the plug-in SPI flash in which the APP file is stored, and then checks the APP.
When the flashh is used as the APP running space, the running space of the Boot in the conventional scheme may be divided into two cases. The first is that extra Rom is needed as the operation space of Boot; the second is that Boot also runs in the flashspace.
When the SRAM is used as the APP running space, the Boot region is an independent region, and an additional Rom memory device is needed, so that the area of the IC is increased. And the SRAM is used as the operation space of the APP, so that the SRAM is easily interfered by ESD, once the data in the SRAM is knocked over by the ESD, the whole system cannot be reset, and the power needs to be powered on again. In addition, because Rom is used as the Boot running space, the Boot needs to be added into the production flow when the IC is produced, so that the modification cannot be carried out. Once errors are found during subsequent chip verification, the errors must be corrected by re-streaming, and the fault-tolerant cost is too high.
When the flashh is used as the APP operation space, the two Boot operation modes of the traditional scheme have respective disadvantages. The first method needs extra Rom as the Boot operating space, and the Boot area is an independent area and needs extra Rom storage equipment, so that the area of the IC is increased. Once errors are found during subsequent chip verification, the errors must be corrected by re-streaming, and the fault-tolerant cost is too high. The second type of Boot also runs in the flash space, the main function of the Boot is to upgrade or download an APP file to the flash space, because only one flash interface is provided, the switching of the access of the flash interface is needed to meet the requirement of CPU instruction fetching and data access at the same time, the speed is reduced, and the TP IC has requirements on the first frame time of reporting points.
Disclosure of Invention
The invention provides a TP chip power-on starting method for reducing SRAM space, which is used for achieving the purposes of saving SRAM area and reducing power consumption, and the specific scheme is as follows:
a TP chip power-on starting method for reducing SRAM space comprises the following steps:
s1, defining a register bit REMAP, and performing address mapping control by this bit, where REMAP is 0 at the beginning of power-on;
s2, resetting the CPU by the IC internal module, stopping the CPU from running, simultaneously carrying the Boot program stored by the Eflash to Dramb by the Eflash _ Ctrl module, and releasing the CPU reset after the carrying is finished;
s3, the CPU starts to run Boot, the running space is Dramb at the moment, and the data cache space of the CPU is Drama;
s4, when the Boot function is completed, configuring the register to make REMAP 1; when REMAP is 1, CPU resets to make CPU run again, at this time, CPU running space is mapped to Eflash (storage area of APP), both Drama and Dramb are used as data buffer area, and routing distribution access Drama or Dramb is carried out according to address division of IC invention.
The invention has the beneficial effects that:
(1) with the higher integration of ICs, the global demand for SOC chips is also increasing. One of the main reasons for being called an SOC chip is that the IC has a CPU core integrated therein, and the CPU has the meaning of running APP. For a small embedded application SOC chip, SRAM and Eflash are generally used as the running space of APP. Whichever mode is used as the operating space of the APP, an additional storage space is required to operate the power-on Boot program of the system, which is generally referred to as Boot. When the IC is powered on, the invention firstly utilizes an IC internal module to move the Boot of the Eflash to the DRAM serving as a data cache space as a temporary Boot operation space. Therefore, the Boot operation space and the data cache space are subjected to time-sharing multiplexing, and the aims of reducing the area of the SRAM and reducing the power consumption are fulfilled.
(2) According to the invention, the eFlash is used as a Boot storage area, and when the eFlash is operated, the IC internal module is used for temporarily transporting the Boot to a DRAM area of a data cache, so that the defects of the traditional scheme in the background technology are effectively overcome.
Drawings
Fig. 1 is a block diagram of internal logic when REMAP is 0.
Fig. 2 is a block diagram of internal logic when REMAP is 1.
Detailed Description
A TP chip power-on starting method for reducing SRAM space. The method comprises the following steps:
s1, defining a register bit REMAP, and performing address mapping control by this bit, where REMAP is 0 at the beginning of power-on;
s2, resetting the CPU by the IC internal module, stopping the CPU from running, simultaneously carrying the Boot program stored by the Eflash to Dramb by the Eflash _ Ctrl module, and releasing the CPU reset after the carrying is finished;
s3, the CPU starts to run Boot, the running space is Dramb at the moment, and the data cache space of the CPU is Drama;
s4, when the Boot function is completed, the configuration register sets REMAP to 1, as shown in fig. 1. When REMAP is 1, CPU resets to make CPU run again, at this time, CPU running space is mapped to Eflash (storage area of APP), both Drama and Dramb are used as data buffer area, and routing allocation access Drama or Dramb is performed according to address division of IC invention, as shown in FIG. 2.
As can be seen from the present invention, the data buffer area of the CPU is divided into Drama and Dramb. Dramb is used as an instruction operation area of the CPU when the REMAP is 0, and is used as a data cache area of the CPU when the REMAP is 1, thereby achieving the purpose of time division multiplexing. When performing the size division of Drama and Dramb, it follows that the space where Drama and Dramb are added together should satisfy the requirement of data buffer space in the ReMAP 1 stage, and the size of Dramb should satisfy the size of Boot file.
Therefore, the purposes of reducing the area of the SRAM and reducing the power consumption are achieved through the ingenious arrangement of the invention, and the scheme of using the Elash as the CPU operation space also enhances the ESD resistance.
The above description is only for the preferred embodiment of the present invention, but the scope of the present invention is not limited thereto, and any person skilled in the art should be considered to be within the technical scope of the present invention, and the technical solutions and the inventive concepts thereof according to the present invention should be equivalent or changed within the scope of the present invention.

Claims (1)

1. A TP chip power-on starting method for reducing SRAM space is characterized by comprising the following steps:
s1, defining a register bit REMAP, and performing address mapping control by this bit, where REMAP is 0 at the beginning of power-on;
s2, resetting the CPU by the IC internal module, stopping the CPU from running, simultaneously carrying the Boot program stored by the Eflash to Dramb by the Eflash _ Ctrl module, and releasing the CPU reset after the carrying is finished;
s3, the CPU starts to run Boot, the running space is Dramb at the moment, and the data cache space of the CPU is Drama;
s4, when the Boot function is completed, configuring the register to make REMAP 1; when REMAP is 1, CPU resets to make CPU run again, at this time, CPU running space is mapped to Eflash, both Drama and Dramb are used as data buffer area, and routing distribution is carried out according to IC invented address division to access Drama or Dramb.
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CN108763760A (en) * 2018-05-29 2018-11-06 西安微电子技术研究所 A kind of system level chip based on two-stage BOOT structures
CN111176739A (en) * 2019-12-29 2020-05-19 苏州浪潮智能科技有限公司 System starting method, device, equipment and storage medium
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CN105608023A (en) * 2014-10-29 2016-05-25 梅特勒-托利多(常州)测量技术有限公司 Method and system for protecting DRAM stored data of embedded system software
CN108763760A (en) * 2018-05-29 2018-11-06 西安微电子技术研究所 A kind of system level chip based on two-stage BOOT structures
CN111198718A (en) * 2019-12-27 2020-05-26 广东高云半导体科技股份有限公司 FPGA-based processor starting method and processor
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