CN115827071A

CN115827071A - Method and system for suspending standby operation of power management system

Info

Publication number: CN115827071A
Application number: CN202211318590.3A
Authority: CN
Inventors: 王洁; 黄志文; 陈曦
Original assignee: Shenzhen Xihua Technology Co Ltd
Current assignee: Shenzhen Xihua Technology Co Ltd
Priority date: 2022-10-26
Filing date: 2022-10-26
Publication date: 2023-03-21

Abstract

The invention discloses a method and a system for suspending the standby operation of a power management system, wherein the method comprises the following steps: after receiving the deep sleep instruction, the power management controller PMC generates a hold unexecuted instruction holdselepen signal of a CPU; controlling the timing of an internal low-speed SIRC clock to enable a holdsleepn signal acting on a CPU to be in a low effective state; if the PMC does not receive a response message fed back by the CPU based on the holdslepen signal and recognizes that a wakeup source wakeup signal appears, controlling an internal low-speed SIRC clock timing sequence to enable the holdslepen signal acting on the CPU to be in a high-invalid state; and completing information synchronization of the power management controller and the CPU based on the condition that the holdsleepn signal is in a high-invalid state. The invention ensures that the running mechanisms of the CPU and the power management controller are the same, and can achieve the information synchronization under the normal mode running.

Description

Method and system for suspending standby operation of power management system

Technical Field

The present invention relates to the field of power supply technologies, and in particular, to a method and a system for suspending a standby operation of a power management system.

Background

A System On Chip (SOC) supports a normal operation mode RUN, a STANDBY mode STANDBY and a STOP mode STOP, wherein the RUN mode is entered after power-on reset (POR) of a Chip, all power supplies, clocks and functional modules of the Chip are in normal working states in the RUN mode, the power supply module keeps supplying power and closes a core clock in the STOP mode, a CPU in the SOC, namely a power management System, STOPs reading and writing a flash memory unit flash and a static memory sram, and other clock sources can be determined by System software to be closed or not; in STANDBY mode, the mode that minimizes system-on-chip power consumption. In the STANDBY mode, the system on chip turns off the power supply of most digital circuits, only an external wake-up source is reserved, a 128KHz low-speed clock is reserved by a clock module, flash enters deep power down or power off, and sram enters a memory retentivity state.

The system on a chip includes: the system comprises a CPU (central processing unit), a Power Management Controller (PMC) and the like, wherein after receiving a deep sleep operation sent by the CPU, the PMC can control the whole system to be ready to enter a standby mode, the PMC needs to enable the CPU, a flash memory unit, a static memory sram and the like to enter a Power-down preparation state, if a wake-up source exists outside the system, the PMC receives the wake-up source, the PMC is in a normal operation mode state, the CPU is in a Power-down preparation stage, the two states of the CPU and the Power management controller are not synchronous, the CPU can continue to execute a set operation behavior, the CPU can be hung or RUN away, the CPU cannot be synchronized with the PMC state, and the whole system is stopped and cannot enter an RUN mode.

Disclosure of Invention

The invention aims to overcome the defects of the prior art, and provides a method and a system for suspending the standby operation of a power management system.

In order to solve the above problem, the present invention provides a method for suspending a standby operation of a power management system, the method comprising the steps of:

after receiving the deep sleep instruction, the PMC generates a hold release signal for a CPU to hold an unexecuted instruction, and sends the hold release signal to the CPU;

controlling the timing sequence of an internal low-speed SIRC clock to enable a holdsleepn signal acting on a CPU to be in a low effective state, and enabling a power management system to be ready to enter a standby state;

in the process of preparing to enter a standby state, if the PMC does not receive a response message fed back by the CPU based on the holdslepen signal and identifies that a wakeup source wakeup signal appears, controlling the internal low-speed SIRC clock timing sequence to enable the holdslepen signal acting on the CPU to be in a high invalid state;

and finishing information synchronization of the power management controller and the CPU based on the condition that the holdlepn signal is in a high invalid state, so that the power management system enters a normal operation mode.

The preparing the power management system to enter the standby state comprises:

judging whether the power management system supports a CPU memory function or not;

if the CPU supports the CPU memory function, the PMC sends a CPU memory instruction to a CPU memory control unit;

and if the CPU does not support the CPU memory function, the PMC triggers the power management system to enter an isolation enabling state.

The method further comprises the following steps:

and the CPU memory control unit receives the CPU memory instruction and reads the CPU memory information based on the CPU memory instruction.

The operation of reading the CPU memory information based on the CPU memory instruction comprises the following steps:

reading CPU memory information from the CPU and storing the CPU memory information into a CPU memory static storage unit.

The step of completing information synchronization of the power management controller and the CPU based on the condition that the holdsleepn signal is in a high invalid state comprises the following steps:

and when the internal low-speed SIRC clock timing is controlled to enable a holdslepen signal acting on the CPU to be in a high inactive state, the internal low-speed SIRC clock timing is controlled to jump the PMC back to a normal operation mode.

The method further comprises the following steps:

controlling the internal low-speed SIRC clock timing to act on the flash memory cell causes the flash memory cell to jump back to a normal operating mode from a standby state.

The controlling the internal low-speed SIRC clock timing to act on the flash memory cell so that the flash memory cell jumps back to the normal operation mode from the standby state comprises:

identifying a low power mode of the flash memory cell;

and controlling the internal low-speed SIRC clock timing to act on the control signal timing corresponding to the low power consumption mode, so that the flash memory unit jumps back to the normal operation mode from the standby mode.

Correspondingly, the invention also provides a power management system, which comprises:

the PMC is used for generating a hold release instruction hold release signal of the CPU after receiving the deep sleep instruction and sending the hold release signal to the CPU; controlling the timing sequence of an internal low-speed SIRC clock to enable a holdsleepn signal acting on a CPU to be in a low effective state, and enabling a power management system to be ready to enter a standby state; in the process of preparing to enter a standby state, if the PMC does not receive a response message fed back by the CPU based on the holdselepen signal and recognizes that a wakeup source wakeup signal appears, controlling the internal low-speed SIRC clock timing sequence to enable the holdselepen signal acting on the CPU to be in a high invalid state; completing information synchronization of a power management controller and a CPU based on the condition that the holdlepn signal is in a high invalid state, so that the power management system enters a normal operation mode;

the CPU is used for generating a deep sleep instruction and sending the deep sleep instruction to the PMC; and receiving a holdsleepn signal.

The power management system further comprises:

the CPU memory control unit is used for receiving a CPU memory instruction sent by the PMC in the process of preparing to enter a standby state, reading a current operation instruction from the CPU based on the memory instruction and writing the operation instruction into the CPU memory static storage unit;

and the CPU memory static storage unit is used for storing the current operation instruction written by the CPU memory control unit.

The power management system further comprises:

and the flash memory unit is used for jumping back to a normal operation mode from the standby state under the control of the internal low-speed SIRC clock timing in the process of preparing to enter the standby state.

According to the method and the system, the holdslepen signal is arranged between the PMC and the CPU and is related to the internal low-speed SIRC clock time sequence, so that the CPU can keep the instruction-free process when the CPU is ready to enter the standby state, the holdslepen signal is in the high-invalid state when the wake-up source trigger is received, the CPU can enter the normal operation mode, the CPU and the power management controller can be in the normal operation mode, the CPU is prevented from being hung up or running away, the running mechanism of the CPU and the power management controller is the same, and the information synchronization under the normal mode operation can be achieved.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.

FIG. 1 is a schematic diagram of a power management system according to an embodiment of the present invention;

FIG. 2is a flow chart of a first method for suspending standby operation of a power management system in an embodiment of the invention;

FIG. 3 is a flowchart of a second method for suspending standby operation of a power management system according to an embodiment of the present invention

FIG. 4 is a first diagram illustrating the timing of a wake-up control signal when the PMC enters a standby mode according to an embodiment of the present invention;

fig. 5 is a second schematic diagram of a timing sequence of a wake-up control signal when the PMC enters a standby mode according to an embodiment of the present invention.

Detailed Description

The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Example one

Specifically, fig. 1 shows a schematic structural diagram of a power management system in an embodiment of the present invention, where the power management system may be an SOC or an independent power module, and the power management system includes:

CPU, CPU memory control unit, CPU memory static memory unit, system static memory unit, flash memory unit, analog unit, PMC control unit, etc.

The system supports CPU memory retentivity control, namely, before entering a STANDBY mode STANDBY, the system controls a read instruction from a CPU to be stored in a sram (CPU memory static storage unit), and after the system is powered on again in the STANDBY mode STANDBY, the system controls a reload instruction from the sram (CPU memory static storage unit) to be written in the CPU.

Under the normal working mode RUN, 1.1v power supply of the power management system is provided by the linear voltage regulator LDO11_ MR; in the low power mode, i.e., STANDBY mode, LDO11_ MR is turned off and the chip is powered by LDO11_ LR. The CPU memory static storage unit, the system static storage unit and the 1.1v power supply of the flash are all provided by the LDO11_ LR.

Under the STANDBY mode STANDBY, the CPU memory control unit, and the part of the analog unit include an oscillator, a phase-locked loop, a CMP, an ADC, a flash memory unit, and the like, which have no power supply and belong to a shutdown area (shut), and the PMC control unit and the part of the analog unit LDO always have power supply and belong to an always-on area (always-on) of a normally-on area.

The flash memory unit flash is internally provided with a power switch which can be switched on and off by controlling a supply signal SUPPLYON. When SUPPLYON =0, the 1.1v and 3.3v power supplies of the flash are turned off.

The system supports PAD keep enabling control, and mainly controls shutdown domain related data output and enabling signals to be maintained in a state before power failure when the system is ready to enter a standby state.

When the system is not powered down, abort standby operation can be performed through handshake between the CPU and the PMC, so that CPU operation is prevented from being suspended or running away.

In a specific implementation process, the PMC is configured to generate a holdsleepn signal for a CPU to hold an unexecuted instruction after receiving a deep sleep instruction, and send the holdsleepn signal to the CPU; controlling the timing sequence of an internal low-speed SIRC clock to enable a holdsleepn signal acting on a CPU to be in a low effective state, and enabling a power management system to be ready to enter a standby state; in the process of preparing to enter a standby state, if the PMC does not receive a response message fed back by the CPU based on the holdselepen signal and recognizes that a wakeup source wakeup signal appears, controlling the internal low-speed SIRC clock timing sequence to enable the holdselepen signal acting on the CPU to be in a high invalid state; completing information synchronization of a power management controller and a CPU based on the condition that the holdsleepn signal is in a high-invalid state, so that a power management system enters a normal operation mode; the CPU is used for generating a deep sleep instruction and sending the deep sleep instruction to the PMC; and receiving a holdsleepn signal.

The CPU memory control unit is used for receiving a CPU memory instruction sent by the PMC in the process of preparing to enter a standby state, reading a current operation instruction from the CPU based on the memory instruction and writing the operation instruction into the CPU memory static storage unit; and the CPU memory static storage unit is used for storing the current operation instruction written by the CPU memory control unit.

The flash memory cell is used to jump back from the standby state to the normal operating mode in preparation for entering the standby state under the control of the internal low speed SIRC clock timing.

In the power management system in the embodiment of the invention, the holdslepen signal is arranged between the PMC and the CPU and is related to the internal low-speed SIRC clock time sequence, so that the CPU can keep the instruction-free process when the CPU is ready to enter the standby state, the holdslepen signal is in the high-invalid state when the wake-up source trigger is received, and the CPU can enter the normal operation mode, so that the CPU and the power management controller can be in the normal operation mode, the CPU operation is prevented from being hung up or running away, the running mechanisms of the CPU and the power management controller are the same, and the information synchronization under the normal mode running can be achieved.

Specifically, fig. 2 shows a flowchart of a first method for suspending a standby operation of a power management system according to an embodiment of the present invention, which specifically includes the following steps:

s201, after receiving a deep sleep instruction, a PMC generates a hold release signal for a CPU to hold an unexecuted instruction, and sends the hold release signal to the CPU;

s202, controlling the time sequence of an internal low-speed SIRC clock to enable a holdsleepn signal acting on a CPU to be in a low effective state, and enabling a power management system to prepare to enter a standby state;

s203, in the process of preparing to enter a standby state, if the PMC does not receive a response message fed back by the CPU based on the holdselepen signal and recognizes that a wakeup source wakeup signal appears, controlling an internal low-speed SIRC clock timing sequence to enable the holdselepen signal acting on the CPU to be in a high invalid state;

and S204, completing information synchronization of the power management controller and the CPU based on the condition that the holdlepn signal is in a high invalid state, and enabling the power management system to enter a normal operation mode.

Based on the examples shown in fig. 1 and fig. 2, a holdslepen signal is set between the PMC and the CPU, and is associated with an internal low-speed SIRC clock timing sequence, so that the CPU can keep a non-execution instruction process when preparing to enter a standby state, and when receiving a wake-up source trigger, the holdslepen signal is in a high-invalid state, and the CPU can enter a normal operation mode, so that the CPU and the power management controller can both be in a normal operation mode, thereby avoiding the CPU from being hung up or running away, enabling the operating mechanisms of the CPU and the power management controller to be the same, and achieving information synchronization in the normal mode operation.

Example two

Specifically, fig. 3 shows a flowchart of a second method for suspending a standby operation of a power management system in an embodiment of the present invention, where the method shown in fig. 3 is implemented according to the power management system shown in fig. 1, and the power management system supports CPU memory retention control, and the method includes the following steps:

s301, the CPU generates a deep sleep instruction and sends the deep sleep instruction to the PMC;

when the SOC is in the normal running RUN mode, and when the SOC is required to enter the STANDBY mode STANDBY, in order to ensure the state change, it needs to WAIT for the PMC _ WAIT _ CPU _ HOLD, PMC _ RDCPU _ REQ, PMC _ ISO _ ON, and so ON, to enter the STANDBY mode, where:

when a RUN mode in the SOC enters a PMC _ WAIT _ CPU _ HOLD state, a CPU generates a deep sleep instruction, the deep sleep instruction is sent to a PMC, the PMC generates a HOLD non-execution instruction HOLD signal of the CPU, in the process, the CPU is in a PMC state that the CPU needs to WAIT for being maintained by the PMC in a sleep (HOLD sleep) state, namely a PMC _ WAIT _ CPU _ HOLD state, and the CPU is supplied with power but does not execute the instruction in the state;

in the process that a CPU is ready to power down, because the system supports CPU memory retention control, the system needs to enter a CPU retention read request stage, namely, the PMC _ WAIT _ CPU _ HOLD state needs to be switched to a PMC _ RDCPU _ REQ state, under the PMC _ RDCPU _ REQ state, a CPU is supplied with power but does not execute an instruction, the PMC generates a CPU memory instruction and then sends the CPU memory instruction to a CPU memory static storage unit, and the CPU memory static storage unit reads a current operation instruction from the CPU based on the CPU memory instruction and writes the operation instruction into the CPU memory static storage unit; if the entire retention control is complete, the PMC needs to enter into an isolation ON enable state, i.e., PMC _ ISO _ ON state. In a PMC _ ISO _ ON state, a CPU is in a PMC hold state, the PMC is in normal operation, and it is necessary to enable the PMC to enter a mode with the lowest power consumption from normal operation to complete a system isolation enabling state, and after the system isolation enabling state is completed, the system ON chip turns off the voltage of most digital circuits, and only an external wake-up source is reserved to enter a STANDBY mode.

The isolation enable state refers to isolation enable of a shutdown domain output signal, when the isolation enable is valid, the output signal has no influence on control logic of always on domain, and when the enable signal is invalid, the output signal is a normal control logic signal.

S302, after receiving a deep sleep instruction, a PMC generates a hold release signal for a CPU to hold an unexecuted instruction, and sends the hold release signal to the CPU;

in the process of waiting for states such as PMC _ WAIT _ CPU _ HOLD, PMC _ RDCPU _ REQ, PMC _ ISO _ ON and the like to enter the STANDBY mode, the CPU does not execute instructions, but obtains power supply of the power module.

And a deep sleep instruction, a holdsleepn signal and a holdsleep-ackn are arranged between the CPU and the PMC to realize the synchronization process between the CPU and the PMC.

The deep sleep instruction is a deep sleep signal generated by the CPU, and the PMC starts to control the system to enter a STANDBY mode after receiving the deep sleep signal.

The holdslepen signal is a signal for holding the CPU in the status of the CPU, and is generated by the PMC and sent to the CPU, and the CPU receives the signal and holds the CPU status. During entering the STANDBY mode, when a PMC synchronization wakeup source appears, the holdslepen signal is set to be invalid in the second beat.

The hold _ ackn is an acknowledger signal of the CPU held after the CPU receives the hold signal, the acknowledger signal is generated by the CPU and sent to the PMC component, and the hold _ ackn is invalid after the second beat when the hold signal is invalid.

After the PMC receives the deep sleep instruction, generating a holdselepen signal for a CPU to keep not executing the instruction, and sending the holdselepen signal to the CPU, wherein the holdselepen signal comprises the following steps: the PMC generates a holdslepen signal based on internal low speed SIRC clock (sirclk) timing after receiving the deep sleep instruction.

S303, the PMC controls an internal low-speed SIRC clock timing sequence to enable a holdsleepn signal acting on the CPU to be in a low effective state, and the power management system is ready to enter a standby state;

note that, preparing the power management system to enter the standby state includes: judging whether the power management system supports a CPU memory function; if the CPU supports the CPU memory function, the PMC sends a CPU memory instruction to a CPU memory control unit; and if the CPU does not support the CPU memory function, the PMC triggers the power management system to enter an isolation enabling state.

In this embodiment, since the system supports CPU memory permission control, the CPU memory control unit herein receives the CPU memory instruction and performs an operation of reading CPU memory information based on the CPU memory instruction.

The operation of reading the CPU memory information based on the CPU memory instruction comprises the following steps: reading CPU memory information from the CPU and storing the CPU memory information into a CPU memory static storage unit.

S304, identifying the appearance of a wakeup source wakeup signal by the PMC;

s305, judging whether the CPU feeds back a response message, if not, entering S306, and if so, entering;

the HOLD _ ackn is an acknowledger signal that the CPU is held after receiving the HOLD signal, that is, a response message here, and for receiving the response message, it indicates that the CPU in the three stages is not powered down yet in the states of PMC _ WAIT _ CPU _ HOLD, PMC _ RDCPU _ REQ, PMC _ ISO _ ON, etc., and it may release the valid state of the HOLD _ leepn to enter the RUN mode according to the generation of the wake-up source.

S306, controlling the timing sequence of the internal low-speed SIRC clock to enable a holdsleepn signal acting on the CPU to be in a high invalid state;

in the process of preparing to enter a standby state, if the PMC does not receive a response message fed back by the CPU based on the holdslepen signal and recognizes that a wake-up source wakeup signal appears, controlling the timing sequence of an internal low-speed SIRC clock to enable the holdslepen signal acting on the CPU to be in a high-invalid state.

S307, completing information synchronization of a power management controller and a CPU based on the condition that the holdlepn signal is in a high invalid state;

here, the synchronizing information between the power management controller and the CPU based on the holdsleepn signal being in the high inactive state includes: and when the internal low-speed SIRC clock timing is controlled to enable a holdsleepn signal acting on the CPU to be in a high invalid state, the internal low-speed SIRC clock timing is controlled to jump the PMC back to a normal operation mode.

In the first case: when the system supports cpu coverage, when the state of the system jumps to a PMC _ CPURD _ REQ state, and when the system reads cpu coverage information, a wakeup source suddenly appears, the PMC can be controlled to jump to a normal run mode in the third cycle of the src _ clk, and the operation of the read cpu coverage information is stopped.

In the second case: when the system supports cpu retention, when the PMC enters the stage from isolation enable to power down, namely in the PMC _ ISO _ ON state, when the wakeup source appears in this stage, the PMC can be controlled to jump to normal run mode in the third cycle of the src _ clk.

In the first case and the second case, a hold signal may be pulled up in the third cycle of the src _ clk, so as to complete the information synchronization of the PMC and the CPU. Namely, the PMC controls the timing of the internal low-speed SIRC clock to enable the power management controller to be in a normal operation mode in the same timing, and enables a holdsleepn signal acting on the CPU to be in a high-invalid state, so that the CPU is enabled to complete the jump to the normal operation mode.

S308, synchronously waking up the source wakeup signal to the CPU to wake up the CPU;

in the process of preparing to enter a standby state, if the PMC receives a response message fed back by the CPU based on the holdlepn signal and recognizes that a wakeup source wakeup signal occurs, it is required to synchronize the wakeup source wakeup signal to the CPU to perform wakeup processing on the CPU.

And S309, enabling the power management system to enter a normal operation mode.

The information synchronization of the power management controller and the CPU is completed based on the condition that the holdlepn signal is in a high invalid state, so that the power management system enters a normal operation mode, the whole power management system enters the normal operation mode, and the risk of hang-up or run-off of the CPU is avoided.

Based on the method shown in fig. 3, a holdslepen signal can be set between the PMC and the CPU, and is associated with an internal low-speed SIRC clock timing sequence, so that the CPU can keep an instruction-not-executed process when preparing to enter a standby state, the holdslepen signal is in a high-invalid state when receiving a wake-up source trigger, and the CPU can enter a normal operation mode when the CPU is in a CPU memory retention control state, so that the CPU and the power management controller can both be in a normal operation mode, thereby avoiding the CPU from being hung up or running away, enabling the CPU and the power management controller to operate in the same mechanism, and achieving information synchronization in the normal operation mode.

Example III,

Specifically, fig. 3 shows a flowchart of a second method for suspending a standby operation of a power management system in an embodiment of the present invention, where the method shown in fig. 3 is implemented according to the power management system shown in fig. 1, and in a third embodiment, the power management system supports CPU memory retention control and needs to perform low power consumption control on a flash, the method includes the following steps:

in the process that a CPU is prepared to carry out power failure, because the system supports CPU memory permission control, the system needs to enter a CPU permission read request stage, namely, the PMC _ WAIT _ CPU _ HOLD state needs to be switched into a PMC _ RDCPU _ REQ state, under the PMC _ RDCPU _ REQ state, a CPU is supplied with power but does not execute an instruction, the PMC generates a CPU memory instruction and then sends the CPU memory instruction to a CPU memory static storage unit, and the CPU memory static storage unit reads a current operation instruction from the CPU based on the CPU memory instruction and writes the operation instruction into the CPU memory static storage unit; if the entire retention control is complete, the PMC needs to enter into an isolation ON enable state, i.e., PMC _ ISO _ ON state. In a PMC _ ISO _ ON state, a CPU is in a PMC hold state, the PMC is in normal operation, and it is necessary to enable the PMC to enter a mode with the lowest power consumption from normal operation to complete a system isolation enabling state, and after the system isolation enabling state is completed, a system ON chip turns off the power of most digital circuits, and only an external wake-up source is reserved to enter a STANDBY mode.

The holdslepen signal is a signal for holding the CPU in the status of the CPU, and is generated by the PMC and sent to the CPU, and the CPU receives the signal and holds the CPU status. During entering the STANDBY mode, the holdslepen signal is set to be invalid in the second beat when the PMC synchronous wakeup source occurs.

After the PMC receives the deep sleep instruction, generating a holdselepen signal for a CPU to keep not executing the instruction, and sending the holdselepen signal to the CPU, wherein the holdselepen signal comprises the following steps: the PMC generates a holdslepen signal based on an internal low speed SIRC clock (src _ clk) timing after receiving the deep sleep instruction.

note that, preparing the power management system to enter the standby state includes: judging whether the power management system supports a CPU memory function; if the CPU supports the CPU memory function, the PMC sends a CPU memory instruction to a CPU memory control unit; if the CPU does not support the CPU memory function, the PMC triggers the power management system to enter an isolation enabling state.

In this embodiment, since the system supports CPU memory retention control, the CPU memory control unit herein receives the CPU memory command and performs an operation of reading CPU memory information based on the CPU memory command.

In step S303, the PMC controls the hash to enter a low power consumption mode, which needs to control the flash control signal in different power consumption modes, so that the flash control signal is ready to enter a standby state.

S304, identifying the appearance of a wakeup source wakeup signal by the PMC;

S306, controlling the internal low-speed SIRC clock timing to enable a holdsleepn signal acting on the CPU to be in a high invalid state;

in the process of preparing to enter a standby state, if the PMC does not receive a response message fed back by the CPU based on the holdselepen signal and recognizes that a wake-up source wakeup signal appears, controlling the internal low-speed SIRC clock timing to enable the holdselepen signal acting on the CPU to be in a high invalid state.

here, the performing information synchronization of the power management controller and the CPU based on the holdsleepn signal being in the high inactive state includes: and when the internal low-speed SIRC clock timing is controlled to enable a holdsleepn signal acting on the CPU to be in a high invalid state, the internal low-speed SIRC clock timing is controlled to jump the PMC back to a normal operation mode.

In the first case and the second case, a hold holdslepen signal may be pulled up in the third cycle of src _ clk, so as to complete the information synchronization of PMC and CPU. Namely, the PMC controls the timing of the internal low-speed SIRC clock to enable the power management controller to be in a normal operation mode in the same timing, and enables a holdsleepn signal acting on the CPU to be in a high-invalid state, so that the CPU is enabled to complete the jump to the normal operation mode.

in the process of preparing to enter a standby state, if the PMC receives a response message fed back by the CPU based on the holdslepen signal and recognizes that a wakeup source wakeup signal appears, it is required to synchronize the wakeup source wakeup signal to the CPU to perform wakeup processing on the CPU.

The information synchronization of the power management controller and the CPU is completed based on the condition that the holdlepn signal is in a high invalid state, so that the power management system enters a normal operation mode, the whole power management system enters the normal operation mode, and the risk of running away or hang-up of the CPU is avoided.

During the step S309, in the process of making the power management system enter the normal operation mode, the internal low-speed SIRC clock timing needs to be controlled to act on the flash memory unit so that the flash memory unit jumps back to the normal operation mode from the standby state.

It should be noted that the controlling the internal low-speed SIRC clock timing to act on the flash memory cell so that the flash memory cell jumps back to the normal operation mode from the standby state includes: identifying a low power mode of the flash memory cell; and controlling the internal low-speed SIRC clock timing to act on the control signal timing corresponding to the low power consumption mode, so that the flash memory unit jumps back to the normal operation mode from the standby mode.

Since the flash has two low power consumption modes of DPD and power off, the control signal of the flash needs to be controlled in different power consumption modes.

Fig. 4 is a first diagram illustrating a timing sequence of a wake-up control signal when the PMC enters a standby mode, where a flash is a Deep Power Down (DPD) low Power mode, after the PMC is powered on for the first time, a fls _ DPD signal is always kept low, and the PMC controls other control signals of the flash during the standby mode.

Fig. 5 is a second schematic diagram illustrating timing of waking up control signals when the PMC enters the standby mode according to an embodiment of the present invention, where flash is a power-off low power consumption mode, and when the flash is power-off, after the first power-on, the fls _ probb and fls _ suppyon signals are all kept high, and if the PMC controls the fls _ probb and fls _ suppyon signals during entering the standby mode, the PMC wakes up during entering the standby mode.

It should be noted that here wakeup (sync 2) occurs in ds2iso phase, and except that holdlepn is pulled down, other control signals will maintain the original values, and the holdlepn signal will be pulled up immediately when PMC enters run mode.

According to the method provided by the embodiment of the invention, the holdslepen signal is arranged between the PMC and the CPU and is related to the internal low-speed SIRC clock time sequence, so that the CPU can keep the instruction-free process when the CPU is ready to enter the standby state, the holdslepen signal is in the high-invalid state when the wake-up source trigger is received, and the CPU can enter the normal operation mode, so that the CPU and the power management controller can be in the normal operation mode, the CPU operation is prevented from being hung up or running away, the running mechanisms of the CPU and the power management controller are the same, and the information synchronization under the normal mode running can be achieved.

Example four

Specifically, fig. 3 shows a flowchart of a second method for suspending a standby operation of a power management system in an embodiment of the present invention, where the method shown in fig. 3 is implemented according to the power management system shown in fig. 1, and in a fourth embodiment, the power management system does not support CPU memory permission control, and the method includes the following steps:

when the SOC is in the normal running RUN mode, and when the SOC is required to enter the STANDBY mode STANDBY, in order to ensure the state change, it needs to WAIT for the PMC _ WAIT _ CPU _ HOLD, PMC _ ISO _ ON, and so ON, to enter the STANDBY mode, where:

in the process that a CPU is ready to power down, a power management system does not support CPU memory permission control, the state of PMC _ WAIT _ CPU _ HOLD needs to be switched into a PMC _ ISO _ ON state, namely in the PMC _ ISO _ ON state, the CPU is in a PMC HOLD state, the PMC is in normal operation, the PMC needs to enter a mode with lowest power consumption from normal operation to complete a system isolation enabling state, after the system isolation enabling state is completed, a system ON chip closes power supply of most digital circuits, and only an external wake-up source is reserved to enter a STANDBY mode.

S302, after receiving a deep sleep instruction, a PMC generates a hold slepen signal for a CPU to keep not executing the instruction, and sends the hold slepen signal to the CPU;

in the process of waiting for the states of PMC _ WAIT _ CPU _ HOLD, PMC _ ISO _ ON and the like to enter the STANDBY mode, the CPU only does not execute instructions, but is supplied with power by the power module.

A deep sleep instruction, a holdsleepn signal and a holdsleep _ ackn are arranged between the CPU and the PMC to realize the synchronization process between the CPU and the PMC.

After the PMC receives the deep sleep instruction, generating a holdsleepn signal for a CPU to hold an unexecuted instruction, and sending the holdsleepn signal to the CPU comprises the following steps: the PMC generates a holdslepen signal based on internal low speed SIRC clock (sirclk) timing after receiving the deep sleep instruction.

note that, preparing the power management system to enter the standby state includes: judging whether the power management system supports a CPU memory function; if the CPU supports the CPU memory function, the PMC sends a CPU memory instruction to a CPU memory control unit; and if the CPU does not support the CPU memory function, the PMC triggers the power management system to enter an isolation enabling state. Since the CPU memory function is not supported here, the PMC triggers the power management system to directly enter the isolation enable state.

It should be noted that, in this process, the PMC may control the hash to enter the low power consumption mode, and it needs to control the flash control signal in different power consumption modes, so that it is ready to enter the standby state.

S304, the PMC identifies the appearance of a wakeup source wakeup signal;

the HOLD _ ackn is an acknowledger signal that is used for feeding back the CPU after the CPU receives the HOLD signal and held, that is, the response message here, and for receiving the response message, it indicates that the CPU in the states of PMC _ WAIT _ CPU _ HOLD, PMC _ RDCPU _ REQ, PMC _ ISO _ ON and the like is not powered down yet in the three stages, and it can release the HOLD valid state at any time and enter the RUN mode.

here, the performing information synchronization of the power management controller and the CPU based on the holdsleepn signal being in the high inactive state includes: and when the internal low-speed SIRC clock timing is controlled to enable a holdslepen signal acting on the CPU to be in a high inactive state, the internal low-speed SIRC clock timing is controlled to jump the PMC back to a normal operation mode.

Because the system does not support cpu retention, when the PMC enters the stage from isolation enable to power down, namely in the PMC _ ISO _ ON state, and when the wakeup source appears in this stage, the PMC can be controlled to jump to normal run mode in the third cycle of the src _ clk.

In this case, the hold holdleepn signal may be pulled up in the third cycle of the src _ clk, so as to complete the information synchronization of the PMC and the CPU. Namely, the PMC controls the timing of the internal low-speed SIRC clock to enable the power management controller to be in a normal operation mode in the same timing, and enables a holdsleepn signal acting on the CPU to be in a high-invalid state, so that the CPU is enabled to complete the jump to the normal operation mode.

It should be noted that, in the process of making the power management system enter the normal operation mode, the internal low-speed SIRC clock timing needs to be controlled to act on the flash memory unit so that the flash memory unit jumps back to the normal operation mode from the standby state.

Since the flash has two low power consumption modes, namely DPD mode and power off mode, it is necessary to control the control signal of the flash in different power consumption modes.

The computer readable storage medium may be an internal storage unit of the device according to the foregoing embodiment, such as a hard disk or a memory. The computer readable storage medium may be an external storage device of the above-described apparatus, such as a plug-in hard disk, a Smart Media Card (SMC), a Secure Digital (SD) Card, a Flash memory Card (Flash Card), and the like. Further, the computer-readable storage medium may include both an internal storage unit and an external storage device of the device. The computer-readable storage medium is used for storing the computer program and other programs and data required by the apparatus. The above-described computer-readable storage medium may also be used to temporarily store data that has been output or is to be output.

It will be understood by those skilled in the art that all or part of the processes of the methods of the above embodiments may be implemented by a computer program, which can be stored in a computer-readable storage medium, and can include the processes of the above embodiments of the methods when the computer program is executed. And the aforementioned storage medium includes: various media that can store program codes, such as ROM, RAM, magnetic or optical disks.

The above embodiments of the present invention are described in detail, and the principle and the implementation of the present invention are described herein by using specific embodiments, and the description of the above embodiments is only used to help understanding the method of the present invention and the core idea thereof; meanwhile, for a person skilled in the art, according to the idea of the present invention, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present invention.

Claims

1. A method of suspending standby operation of a power management system, the method comprising the steps of:

after receiving the deep sleep instruction, the PMC generates a hold leepn signal for keeping the CPU not to execute the instruction, and sends the hold leepn signal to the CPU;

in the process of preparing to enter a standby state, if the PMC does not receive a response message fed back by the CPU based on the holdselepen signal and recognizes that a wakeup source wakeup signal appears, controlling the internal low-speed SIRC clock timing sequence to enable the holdselepen signal acting on the CPU to be in a high invalid state;

2. The method of claim 1, wherein the preparing the power management system to enter the standby state comprises:

3. The method of suspending power management system standby operations of claim 2, the method further comprising:

4. The method of claim 3, wherein the reading CPU memory information based on the CPU memory instruction comprises:

5. The method of suspending standby operation of a power management system as set forth in claim 1, wherein said completing synchronization of information of a power management controller and a CPU based on said holdsleepn signal being in a high inactive state comprises:

and when the internal low-speed SIRC clock timing is controlled to enable a holdsleepn signal acting on the CPU to be in a high invalid state, the internal low-speed SIRC clock timing is controlled to jump the PMC back to a normal operation mode.

6. The method of suspending power management system standby operation of claim 1, the method further comprising:

7. The method of suspending power management system standby operation of claim 6 wherein controlling the internal low speed SIRC clock timing to act on the flash memory cells such that the flash memory cells jump back from a standby state to a normal operating mode comprises:

identifying a low power mode of the flash memory cell;

8. A power management system, the power management system comprising:

the power management controller PMC is used for generating a hold leepn signal of a CPU (central processing unit) for keeping an instruction not executed after receiving a deep sleep instruction, and sending the hold leepn signal to the CPU; controlling the timing sequence of an internal low-speed SIRC clock to enable a holdsleepn signal acting on a CPU to be in a low effective state, and enabling a power management system to be ready to enter a standby state; in the process of preparing to enter a standby state, if the PMC does not receive a response message fed back by the CPU based on the holdslepen signal and identifies that a wakeup source wakeup signal appears, controlling the internal low-speed SIRC clock timing sequence to enable the holdslepen signal acting on the CPU to be in a high invalid state; completing information synchronization of a power management controller and a CPU based on the condition that the holdlepn signal is in a high invalid state, so that the power management system enters a normal operation mode;

9. The power management system of claim 8, wherein the power management system further comprises:

10. The power management system of claim 8, wherein the power management system further comprises: