CN108334422B

CN108334422B - Method for controlling cold restart of heterogeneous hybrid memory system and BMC

Info

Publication number: CN108334422B
Application number: CN201810089557.5A
Authority: CN
Inventors: 王龙飞; 罗刚
Original assignee: Zhengzhou Yunhai Information Technology Co Ltd
Current assignee: Zhengzhou Yunhai Information Technology Co Ltd
Priority date: 2018-01-30
Filing date: 2018-01-30
Publication date: 2022-02-18
Anticipated expiration: 2038-01-30
Also published as: CN108334422A

Abstract

The invention discloses a method for controlling a cold restart of a heterogeneous hybrid memory system and a BMC (baseboard management controller). after a computer system sends a cold restart signal, a data protection signal is generated so that a NVM (non-volatile memory) in the computer system can write back data after receiving the data protection signal; after the NVM is detected to finish data write-back operation, the CPLD is controlled to perform power-off operation on the computing board and then perform power-on operation, and after the computing board is powered on, the BIOS is guided to perform QPI starting; and after finishing QPI starting, the BIOS controls the communication of a channel for accessing the NVM by the CPU in the computer system, controls the memory information interaction between the DRAM and the NVM in the computer system, guides the BIOS to finish the residual starting process and controls the computer system to finish cold restart. The method and the device protect the data in the heterogeneous hybrid memory when the computer system is restarted in a cold state, so that the computer system where the heterogeneous hybrid memory is located can be normally used.

Description

Method for controlling cold restart of heterogeneous hybrid memory system and BMC

Technical Field

The invention relates to the technical field of storage, in particular to a method for controlling a cold restart of a heterogeneous hybrid memory system and BMC.

Background

With the development of Memory technology, a new type of Memory medium NVM (Non-Volatile Memory) is gradually becoming widely used. The NVM has the advantages of bit-based access capability, no data loss after power failure, high storage density, low static power consumption, high dynamic power consumption, strong expandability and the like. However, the writing latency of NVM is one or several orders of magnitude slower than that of currently used DRAM (Dynamic Random Access Memory), and the writing times are also limited, so in order to meet the real-time requirement of the computer system, the DRAM and NVM are connected together on the system bus to form a heterogeneous hybrid Memory, which has the advantages of both DRAM and NVM.

However, when the computer system needs to be cold restarted (i.e., power off and then power on), if the data in the NVM is not written back for protection, the computing board is powered off directly, which will cause the computer system to be unable to be used normally after cold restart, and therefore how to control the computer system where the heterogeneous hybrid memory is located to complete cold restart and implement normal use needs to be considered during cold restart.

Therefore, how to provide a solution to the above technical problem is a problem that needs to be solved by those skilled in the art.

Disclosure of Invention

The invention aims to provide a method for controlling the cold restart of a heterogeneous hybrid memory system and a BMC (baseboard management controller), which protect data in the heterogeneous hybrid memory when a computer system is in the cold restart and enable the computer system where the heterogeneous hybrid memory is located to be normally used.

In order to solve the above technical problem, the present invention provides a method for controlling a cold reboot of a heterogeneous hybrid memory system, which is applied to a baseboard management controller BMC in a computer system, and includes:

generating a data protection signal after the computer system sends a cold restart signal, so that a nonvolatile memory (NVM) in the computer system performs data write-back operation after receiving the data protection signal;

after detecting that the NVM finishes data write-back operation, controlling a Complex Programmable Logic Device (CPLD) to perform power-off operation on a computing board and then performing power-on operation, and after finishing power-on of the computing board, guiding a Basic Input and Output System (BIOS) to perform quick channel interconnection (QPI) starting;

and after completing QPI starting, the BIOS controls a CPU in the computer system to access a channel of the NVM to be communicated, controls memory information interaction between a Dynamic Random Access Memory (DRAM) in the computer system and the NVM, guides the BIOS to complete a residual starting process and controls the computer system to complete cold restart.

Preferably, after the CPLD is controlled to perform the power-off operation on the computing board, before the CPLD is controlled to perform the power-on operation on the computing board, the method further includes:

and starting timing after the computing board is powered off, and generating a power-on operation signal when the timing time reaches the preset time so that the CPLD can carry out power-on operation on the computing board after receiving the power-on operation signal.

Preferably, the preset time is 5 s.

Preferably, the process of controlling the channel communication of the CPU in the computer system accessing the NVM specifically includes:

respectively configuring a first Field Programmable Gate Array (FPGA) in the computer system and a second FPGA for mounting the NVM;

controlling communication of access channels between a CPU and a first FPGA in the computer system, and controlling communication of the access channels between the first FPGA and a second FPGA so that the CPU accesses the NVM sequentially through the first FPGA and the second FPGA.

Preferably, the memory information includes memory capacity and memory address.

Preferably, the process of controlling the memory information interaction between the DRAM and the NVM in the computer system specifically includes:

acquiring the memory information of a DRAM in the computer system from the CPU, and sending the memory information of the DRAM to the second FPGA;

obtaining the memory information of the NVM correspondingly determined by the second FPGA according to the memory information of the DRAM and the splicing sequence of the DRAM and the NVM from the second FPGA;

and sending the determined memory information of the NVM to the BIOS to complete the interaction of the memory information between the DRAM and the NVM.

Preferably, the process of respectively configuring the first field programmable gate array FPGA in the computer system and the second FPGA mounted on the NVM specifically includes:

and correspondingly writing specified data into the two chips according to the chip descriptions of the first FPGA and the second FPGA mounted on the NVM in the computer system.

Preferably, the process of booting the BIOS to perform QPI boot is specifically:

booting the BIOS to perform QPI slow start;

and after a restart signal generated after the BIOS completes QPI slow start is received, the BIOS is guided to carry out QPI fast start.

Preferably, the first FPGA is a Virtex72000T type FPGA, and the second FPGA is a Virtex 7690T type FPGA.

In order to solve the above technical problem, the present invention further provides a BMC for controlling a cold reboot of a heterogeneous hybrid memory system, including:

the data protection unit is used for generating a data protection signal after the computer system sends a cold restart signal so as to facilitate the data write-back operation of the NVM in the computer system after receiving the data protection signal;

the power-off and power-on unit is used for controlling the CPLD to perform power-off operation and then power-on operation on the computing board after detecting that the NVM completes data write-back operation, and guiding the BIOS to perform QPI starting after the computing board completes power-on;

and the cold restart unit is used for controlling the communication of a channel for accessing the NVM by a CPU in the computer system after the BIOS completes QPI starting, controlling the memory information interaction between the DRAM in the computer system and the NVM, guiding the BIOS to complete the residual starting process and controlling the computer system to complete the cold restart.

The invention provides a method for controlling cold restart of a heterogeneous hybrid memory system, which is applied to a Baseboard Management Controller (BMC) in a computer system. According to the method and the device, after the computer system sends the cold restart signal, the BMC in the computer system sends the data protection signal to the NVM, and the NVM performs data write-back operation after receiving the data protection signal. And when the BMC detects that the NVM finishes the data writing-back operation, the CPLD is controlled to perform power-off operation on the computing board and then perform power-on operation.

After the computing board finishes the power-on operation, the BIOS is guided by the BMC to carry out QPI starting, and the QPI is a quick interconnection channel between a CPU and other chips in the computer system. The BMC controls the CPU to access the channel communication of the NVM after the BIOS finishes QPI starting, controls the memory information interaction between the DRAM and the NVM, and then guides the BIOS to finish the residual starting process until the computer system runs to the operation interface of the startup to finish the starting process, thereby protecting the data in the heterogeneous hybrid memory when the computer system is in cold restart and enabling the computer system where the heterogeneous hybrid memory is located to be normally used.

The invention also provides a BMC for controlling the cold restart of the heterogeneous hybrid memory system, and the BMC has the same beneficial effect as the cold restart method.

Drawings

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed in the prior art and the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings without creative efforts.

Fig. 1 is a flowchart illustrating a method for controlling a cold reboot of a heterogeneous hybrid memory system according to the present invention;

fig. 2 is a schematic structural diagram of a BMC for controlling a cold reboot of a heterogeneous hybrid memory system according to the present invention.

Detailed Description

The core of the invention is to provide a method for controlling the cold restart of a heterogeneous hybrid memory system and a BMC, which protect data in the heterogeneous hybrid memory when a computer system is in the cold restart and enable the computer system where the heterogeneous hybrid memory is located to be normally used.

In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are some, but not all, embodiments of the present invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.

Referring to fig. 1, fig. 1 is a flowchart illustrating a method for controlling a cold reboot of a heterogeneous hybrid memory system according to the present invention.

The method is applied to BMC (Baseboard Management Controller) in a computer system, and comprises the following steps:

step S1: generating a data protection signal after the computer system sends a cold restart signal so as to facilitate the data write-back operation of a nonvolatile memory (NVM) in the computer system after receiving the data protection signal;

specifically, the BMC is usually included in a main board or a main circuit board of a device to be monitored, and is often used to monitor and manage an operation state of a server, such as turning on and off in an out-of-band manner, monitoring a sensor state of the server, accessing a BIOS (Basic Input Output System) configuration or accessing console information of an operating System, and the like.

After the computer system sends a cold restart signal, in order to prevent data loss which is not written back by the NVM in the computer system, the data protection signal is generated by the BMC in the computer system and is sent to the NVM, and after the NVM receives the data protection signal, data write-back operation is carried out.

Step S2: after the NVM is detected to finish data write-back operation, the complex programmable logic device CPLD is controlled to perform power-off operation on the computing board and then perform power-on operation, and after the computing board is powered on, the basic input and output system BIOS is guided to perform quick channel interconnection QPI starting;

specifically, the computer system is powered off and then powered on after the computer system is restarted in a cold state. When the BMC detects that the NVM completes data write-back operation, the BMC controls the CPLD (Complex Programmable Logic Device) to firstly perform power-off operation on the computing board and then perform power-on operation on the computing board, so that the computer system can be started and operated.

When the computer system is started, the BIOS is first entered. The BIOS is a set of programs that are fixed on a ROM (Read Only Memory) chip in a computer system, and the BIOS programs include a basic input/output program, a self-test program after power-on, and a system self-starting program.

Therefore, after the computing board of the computer system is powered on, the BMC in the computer system first directs the BIOS to perform QPI (Quick Path Interconnect) start, where QPI is a framework of Quick Interconnect between chips (such as a CPU and other chips in the system) in the computer system, and is mainly used for data transmission, and data transmission completed through QPI has a higher data transmission rate.

Step S3: and after finishing QPI starting, the BIOS controls the communication of a channel for accessing the NVM by the CPU in the computer system, controls the memory information interaction between the DRAM and the NVM in the computer system, guides the BIOS to finish the residual starting process and controls the computer system to finish cold restart.

Specifically, after the BIOS completes QPI startup, the BMC controls the channel communication of the CPU in the computer system accessing the NVM in the computer system, laying a foundation for the CPU accessing the NVM.

In addition, the memory in the computer system adopts a heterogeneous hybrid memory formed by combining DRAM and NVM which are connected on a bus of the computer system. The premise of combining the DRAM and the NVM into a heterogeneous hybrid memory is that the DRAM and the NVM interact with each other to obtain respective memory information. For example, if the memory of the NVM is spliced to the DRAM, the location of the NVM in the memory block can only be determined based on the memory information of the DRAM that is known to the NVM.

Therefore, in order to construct the heterogeneous hybrid memory, the BMC should control the memory information interaction between the DRAM and the NVM in the computer system, so as to determine the locations of the DRAM and the NVM in the memory block, thereby implementing the combination of the DRAM and the NVM into the heterogeneous hybrid memory.

Then, the BMC guides the BIOS to complete the remaining boot process, and the flag that the remaining boot process is completed is an operation interface for the computer system to run to boot, thereby completing the boot of the computer system.

On the basis of the above-described embodiment:

as a preferred embodiment, after the controlling CPLD performs the power-off operation on the computing board, before the controlling CPLD performs the power-on operation on the computing board, the method further includes:

It should be noted that the preset is set in advance, and only needs to be set once, and the preset does not need to be reset unless modified according to actual conditions.

Specifically, the BMC controls the CPLD to perform power-off operation and power-on operation on the computing board. In order to prevent the operation from being too frequent, the timing is started after the power of the computing board is cut off, and when the timing time reaches the set time, the BMC generates a power-on operation signal and sends the power-on operation signal to the CPLD. And the CPLD performs power-on operation on the computing board after receiving the power-on operation signal.

As a preferred embodiment, the preset time is 5 s.

Further, the interval time between the power-off operation and the power-on operation of the computing board in the present application may be, but is not limited to, 5s, and the present application is not particularly limited thereto.

As a preferred embodiment, the process of controlling the channel connectivity of the CPU accessing the NVM in the computer system specifically includes:

respectively configuring a first Field Programmable Gate Array (FPGA) and a second FPGA for mounting the NVM in the computer system;

and controlling the communication of an access channel between a CPU (central processing unit) and the first FPGA in the computer system and controlling the communication of the access channel between the first FPGA and the second FPGA so that the CPU accesses the NVM sequentially through the first FPGA and the second FPGA.

Further, a first FPGA (Field-Programmable gate array) and a second FPGA are included in the computer system, and the NVM in the computer system is mounted on the second FPGA. When a CPU in the computer system wants to access the NVM, the CPU needs to pass through a first FPGA and then a second FPGA. Therefore, in order to establish a link for the CPU to access the NVM, a first FPGA and a second FPGA should be configured separately.

According to the method and the system, the BMC configures the first FPGA in the computer system, and the purpose of configuring the first FPGA is to communicate an access channel between the CPU and the first FPGA, so that the CPU can access the first FPGA. In addition, the BMC also configures a second FPGA in the computer system, the purpose of configuring the second FPGA is similar to that of configuring the first FPGA, and the purpose is to communicate an access channel between the first FPGA and the second FPGA, so that the CPU can access the second FPGA through the first FPGA, and further the CPU accesses the NVM.

In a preferred embodiment, the memory information includes memory capacity and memory address.

Specifically, the memory information in the present application may include a memory capacity and a memory address, where the memory capacity represents a storage capacity of the memory, for example, the storage capacity of the 64MB memory is smaller than that of the 128MB memory, and the larger the memory capacity is, the more favorable the operation of the computer system is.

The memory address indicates the location of the memory in the memory block, and the memory address generally refers to the base address of the memory, i.e., the first address of the memory. Therefore, knowing the memory address and memory capacity of the memory, the tail address of the memory can be determined.

Of course, the memory information in the present application may also include other information, and the present application is not particularly limited herein, depending on the actual situation.

As a preferred embodiment, the process of controlling the memory information interaction between the DRAM and the NVM in the computer system specifically includes:

acquiring the memory information of the DRAM in the computer system from the CPU, and sending the memory information of the DRAM to the second FPGA;

Further, the DRAM is the memory of the CPU, so the BMC obtains the memory information of the DRAM, i.e., the memory address and the memory capacity of the DRAM, from the CPU. And because the NVM is hung on the second FPGA, the memory address and the memory capacity of the DRAM are sent to the second FPGA. And the second FPGA correspondingly determines the memory address and the memory capacity of the NVM according to the splicing sequence of the DRAM and the NVM and the memory address and the memory capacity of the DRAM.

Specifically, if the NVM is spliced behind the DRAM, the second FPGA, knowing the memory address and memory capacity of the DRAM, can determine the tail address of the DRAM, which is the first address of the NVM, and thus determine the location of the NVM in the memory block. If the NVM is spliced in front of the DRAM, the second FPGA knows the first address of the DRAM, the first address of the DRAM is the tail address of the NVM, and the second FPGA acquires the memory capacity of the NVM so as to determine the first address of the NVM, namely the memory address of the NVM.

The BMC can correspondingly acquire the determined memory information of the NVM from the second FPGA and send the determined memory information of the NVM to the BIOS, so that the interaction of the memory information between the DRAM and the NVM is completed.

As a preferred embodiment, the process of respectively configuring the first field programmable gate array FPGA and the second FPGA mounted on the NVM in the computer system specifically includes:

and writing specified data into the two chips correspondingly according to the chip descriptions of the two chips of the first FPGA and the second FPGA mounted with the NVM in the computer system.

Specifically, the process of configuring the first FPGA and the second FPGA by the BMC is a process of writing data into the register, and the written data is determined by chip descriptions of two chips of the first FPGA and the second FPGA. For example, the chip description of the first FPGA specifies that writing 0x01 to the 0x00 address of the first FPGA can communicate the CPU with the first FPGA, and the process of the BMC configuring the first FPGA is to write 0x01 to the 0x00 address of the first FPGA.

As a preferred embodiment, the process of booting the BIOS to perform QPI boot is specifically as follows:

booting the BIOS to perform QPI slow start;

and after receiving a restart signal generated after the BIOS completes the QPI slow start, booting the BIOS to carry out the QPI fast start.

Further, QPI is a framework for fast interconnection between chips in a computer system, and is limited by the chips themselves, and it cannot achieve a faster transmission speed by configuring QPI once. Therefore, BMC directs BIOS to perform QPI boot including slow boot and fast boot. The slow start refers to configuring the QPI and increasing the transmission speed to a slow level, and the fast start refers to reconfiguring the QPI again on the basis of the slow start to increase the transmission speed to a high level.

Specifically, the BMC directs the BIOS to QPI slow start. And the BIOS generates a restart signal after finishing the QPI slow start and sends the restart signal to the BMC. And the BMC guides the BIOS to carry out QPI quick start after receiving the restart signal.

As a preferred embodiment, the first FPGA is a Virtex72000T FPGA, and the second FPGA is a Virtex 7690T FPGA.

Specifically, the model of the first FPGA in the present application may be selected from, but not limited to, Virtex72000T, and the model of the second FPGA may be selected from, but not limited to, Virtex 7690T. As to the specific models of the first FPGA and the second FPGA, the present application is not particularly limited.

Referring to fig. 2, fig. 2 is a schematic structural diagram of a BMC for controlling a cold reboot of a heterogeneous hybrid memory system according to the present invention, where the BMC includes:

the data protection unit 1 is used for generating a data protection signal after the computer system sends a cold restart signal, so that the NVM in the computer system can write back data after receiving the data protection signal;

the power-off and power-on unit 2 is used for controlling the CPLD to perform power-off operation on the computing board and then perform power-on operation after detecting that the NVM completes data write-back operation, and guiding the BIOS to perform QPI starting after the computing board completes power-on;

and the cold restart unit 3 is used for controlling the communication of a channel for accessing the NVM by the CPU in the computer system after the BIOS completes the QPI start, controlling the memory information interaction between the DRAM and the NVM in the computer system, guiding the BIOS to complete the rest start process and controlling the computer system to complete the cold restart.

For the BMC introduction provided in the present application, reference is made to the above method embodiments, which are not repeated herein.

The embodiments in the present description are described in a progressive manner, each embodiment focuses on differences from other embodiments, and the same and similar parts among the embodiments are referred to each other. The device disclosed by the embodiment corresponds to the method disclosed by the embodiment, so that the description is simple, and the relevant points can be referred to the method part for description.

It is further noted that, in the present specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.

The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the invention. Thus, the present invention is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for controlling the cold restart of a heterogeneous hybrid memory system is applied to a Baseboard Management Controller (BMC) in a computer system, and is characterized by comprising the following steps:

after completing QPI starting, the BIOS controls a CPU in the computer system to access a channel of the NVM to be communicated, controls memory information interaction between a Dynamic Random Access Memory (DRAM) in the computer system and the NVM, guides the BIOS to complete a residual starting process and controls the computer system to complete cold restart;

wherein the process of controlling the channel communication of the CPU accessing the NVM in the computer system specifically comprises:

2. The method of claim 1, wherein after the controlling CPLD powers off the computing board, and before the controlling CPLD powers on the computing board, the method further comprises:

3. The method of claim 2, wherein the predetermined time is 5 s.

4. The method of claim 1, wherein the memory information comprises memory capacity and memory address.

5. The method according to claim 4, wherein the controlling of the memory information interaction between the DRAM and the NVM in the computer system comprises:

6. The method according to claim 1, wherein the process of separately configuring the first FPGA and the second FPGA for mounting the NVM in the computer system specifically comprises:

7. The method according to claim 5 or 6, wherein the booting of the BIOS to perform QPI boot is performed by specifically:

booting the BIOS to perform QPI slow start;

8. The method for controlling the cold reboot of a heterogeneous hybrid memory system according to claim 7, wherein the first FPGA is a Virtex72000T type FPGA, and the second FPGA is a Virtex 7690T type FPGA.

9. A BMC that controls a cold reboot of a heterogeneous hybrid memory system, comprising:

the cold restart unit is used for controlling the communication of a channel for accessing the NVM by a CPU in the computer system after the BIOS completes QPI starting, controlling the memory information interaction between a DRAM in the computer system and the NVM, guiding the BIOS to complete the residual starting process and controlling the computer system to complete cold restart;