CN113419884B - Method, device, terminal and storage medium for preventing BMC image file from being damaged - Google Patents

Method, device, terminal and storage medium for preventing BMC image file from being damaged Download PDF

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CN113419884B
CN113419884B CN202110653098.0A CN202110653098A CN113419884B CN 113419884 B CN113419884 B CN 113419884B CN 202110653098 A CN202110653098 A CN 202110653098A CN 113419884 B CN113419884 B CN 113419884B
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operation mode
bmc
chip
flash chip
configuration information
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CN113419884A (en
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彭继阳
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Suzhou Inspur Intelligent Technology Co Ltd
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Suzhou Inspur Intelligent Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
    • G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
    • G06F11/0709—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a distributed system consisting of a plurality of standalone computer nodes, e.g. clusters, client-server systems
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1446—Point-in-time backing up or restoration of persistent data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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  • General Engineering & Computer Science (AREA)
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  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Computer Hardware Design (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

The invention discloses a method, a device, a terminal and a storage medium for preventing a BMC image file from being damaged, wherein after a BMC master chip is restarted, operation mode information is actively sent to a flash chip to inform the flash chip of an operation mode required by the BMC master chip, the flash chip adjusts the operation mode according to the received operation mode information, the adjusted operation mode is ensured to be the operation mode required by the BMC master chip, and then the BMC master chip and the flash chip are normally interacted through the operation mode, so that the problem of inconsistent operation mode of the BMC master chip and the flash operation mode is avoided, the problem of damage of the BMC image file in the flash chip is avoided, the problem of damage of the BMC image file is fundamentally solved, the server is prevented from fault, the stable operation of the server is ensured, and the operation efficiency is improved.

Description

Method, device, terminal and storage medium for preventing BMC image file from being damaged
Technical Field
The invention relates to the field of server BMCs, in particular to a method, a device, a terminal and a storage medium for preventing BMC image files from being damaged.
Background
With the development of society, the computing power is gradually increased, the server scale is enlarged, the network delay requirement is higher, the service response requirement is faster, on the basis, the system is extremely easy to generate network storm, when the network is congested, the bottom chip continuously erases and writes the flash chip (memory chip) in the data interaction process, and in the process, if the main chip is restarted when meeting BMC (Baseboard Management Controller, a baseboard management controller), the BMC image file in the flash chip is damaged in a probabilistic manner. Under normal conditions, the interaction mode of the BMC main chip and the flash chip is consistent with the operation mode of the flash chip, so that normal erasing and writing can be ensured. When the BMC main chip is restarted, the BMC main chip is restarted in a default interaction mode, if the default interaction mode is different from the operation mode of the flash chip at the moment (when the BMC main chip is restarted), the BMC mirror image file in the flash chip is damaged, normal erasing and writing cannot be performed, a server is failed, and the server cannot stably operate. If the BMC image file in the flash chip is damaged, only a new version can be updated or the main board can be replaced for maintenance, so that the operation efficiency is greatly influenced.
Disclosure of Invention
In order to solve the problems, the invention provides a method, a device, a terminal and a storage medium for preventing BMC image files from being damaged, which avoid damaging BMC image files in a flash chip when a BMC main chip is restarted, avoid server faults, fundamentally solve the problems of lifting or mainboard maintenance, ensure stable operation of a server and provide operation efficiency.
In a first aspect, the present invention provides a method for preventing a BMC image file from being damaged, the method comprising the steps of:
after restarting the BMC main chip, the BMC main chip sends operation mode information to the flash chip;
the flash chip adjusts the operation mode according to the received operation mode information.
Further, the BMC main chip sends operation mode information to the flash chip, specifically:
and the BMC main chip sends operation mode information to the flash chip through the SPI bus.
Further, the BMC main chip sends operation mode information to the flash chip through the SPI bus, specifically:
and the BMC main chip sends the register configuration information to the flash chip through the SPI bus.
Further, the flash chip adjusts the operation mode according to the received operation mode information, specifically:
the flash chip detects whether the register configuration information is reconfigured in real time;
if so, the operating mode is adjusted according to the new configuration information.
In a second aspect, the present invention provides an apparatus for preventing BMC image files from being damaged, the apparatus comprising,
an operation mode information sending module: the method comprises the steps that the method operates on a BMC main chip, and after the BMC main chip is restarted, operation mode information is sent to a flash chip;
the operation module adjusting module: and operating on the flash chip, and adjusting the operation mode according to the received operation mode information.
Further, the operation mode information sending module sends operation mode information to the flash chip, specifically:
and sending the operation mode information to the flash chip through the SPI bus.
Further, the running mode information is sent to the flash chip through the SPI bus, specifically:
and sending the register configuration information to the flash chip through the SPI bus.
Further, the operation module adjusting module adjusts the operation mode according to the received operation mode information, specifically:
detecting in real time whether a register is reconfigured;
if so, the operating mode is adjusted according to the new configuration information.
In a third aspect, a technical solution of the present invention provides a terminal, including:
a processor;
a memory for storing execution instructions of the processor;
wherein the processor is configured to the method of any of the above.
In a fourth aspect, the present invention provides a computer-readable storage medium storing a computer program which, when executed by a processor, implements a method as described in any one of the preceding claims.
The method, the device, the terminal and the storage medium for preventing the BMC image file from being damaged have the following beneficial effects compared with the prior art: after the BMC master chip is restarted, the operation mode information is actively sent to the flash chip, the flash chip is informed of the operation mode required by the BMC master chip, the operation mode is adjusted according to the received operation mode information, the adjusted operation mode is guaranteed to be the operation mode required by the BMC master chip, then the BMC master chip and the flash chip interact normally through the operation mode, the problem that the operation mode of the BMC master chip is inconsistent with the operation mode of the flash chip is avoided, the problem that BMC mirror files in the flash chip are damaged is avoided, the problem that the BMC mirror files are damaged is fundamentally solved, server faults are avoided, stable operation of a server is guaranteed, and operation efficiency is improved.
Drawings
For a clearer description of embodiments of the present application or of the prior art, the drawings that are used in the description of the embodiments or of the prior art will be briefly described, it being apparent that the drawings in the description that follow are only some embodiments of the present application, and that other drawings may be obtained from these drawings by a person of ordinary skill in the art without inventive effort.
FIG. 1 is a flowchart illustrating a method for preventing BMC image files from being damaged according to an embodiment of the present invention;
FIG. 2 is a schematic block diagram of an apparatus for preventing BMC image files from being damaged according to a third embodiment of the present invention;
fig. 3 is a schematic structural diagram of a terminal according to a fifth embodiment of the present invention.
Detailed Description
The method, the device, the terminal and the storage medium for preventing the BMC image file from being damaged are characterized in that when the BMC master chip 100 is restarted, the BMC master chip 100 actively informs the flash chip 200 to adjust the operation mode, so that the operation mode of the flash chip 200 is adjusted to be the operation mode required by the BMC master chip 100, the operation modes of the BMC master chip 100 and the flash chip 200 are ensured to be consistent, the BMC master chip 100 and the flash chip 200 can interact normally, data erasure is performed, and the BMC image file in the flash chip 200 is prevented from being damaged.
In order to provide a better understanding of the present application, those skilled in the art will now make further details of the present application with reference to the drawings and detailed description. It will be apparent that the described embodiments are only some, but not all, of the embodiments of the present application. All other embodiments, which can be made by one of ordinary skill in the art without undue burden from the present disclosure, are within the scope of the present disclosure.
Example 1
The flash chip 200 generally has various operation modes, such as a 1/4bit command mode (1/4 bit command mode), a 3/4 byte ADDR mode (3/4 byte address mode), performance enhance mode (performance enhancing module)/continue read mode (continuous read mode), which will be hereinafter referred to as a mode one, a mode two, a mode three and a mode four. Normally, the BMC host chip 100 interacts with the flash chip 200 in one of the modes, e.g., the BMC host chip 100 interacts with the flash chip 200 in mode one. After the BMC main chip 100 and the flash chip 200 are powered up for the first time, the BMC main chip 100 and the flash chip 200 interact in one of the modes by default, for example, interact in the third mode by default. In the interaction process, possibly due to performance requirements and the like, the BMC master chip 100 may change the interaction mode, for example, change the operation state to the mode four to interact with the flash, and then the flash chip 200 may also change to the mode four to operate, so as to ensure that the BMC master chip 100 and the flash chip 200 can interact normally. After the interaction mode is changed, if the BMC master chip 100 is restarted, the running state of the BMC master chip 100 is reset to the default mode three interaction mode, and at this time, the flash chip 200 is still in the mode four running mode, and the two modes are inconsistent, so that normal interaction cannot be performed, and the BMC image file in the flash chip 200 is damaged.
Therefore, in the first embodiment, a method for preventing the BMC image file from being damaged is provided, and the flash chip 200 is actively adjusted to the operation mode consistent with the BMC master chip 100 when restarting.
As shown in fig. 1, the method for preventing the BMC image file from being damaged in the first embodiment specifically includes the following steps:
s101, after restarting the BMC master chip 100, the BMC master chip 100 sends operation mode information to the flash chip 200;
s102, the flash chip 200 adjusts the operation mode according to the received operation mode information.
According to the method, after the BMC master chip 100 is restarted, the operation mode information is actively sent to the flash chip 200, the flash chip 200 is informed of the operation mode required by the BMC master chip 100, the flash chip 200 adjusts the operation mode according to the received operation mode information, the adjusted operation mode is guaranteed to be the operation mode required by the BMC master chip 100, then the BMC master chip 100 and the flash chip 200 interact normally through the operation mode, the problem that the operation mode of the BMC master chip 100 is inconsistent with the operation mode of the flash chip 200 cannot occur, and therefore the problem that BMC mirror files in the flash chip 200 are damaged is avoided, the problem that the BMC mirror files are damaged is fundamentally solved, server faults are avoided, stable operation of a server is guaranteed, and operation efficiency is improved.
Example two
In order to facilitate the detailed understanding of the present invention, a method for preventing the BMC image file from being damaged is further described below based on the principles of the present invention.
Specifically, a method for preventing the BMC image file from being damaged in the second embodiment includes the following steps.
S201, after the BMC master chip 100 is restarted, the BMC master chip 100 sends operation mode information to the flash chip 200.
Considering that the BMC main chip 100 and the flash chip 200 are connected through an SPI (Serial Peripheral Interface ) bus, in this step, the BMC main chip 100 sends operation mode information to the flash chip 200, specifically:
the BMC host chip 100 transmits operation mode information to the flash chip 200 through the SPI bus.
That is, after the BMC main chip 100 is restarted, it communicates with the flash chip 200 through the SPI bus first, and the operation mode (for example, mode three) required by the BMC main chip 100 at this time is sent to the flash chip 200, so that the flash chip 200 adjusts its own operation mode. The operation mode required by the BMC host chip 100 refers to an operation state in which the operation state of the BMC host chip 100 is the operation state in which the operation mode interacts, for example, the BMC host chip 100 defaults to interact with the flash chip 200 in mode three.
The operation mode of the flash chip 200 corresponds to the configuration information in the register thereof, and the flash chip 200 adjusts the operation mode according to the configuration information in the register thereof, for example, four operation modes of the flash chip 200 respectively correspond to the configuration information in the register thereof as 00, 01, 10 and 11.
Based on this, the BMC master chip 100 sends operation mode information to the flash chip 200 through the SPI bus, specifically:
the BMC host chip 100 transmits register configuration information to the flash chip 200 through the SPI bus.
That is, after the BMC master chip 100 is restarted, the BMC master chip 100 sends the register configuration information to the flash chip 200 through the SPI bus, and reconfigures the register configuration in the flash chip 200. For example, if the default operation mode after the restart of the BMC master chip 100 is mode three, after the restart of the BMC master chip 100, the configuration information of the register sent by the BMC master chip 100 to the flash chip 200 through the SPI bus is to change the configuration in the register to mode 10.
S202, the flash chip 200 adjusts the operation mode according to the received operation mode information.
After restarting the BMC master chip 100, the BMC master chip 100 sends register configuration information to the flash chip 200 through the SPI bus, the register configuration in the flash chip 200 is reconfigured, and the flash chip 200 adjusts the operation mode according to the received operation mode information, specifically, adjusts the operation mode according to the register configuration information. The flash chip 200 needs to timely determine whether the configuration information of the register is reconfigured, and when in implementation, the method comprises the following steps:
in step one, the flash chip 200 detects whether the register configuration information is reconfigured in real time.
It should be noted that, a time interval for the flash chip 200 to monitor the register configuration information, for example, detection once for 10 seconds or detection once for 1 minute, may be set, and the flash chip 200 implements the monitor register according to the set time interval to detect whether the register configuration information is reconfigured.
And step two, if the configuration is reconfigured, the operation mode is adjusted according to the new configuration information.
When the configuration information of the register is reconfigured, the flash chip 200 adjusts the operation mode according to the new configuration information of the register. For example, if the configuration information of the register is configured to be 10, the flash chip 200 adjusts its operation mode to be mode three, so as to ensure that the operation mode of the flash chip 200 is consistent with the operation mode of the BMC main chip 100, so that the two modes can interact normally, and damage to the BMC image file in the flash chip 200 is avoided.
It should be noted that, the flash chip 200 may determine whether the new configuration information is consistent with the previous configuration information (i.e. before the BMC main chip 100 is restarted), if so, the flash chip 200 does not operate any more, and if not, the operation mode is adjusted according to the new configuration information. Of course, the flash chip 200 may not determine whether the new configuration information is consistent with the previous configuration information, and only after the register configuration information is reconfigured, the operation mode may be readjusted according to the new configuration information.
According to the method, after the BMC master chip 100 is restarted, the operation mode information is actively sent to the flash chip 200, the flash chip 200 is informed of the operation mode required by the BMC master chip 100, the flash chip 200 adjusts the operation mode according to the received operation mode information, the adjusted operation mode is guaranteed to be the operation mode required by the BMC master chip 100, then the BMC master chip 100 and the flash chip 200 interact normally through the operation mode, the problem that the operation mode of the BMC master chip 100 is inconsistent with the operation mode of the flash chip 200 cannot occur, and therefore the problem that BMC mirror files in the flash chip 200 are damaged is avoided, the problem that the BMC mirror files are damaged is fundamentally solved, server faults are avoided, stable operation of a server is guaranteed, and operation efficiency is improved.
For a further detailed understanding of the invention, several embodiments of the invention that can be implemented are described below on the basis of the invention.
In one embodiment, the method comprises the following steps.
S301, powering up the BMC main chip 100 and the flash chip 200, wherein the BMC main chip 100 and the flash chip 200 operate in a default operation mode (mode three is taken as an example for illustration in the mode operation mode below), and the BMC main chip 100 and the flash chip 200 interact normally in the mode three.
In the interaction process of the BMC master chip 100 and the flash chip 200, the BMC master chip 100 changes the operation mode to the mode four, and meanwhile, the BMC master chip 100 notifies the flash chip 200 to change the operation mode to the mode four, and then the BMC master chip 100 and the flash chip 200 interact normally in the mode four.
S303, restarting the BMC main chip 100, resetting the running mode of the BMC main chip 100 to a default mode III, and sending register configuration information to the flash chip 200 by the BMC main chip 100 through the SPI bus.
It should be noted that, the transmitted configuration information of the register is the configuration information for adjusting the operation mode of the flash chip 200 to the mode three, i.e. the configuration information of the register is reconfigured to 10. Before the BMC master chip 100 is restarted, the configuration information in the register of the flash chip 200 is 11, i.e. the configuration information of the mode four.
S304, the flash chip 200 detects whether the register configuration information is reconfigured in real time.
S305, if the configuration information of the register is reconfigured, judging whether the new configuration information is the same as the previous configuration information;
s306, the flash chip 200 judges that the new configuration information is different from the previous configuration information, and then adjusts the operation mode according to the new configuration information of the register.
It should be noted that, at this time, the flash chip 200 adjusts the operation mode from the fourth mode to the third mode.
S307, the BMC main chip 100 and the flash chip 200 continue to interact normally in mode three.
The second embodiment comprises the following steps.
S401, the BMC main chip 100 and the flash chip 200 are powered on, and the BMC main chip 100 and the flash chip 200 both operate in a default operation mode (hereinafter, the mode operation mode is described as a mode three, which is an example), and the BMC main chip 100 and the flash chip 200 interact normally in this mode three.
In the interaction process of the BMC master chip 100 and the flash chip 200, the BMC master chip 100 changes the operation mode to the mode four, and meanwhile, the BMC master chip 100 notifies the flash chip 200 to change the operation mode to the mode four, and then the BMC master chip 100 and the flash chip 200 interact normally in the mode four.
S403, the BMC master chip 100 is restarted, the running mode of the BMC master chip 100 is reset to a default mode III, and the BMC master chip 100 sends register configuration information to the flash chip 200 through the SPI bus.
It should be noted that, the transmitted configuration information of the register is the configuration information for adjusting the operation mode of the flash chip 200 to the mode three, i.e. the configuration information of the register is reconfigured to 10. Before the BMC master chip 100 is restarted, the configuration information in the register of the flash chip 200 is 11, i.e. the configuration information of the mode four.
S404, the flash chip 200 detects in real time whether the register configuration information is reconfigured.
S405, if the configuration information of the register is reconfigured, the flash chip 200 performs operation mode adjustment according to the new configuration information of the register.
It should be noted that, at this time, the flash chip 200 adjusts the operation mode from the fourth mode to the third mode.
S406, the BMC main chip 100 and the flash chip 200 continue to normally interact in a mode III.
The third embodiment comprises the following steps.
S501, the BMC host chip 100 and the flash chip 200 are powered on, and both the BMC host chip 100 and the flash chip 200 operate in a default operation mode (hereinafter, the mode operation mode is described as a mode three, which is an example), and the BMC host chip 100 and the flash chip 200 interact normally in this mode three.
S502, the BMC main chip 100 is restarted, the running mode of the BMC main chip 100 is reset to a default mode III, and the BMC main chip 100 sends register configuration information to the flash chip 200 through the SPI bus.
It should be noted that, the transmitted configuration information of the register is the configuration information for adjusting the operation mode of the flash chip 200 to the mode three, i.e. the configuration information of the register is reconfigured to 10. Before the BMC main chip 100 is restarted, the configuration information in the register of the flash chip 200 is also 10, namely the configuration information of the mode three, and the flash chip 200 still detects the configuration information of the register in real time.
S503, the flash chip 200 detects in real time whether the register configuration information is reconfigured.
S504, if the configuration information of the register is reconfigured, judging whether the new configuration information is the same as the previous configuration information;
s505, if the flash chip 200 determines that the new configuration information is the same as the previous configuration information, the flash chip 200 does not act.
S506, the BMC main chip 100 and the flash chip 200 continue normal interaction in the mode three.
The fourth embodiment comprises the following steps.
S601, the BMC main chip 100 and the flash chip 200 are powered on, and the BMC main chip 100 and the flash chip 200 both operate in a default operation mode (hereinafter, the mode operation mode is described as a mode three, which is an example), and the BMC main chip 100 and the flash chip 200 interact normally in this mode three.
S602, the BMC main chip 100 is restarted, the running mode of the BMC main chip 100 is reset to a default mode III, and the BMC main chip 100 sends register configuration information to the flash chip 200 through the SPI bus.
It should be noted that, the transmitted configuration information of the register is the configuration information for adjusting the operation mode of the flash chip 200 to the mode three, i.e. the configuration information of the register is reconfigured to 10. Before the BMC main chip 100 is restarted, the configuration information in the register of the flash chip 200 is also 10, namely the configuration information of the mode three, and the flash chip 200 still detects the configuration information of the register in real time.
S603, the flash chip 200 detects in real time whether the register configuration information is reconfigured.
S604, if the configuration information of the register is reconfigured, the flash chip 200 performs operation mode adjustment according to the new configuration information of the register.
It should be noted that, before and after the operation mode adjustment of the flash chip 200, the operation mode is the mode three, and the flash chip 200 operates the operation mode reconfiguration process once.
S605, the BMC main chip 100 and the flash chip 200 continue normal interaction in mode three.
Example III
Aiming at the core principle of the invention, the third embodiment provides a device for preventing the BMC image file from being damaged, which ensures that the running modes of the BMC main chip 100 and the flash chip 200 are consistent, and the BMC main chip 100 and the flash chip 200 can normally interact to erase and write data, thereby preventing the BMC image file in the flash chip 200 from being damaged.
As shown in fig. 2, the device for preventing the BMC image file from being damaged provided in the third embodiment includes the following functional modules.
The operation mode information transmission module 101: the method comprises the steps that when the BMC master chip 100 is operated, after the BMC master chip 100 is restarted, operation mode information is sent to the flash chip 200;
the operation module adjustment module 102: and the flash chip 200 is operated, and the operation mode is adjusted according to the received operation mode information.
After the BMC master chip 100 of the device is restarted, the operation mode information is actively sent to the flash chip 200, the flash chip 200 is informed of the operation mode required by the BMC master chip 100, the flash chip 200 adjusts the operation mode according to the received operation mode information, the adjusted operation mode is ensured to be the operation mode required by the BMC master chip 100, then the BMC master chip 100 and the flash chip 200 interact normally through the operation mode, the problem that the operation mode of the BMC master chip 100 is inconsistent with the operation mode of the flash chip is avoided, and therefore the problem that BMC mirror files in the flash chip 200 are damaged is avoided, the problem of damage to the BMC mirror files is fundamentally solved, server faults are avoided, stable operation of a server is ensured, and the operation efficiency is improved.
Example IV
In order to facilitate the detailed understanding of the present invention, the following describes a device for preventing a BMC image file from being damaged according to the principles of the present invention.
Specifically, a device for preventing a BMC image file from being damaged in the second embodiment includes the following functional modules.
First, the operation mode information transmitting module 101: and the operation is performed on the BMC master chip 100, and after the BMC master chip 100 is restarted, the operation mode information is sent to the flash chip 200.
Considering that the BMC host chip 100 and the flash chip 200 are connected through an SPI (Serial Peripheral Interface ) bus, the BMC host chip 100 in the functional module sends operation mode information to the flash chip 200, specifically:
the BMC host chip 100 transmits operation mode information to the flash chip 200 through the SPI bus.
That is, after the BMC main chip 100 is restarted, it communicates with the flash chip 200 through the SPI bus first, and the operation mode (for example, mode three) required by the BMC main chip 100 at this time is sent to the flash chip 200, so that the flash chip 200 adjusts its own operation mode. The operation mode required by the BMC host chip 100 refers to an operation state in which the operation state of the BMC host chip 100 is the operation state in which the operation mode interacts, for example, the BMC host chip 100 defaults to interact with the flash chip 200 in mode three.
The operation mode of the flash chip 200 corresponds to the configuration information in the register thereof, and the flash chip 200 adjusts the operation mode according to the configuration information in the register thereof, for example, four operation modes of the flash chip 200 respectively correspond to the configuration information in the register thereof as 00, 01, 10 and 11.
Based on this, the BMC master chip 100 sends operation mode information to the flash chip 200 through the SPI bus, specifically:
the BMC host chip 100 transmits register configuration information to the flash chip 200 through the SPI bus.
That is, after the BMC master chip 100 is restarted, the BMC master chip 100 sends the register configuration information to the flash chip 200 through the SPI bus, and reconfigures the register configuration in the flash chip 200. For example, if the default operation mode after the restart of the BMC master chip 100 is mode three, after the restart of the BMC master chip 100, the configuration information of the register sent by the BMC master chip 100 to the flash chip 200 through the SPI bus is to change the configuration in the register to mode 10.
And a second module, an operation module adjusting module 201: and the flash chip 200 is operated, and the operation mode is adjusted according to the received operation mode information.
After restarting the BMC master chip 100, the BMC master chip 100 sends register configuration information to the flash chip 200 through the SPI bus, the register configuration in the flash chip 200 is reconfigured, and the flash chip 200 adjusts the operation mode according to the received operation mode information, specifically, adjusts the operation mode according to the register configuration information. The flash chip 200 needs to timely determine whether the configuration information of the register is reconfigured, and when the flash chip is implemented, the functional module executes the following steps:
in step one, the flash chip 200 detects whether the register configuration information is reconfigured in real time.
It should be noted that, a time interval for the flash chip 200 to monitor the register configuration information, for example, detection once for 10 seconds or detection once for 1 minute, may be set, and the flash chip 200 implements the monitor register according to the set time interval to detect whether the register configuration information is reconfigured.
And step two, if the configuration is reconfigured, the operation mode is adjusted according to the new configuration information.
When the configuration information of the register is reconfigured, the flash chip 200 adjusts the operation mode according to the new configuration information of the register. For example, if the configuration information of the register is configured to be 10, the flash chip 200 adjusts its operation mode to be mode three, so as to ensure that the operation mode of the flash chip 200 is consistent with the operation mode of the BMC main chip 100, so that the two modes can interact normally, and damage to the BMC image file in the flash chip 200 is avoided.
It should be noted that, the flash chip 200 may determine whether the new configuration information is consistent with the previous configuration information (i.e. before the BMC main chip 100 is restarted), if so, the flash chip 200 does not operate any more, and if not, the operation mode is adjusted according to the new configuration information. Of course, the flash chip 200 may not determine whether the new configuration information is consistent with the previous configuration information, and only after the register configuration information is reconfigured, the operation mode may be readjusted according to the new configuration information.
After the BMC master chip 100 of the device is restarted, the operation mode information is actively sent to the flash chip 200, the flash chip 200 is informed of the operation mode required by the BMC master chip 100, the flash chip 200 adjusts the operation mode according to the received operation mode information, the adjusted operation mode is ensured to be the operation mode required by the BMC master chip 100, then the BMC master chip 100 and the flash chip 200 interact normally through the operation mode, the problem that the operation mode of the BMC master chip 100 is inconsistent with the operation mode of the flash chip is avoided, and therefore the problem that BMC mirror files in the flash chip 200 are damaged is avoided, the problem of damage to the BMC mirror files is fundamentally solved, server faults are avoided, stable operation of a server is ensured, and the operation efficiency is improved.
Example five
Fig. 3 is a schematic structural diagram of a terminal device 300 according to an embodiment of the present invention, where the terminal device 300 may be used to execute the method for preventing BMC image file damage according to the embodiment of the present invention.
The terminal apparatus 300 may include: a processor 310, a memory 320 and a communication unit 330. The components may communicate via one or more buses, and it will be appreciated by those skilled in the art that the configuration of the server as shown in the drawings is not limiting of the invention, as it may be a bus-like structure, a star-like structure, or include more or fewer components than shown, or may be a combination of certain components or a different arrangement of components.
The memory 320 may be used to store instructions for execution by the processor 310, and the memory 320 may be implemented by any type of volatile or non-volatile memory terminal or combination thereof, such as Static Random Access Memory (SRAM), electrically erasable programmable read-only memory (EEPROM), erasable programmable read-only memory (EPROM), programmable read-only memory (PROM), read-only memory (ROM), magnetic memory, flash memory, magnetic disk, or optical disk. The execution of the instructions in memory 320, when executed by processor 310, enables terminal 300 to perform some or all of the steps in the method embodiments described below.
The processor 310 is a control center of the storage terminal, connects various parts of the entire electronic terminal using various interfaces and lines, and performs various functions of the electronic terminal and/or processes data by running or executing software programs and/or modules stored in the memory 320, and invoking data stored in the memory. The processor may be comprised of an integrated circuit (Integrated Circuit, simply referred to as an IC), for example, a single packaged IC, or may be comprised of a plurality of packaged ICs connected to the same function or different functions. For example, the processor 310 may include only a central processing unit (Central Processing Unit, simply CPU). In the embodiment of the invention, the CPU can be a single operation core or can comprise multiple operation cores.
And a communication unit 330 for establishing a communication channel so that the storage terminal can communicate with other terminals. Receiving user data sent by other terminals or sending the user data to other terminals.
Example six
The present invention also provides a computer storage medium in which a program may be stored, which program may include some or all of the steps in the embodiments provided by the present invention when executed. The storage medium may be a magnetic disk, an optical disk, a read-only memory (ROM), a random-access memory (random access memory, RAM), or the like.
It will be apparent to those skilled in the art that the techniques of embodiments of the present invention may be implemented in software plus a necessary general purpose hardware platform. Based on such understanding, the technical solution in the embodiments of the present invention may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium such as a U-disc, a mobile hard disc, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk or an optical disk, etc. various media capable of storing program codes, including several instructions for causing a computer terminal (which may be a personal computer, a server, or a second terminal, a network terminal, etc.) to execute all or part of the steps of the method described in the embodiments of the present invention.
The same or similar parts between the various embodiments in this specification are referred to each other. In particular, for the terminal embodiment, since it is substantially similar to the method embodiment, the description is relatively simple, and reference should be made to the description in the method embodiment for relevant points.
In the several embodiments provided by the present invention, it should be understood that the disclosed systems, devices, and methods may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.
The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional unit in the embodiments of the present invention may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.
The foregoing disclosure is merely illustrative of the preferred embodiments of the invention and the invention is not limited thereto, since modifications and variations may be made by those skilled in the art without departing from the principles of the invention.

Claims (9)

1. A method for preventing BMC image file corruption, comprising the steps of:
after restarting the BMC main chip, the BMC main chip sends operation mode information to the flash chip;
the flash chip adjusts the operation mode according to the received operation mode information, and specifically comprises the following steps: the flash chip detects whether the register configuration information is reconfigured in real time, and if so, the operation mode is adjusted according to the new configuration information;
wherein the operation mode includes: bit command mode, 3/4 byte address mode, performance enhancement mode, continuous read mode.
2. The method for preventing damage to a BMC image file according to claim 1, wherein the BMC master chip sends operation mode information to the flash chip, specifically:
and the BMC main chip sends operation mode information to the flash chip through the SPI bus.
3. The method for preventing the BMC image file from being damaged according to claim 2, wherein the BMC master chip sends the operation mode information to the flash chip through the SPI bus, specifically:
and the BMC main chip sends the register configuration information to the flash chip through the SPI bus.
4. An apparatus for preventing BMC image file damage, comprising,
an operation mode information sending module: the method comprises the steps that the method operates on a BMC main chip, and after the BMC main chip is restarted, operation mode information is sent to a flash chip;
the operation module adjusting module: the operation mode is adjusted according to the received operation mode information, and the operation mode is specifically as follows: the flash chip detects whether the register configuration information is reconfigured in real time, and if so, the operation mode is adjusted according to the new configuration information;
wherein the operation mode includes: bit command mode, 3/4 byte address mode, performance enhancement mode, continuous read mode.
5. The device for preventing BMC image file damage according to claim 4, wherein the operation mode information transmitting module transmits operation mode information to the flash chip, specifically:
and sending the operation mode information to the flash chip through the SPI bus.
6. The device for preventing BMC image file damage according to claim 5, wherein the operation mode information is sent to the flash chip through the SPI bus, specifically:
and sending the register configuration information to the flash chip through the SPI bus.
7. The apparatus for preventing BMC image file damage according to claim 6, wherein the operation module adjusting module adjusts the operation mode according to the received operation mode information, specifically:
detecting in real time whether a register is reconfigured;
if so, the operating mode is adjusted according to the new configuration information.
8. A terminal, comprising:
a processor;
a memory for storing execution instructions of the processor;
wherein the processor is configured to perform the method of any of claims 1-3.
9. A computer readable storage medium storing a computer program, which when executed by a processor implements the method of any one of claims 1-3.
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